CN102832243B - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN102832243B CN102832243B CN201110159506.3A CN201110159506A CN102832243B CN 102832243 B CN102832243 B CN 102832243B CN 201110159506 A CN201110159506 A CN 201110159506A CN 102832243 B CN102832243 B CN 102832243B
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Abstract
The invention discloses a kind of semiconductor device, comprise the gate stack structure be arranged on substrate, be positioned at gate isolation side wall around gate stack structure, be positioned at the source-drain area of gate stack structure both sides, be positioned at the epitaxially grown source and drain contact of described source-drain area, it is characterized in that: the compound that the contact of described source and drain is nickel based metal and backing material, be arranged in described source-drain area and with described gate isolation side wall below channel region contacts.According to semiconductor device of the present invention and manufacture method thereof, the material of the compound that nickel based metal and backing material are formed and thickness due to Reasonable adjustment, formed source and drain contact is made to possess good thermal stability, the second high annealing eliminating high k grid dielectric material layer defects can be stood, thus significantly reduce source and drain dead resistance, improve the electric property of device.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of semiconductor device and the manufacture method thereof with contact material in the source-drain area of thermal stability.
Background technology
Along with dimensions of semiconductor devices reduces further, various ghost effect becomes more and more outstanding, seriously limits the raising of device electric property.Progressively be reduced to sub-30nm along with device size especially physical gate is long, source and drain spurious impedance increases gradually, and in whole Transistor Impedance, proportion continues to raise, and having exceeded channel region impedance becomes the significant bottleneck that constraint device performance improves further.Therefore, how the significant challenge that source and drain spurious impedance becomes device performance raising is effectively reduced.
The method of traditional reduction source and drain impedance comprises carries out heavy doping for source-drain area as much as possible, reduces source-drain area resistance, thus avoid equivalent operation voltage drop by high-concentration dopant ion.But because solid solubility limit and short-channel effect control to need dopant profiles to suddenly change, the effect that this doping reduces impedance methodologies becomes more and more restricted.
Fig. 1 a and Fig. 1 b is depicted as the generalized section of existing semiconductor device.As shown in Figure 1a, shallow trench isolation is formed from (STI) 2 in silicon substrate 1, pad oxide, grid and cap rock is deposited in the active area that STI2 surrounds, etching forms gate stack, gate stack is utilized to carry out first time source and drain ion implantation formation light-dope structure LDD, then deposit and etch and form grid curb wall 3, carry out second time source and drain ion implantation and form heavily doped source-drain area 4, nickel deposited Base Metal on source-drain area 4 is also annealed thus form nickel based metal silicide 5 in source-drain area 4, be such as NiSi or NiPtSi, to reduce contact resistance.As shown in Figure 1 b, along with channel length and gate length continual reductions, the junction depth X of source-drain area 4
jalso scaled down while, makes the thickness of nickel based metal silicide 5 also reduce accordingly.
But, due to metal silicide particularly nickel based metal suicide surfaces triggering can be caused phase transformation, along with on source-drain area 4, silicide film is thinning, and its thermal stability is phase strain differential also, experience high temperature time easily condense into block and increase impedance.For the long channel device shown in Fig. 1 a, the junction depth in heavy-doped source drain region is larger, and the silicide of contact is also corresponding thicker, and therefore better heat stability, can bear the high temperature of subsequent technique.But for the short channel device shown in Fig. 1 b, heavy-doped source drain region junction depth is more shallow, the silicide of contact is corresponding thinner, therefore poor heat stability, be difficult to the high annealing bearing subsequent technique, in rear grid technique, such as eliminate the high annealing that high k gate dielectric defect is used, thus condense into block and increase impedance, therefore short channel device penalty.
Generally speaking, the metal silicide poor heat stability of current short channel device, device performance is subject to significant impact.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of semiconductor device and the manufacture method thereof that effectively can improve metal silicide thermal stability in source-drain area.
The invention provides a kind of semiconductor device, comprise the gate stack structure be arranged on substrate, be positioned at gate isolation side wall around gate stack structure, be positioned at the source-drain area of gate stack structure both sides, be positioned at the epitaxially grown source and drain contact of described source-drain area, it is characterized in that: the compound that the contact of described source and drain is metal and backing material, be arranged in described source-drain area and with described gate isolation side wall below channel region contacts.
Wherein, described substrate is Si or SOI, and described source and drain contact is epitaxially grown metal silicide, and its material is NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1.
Wherein, described substrate is Ge or GOI, and described source and drain contact is epitaxially grown metal germanide, and its material is NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1.
Wherein, described substrate is SiGe, and described source and drain contact is epitaxially grown SiGe alloy, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1, z and is all greater than 0 and is less than 1.
Wherein, the thickness of described source and drain contact is less than or equal to 15nm.Wherein, described source-drain area is the heavy-doped source drain region with LDD structure.Wherein, described source-drain area is the lifting source and drain of selective epitaxial growth.Wherein, described source-drain area junction depth is less than or equal to 20nm.Wherein, described gate stack structure width is less than or equal to 30nm.
Present invention also offers a kind of method, semi-conductor device manufacturing method, comprising: on substrate, form gate stack structure; Gate isolation side wall is formed around described gate stack structure; Source-drain area is formed in described gate isolation side wall both sides; Described gate stack structure, described gate isolation side wall and described source-drain area form metal level; Perform annealing, nickel based metal layer and the backing material in described source-drain area are reacted form epitaxially grown source and drain to contact; And divest unreacted described metal level, the contact of described source and drain be arranged in described source-drain area and with described gate isolation side wall below channel region contacts.
Wherein, described substrate is Si or SOI, and described source and drain contact is epitaxially grown metal silicide, and its material is NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1.
Wherein, described substrate is Ge or G0I, and described source and drain contact is epitaxially grown metal germanide, and its material is NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1.
Wherein, described substrate is SiGe, and described source and drain contact is epitaxially grown SiGe alloy, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1, z and is all greater than 0 and is less than 1.
Wherein, described metal level comprises Ni, Co, NiPt, NiCo, and described metal layer thickness is less than 5nm.Wherein, described source-drain area is the heavy-doped source drain region with LDD structure.Wherein, described source-drain area is the lifting source and drain of selective epitaxial growth.Wherein, described source-drain area junction depth is less than or equal to 20nm.Wherein, described gate stack structure width is less than or equal to 30nm.
Wherein, described annealing temperature is 400 DEG C to 850 DEG C.
According to semiconductor device of the present invention and manufacture method thereof, the material of the compound that nickel based metal and backing material are formed and thickness due to Reasonable adjustment, formed source and drain contact is made to possess good thermal stability, the second high annealing eliminating high k grid dielectric material layer defects can be stood, thus significantly reduce source and drain dead resistance, improve the electric property of device.
Object of the present invention, and in these other unlisted objects, met in the scope of the application's independent claims.Embodiments of the invention limit in the independent claim, and specific features limits in dependent claims thereto.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 shows the generalized section of the MOSFETs of prior art; And
Fig. 2 to Fig. 4 shows the generalized section of each processing step of MOSFETs according to manufacture of the present invention with thermal stability metal silicide in source-drain area.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclose semiconductor device and the manufacture method thereof that effectively can improve metal silicide thermal stability in source-drain area.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or processing step.These modify the space of not hint institute's modification device architecture or processing step unless stated otherwise, order or hierarchical relationship.
First, with reference to accompanying drawing 2, form the basic device architecture with heavy doping source and drain.Have such as the conventional method deposition of shallow trench isolation by such as CVD on the substrate 10 of the isolation structure 20 of (STI) forms gate dielectric layer 30.Wherein substrate 10 can be silicon (Si), silicon-on-insulator (SOI), also can be germanium (Si), germanium on insulator (GOI), or SiGe.Except STI, isolation structure 20 can also adopt LOCOS technique to form thermal oxide isolation, but for small size device, or preferably use STI.Gate dielectric layer 30 material can be silicon dioxide conventional in CMOS technology, and also can be the high k grid dielectric material used in small size device, such as, be HfO
2, HfSiON, La
2o
3, Ta
2o
5, barium titanate BTO etc. or its combination.By CVD deposition of gate metal level 40 on gate dielectric layer 30, its material needs according to semiconductor device electric property and determines, particularly, selected metal material is carried out by the gate work-function of decision threshold voltage, can be Ti, Ta, W, Al, Cu, TiAl etc. metal and alloy, can also be the nitride of these metals, it can be individual layer also can be multilayer lamination structure.Seed layer or the depletion layer (not shown) of metal or metal nitride can also be formed, for strengthening bond strength and preventing metallic from diffusing into substrate channel between gate metal layer 40 and gate dielectric layer 30.Adopt conventional mask etching technics to form the gate stack structure overlapped by gate dielectric layer 30 and gate metal layer 40, for small size device of the present invention, grid length Lg is less than 30nm usually.Be that mask carries out first time source and drain Doped ions injection with gate stack structure, Implantation Energy is lower, and the source-drain area of formation is more shallow, also namely forms light-dope structure LDD.Uniform deposition spacer material 50 on gate stack structure and substrate 10, its material is oxide or nitride normally, such as silica (SiO), silicon nitride (SiN) or silicon oxynitride (SiON) or its combination, preferably have and substrate 10 and the high material of gate dielectric layer 30 etching selection ratio, chemical wet etching forms grid curb wall 50 in gate stack structure side periphery subsequently.Utilize grid curb wall 50 and gate stack structure to be mask, carry out second time source and drain Doped ions and inject, Implantation Energy is higher, and the source-drain area of formation is comparatively dark, therefore forms the heavy-doped source drain region 60 with LDD.The kind that twice source and drain Doped ions injects, dosage and Implantation Energy are according to the kind of the source-drain area 60 that will be formed, resistivity, the degree of depth and determine, and such as control implantation dosage and energy make the junction depth Xj of source-drain area 60 be less than or equal to 20nm.
It should be noted that, although the source-drain area 60 of illustrated embodiment is arranged in the substrate 10 of both sides below gate stack structure as shown in Figure 2 in the present invention, but for other particular device structure, source-drain area 60 also can be lifting source and drain (RSD), such as, after forming gate stack structure on substrate, formed higher than the lifting source and drain (not shown in Fig. 2) of substrate level in types of flexure, gate stack structure both sides by selective epitaxial (SEG) technology, then carry out twice similar ion implantation to form the source-drain area 60 with heavily doped region.
Secondly, as shown in Figure 3, the metal level of deposition of thin.Total also namely on source-drain area 60, STI20, gate metal layer 40 and gate isolation side wall 50 such as by the thin metal layer 70 of CVD deposition for the formation of epitaxially grown ultra-thin contact material.The material of thin metal layer 70 can be cobalt (Co), nickel (Ni), nickel platinum alloy (Ni-Pt, wherein Pt content is less than or equal to 8%), nickel cobalt (alloy) (Ni-Co, wherein Co content is less than or equal to 10%) or nickel platinum cobalt ternary-alloy, thickness can be less than 5nm and preferably be less than or equal to 4nm.Particularly, thin metal layer 70 can be thickness is less than the Co of 5nm, thickness is less than or equal to 4nm Ni, thickness is less than or equal to the Ni-Co that the Ni-Pt of 4nm or thickness are less than or equal to 4nm.
Then, annealing forms epitaxially grown super thin metal silicide and divests unreacted thin metal layer.As shown in Figure 3, high annealing is carried out at 400 DEG C to 850 DEG C, the thin metal layer 70 of deposition reacts to the backing material in source-drain area 60 and extension generates corresponding epitaxially grown ultra-thin source and drain contact material, divest the part of unreacted thin metal layer 70, gate stack structure both sides leave ultra-thin epitaxially grown source and drain contact 80 over the substrate 10.From in Fig. 3, ultra-thin source and drain contact 80 contacts with the raceway groove below grid curb wall 50, and also namely source and drain contact 80 is parallel with the side of grid curb wall 50 along the interface of channel direction with source-drain area 60 particularly, is preferably coplanar.The ultra-thin source and drain contact that extension generates is different according to thin metal layer 70 and substrate 10 material difference, and particularly, for the substrate 10 of Si or SOI, source and drain contact 80 is epitaxially grown metal silicides, and its material can be NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1; For the substrate 10 of Ge or GOI, source and drain contact 80 is epitaxially grown metal germanide, and concrete material can be NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1; For the substrate 10 of SiGe, source and drain contact 80 is epitaxially grown SiGe alloys, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1, z and is all greater than 0 and is less than 1.The thickness of epitaxially grown ultra-thin source and drain contact 80 is 1 to 15nm.
It should be noted that, the annealing of the higher temperatures of carrying out in the process of the ultra-thin source and drain contact 80 of epitaxial growth, except impelling except thin metal layer 70 and Si, Ge or the SiGe in source-drain area 60 react, also eliminate the extrinsic surface state that in substrate 10 superficial layer, defect causes, therefore inhibit the pinning effect (pipingeffect) that the Ni-based silicide process of autoregistration has usually.In addition, the material of thin metal layer 70 and thickness due to conservative control, and have employed the annealing of higher temperatures, the high temperature second that the epitaxially grown ultra-thin source and drain contact 80 therefore formed can stand to carry out to improve high k grid dielectric property in subsequent technique is annealed.
Afterwards, adopt same as the prior art or similar process deposits interlayer dielectric layer (IDL), in IDL, form contact openings, in the contact openings, which plated metal embolism to form source and drain Metal Contact.It should be noted that, although the technique that the embodiment of the present invention is lifted is first grid technique (gate-first), also namely first form gate metal layer and form source and drain again, but the technology of the ultra-thin source and drain contact of epitaxially grown thermal stability of the present invention also may be used for the rear grid technique (gate-last) developed at top speed now, also remove dummy gate again after namely forming the dummy gate of polysilicon, formation source and drain and form metal gate, wherein can replace the metal gates 40 in Fig. 1 embodiment of the present invention with the dummy gate of polysilicon.
The Novel MOS FET device structure formed according to manufacture method as above of the present invention as shown in Figure 3.There is shallow trench isolation from (STI) 20 in substrate 10; Be formed with the heavy-doped source drain region 60 with LDD structure in active area in substrate 10 between STI20, substrate 10 part between source-drain area 60 forms the channel region of semiconductor device, and in source-drain area 60, epitaxial growth has ultra-thin source and drain contact 80; The gate stack structure that substrate 10 is formed is between source-drain area 60, and gate stack structure comprises gate dielectric layer 30 and gate metal layer 40, and gate dielectric layer 30 can be high k grid dielectric materials layer, and material is such as HfO
2, HfSiON, La
2o
3, Ta
2o
5, barium titanate BTO etc. or its combination; Gate metal layer 40, its material needs according to semiconductor device electric property and determines, particularly, selected metal material is carried out by the gate work-function of decision threshold voltage, can be Ti, Ta, W, Al, Cu, TiAl etc. metal and alloy, can also be the nitride of these metals, it can be individual layer also can be multilayer lamination structure; The side periphery of gate stack structure is formed with gate isolation side wall 50; The ultra-thin source and drain contact that extension generates is different according to thin metal layer 70 and substrate 10 material difference, and particularly, for the substrate 10 of Si or SOI, source and drain contact 80 is epitaxially grown metal silicides, and its material can be NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1; For the substrate 10 of Ge or GOI, source and drain contact 80 is epitaxially grown metal germanide, and concrete material can be NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1; For the substrate 10 of SiGe, source and drain contact 80 is epitaxially grown SiGe alloys, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1, z and is all greater than 0 and is less than 1; The thickness of epitaxially grown ultra-thin source and drain contact 80 is 1 to 15nm; Source and drain contact 80 contacts with the raceway groove below gate isolation side wall 50.
According to semiconductor device of the present invention and manufacture method thereof, the material of the compound that nickel based metal and backing material are formed and thickness due to Reasonable adjustment, formed source and drain contact is made to possess good thermal stability, the second high annealing eliminating high k grid dielectric material layer defects can be stood, thus significantly reduce source and drain dead resistance, improve the electric property of device.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.
Claims (17)
1. a semiconductor device, comprise the gate stack structure be positioned on substrate, be positioned at the gate isolation side wall around gate stack structure, be positioned at the source-drain area of gate stack structure both sides, be arranged in the epitaxially grown source and drain contact of described source-drain area, it is characterized in that: described source and drain contact is the compound of nickel based metal and backing material, be arranged in described source-drain area and with described gate isolation side wall below channel region contacts, described source and drain contact possesses good thermal stability, the second high annealing eliminating high k grid dielectric material layer defects can be stood, source and drain contact extends in the source-drain area below gate isolation side wall, described source-drain area junction depth is less than or equal to 20nm.
2. semiconductor device as claimed in claim 1, wherein, described substrate is Si or SOI, and described source and drain contact is epitaxially grown metal silicide, and its material is NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1.
3. semiconductor device as claimed in claim 1, wherein, described substrate is Ge or GOI, and described source and drain contact is epitaxially grown metal germanide, and its material is NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1.
4. semiconductor device as claimed in claim 1, wherein, described substrate is SiGe, and described source and drain contact is epitaxially grown SiGe alloy, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1, z and is all greater than 0 and is less than 1.
5. semiconductor device as claimed in claim 1, wherein, the thickness of described source and drain contact is less than or equal to 15nm.
6. semiconductor device as claimed in claim 1, wherein, described source-drain area is the heavy-doped source drain region with LDD structure.
7. semiconductor device as claimed in claim 1, wherein, described source-drain area is the lifting source and drain of selective epitaxial growth.
8. semiconductor device as claimed in claim 1, wherein, described gate stack structure width is less than or equal to 30nm.
9. a method, semi-conductor device manufacturing method, comprising:
Substrate forms gate stack structure;
Gate isolation side wall is formed around described gate stack structure;
Source-drain area is formed in described gate isolation side wall both sides;
Described gate stack structure, described gate isolation side wall and described source-drain area form nickel based metal layer;
Perform annealing, described nickel based metal layer and the backing material in described source-drain area are reacted form epitaxially grown source and drain to contact, source and drain contact extends in the source-drain area below gate isolation side wall; And
Divest unreacted described metal level, the contact of described source and drain be arranged in described source-drain area and with described gate isolation side wall below channel region contacts, described source and drain contact possesses good thermal stability, can stand the second high annealing eliminating high k grid dielectric material layer defects, described source-drain area junction depth is less than or equal to 20nm.
10. method, semi-conductor device manufacturing method as claimed in claim 9, described substrate is Si or SOI, and described source and drain contact is epitaxially grown metal silicide, and its material is NiSi
2-y, Ni
1-xpt
xsi
2-y, CoSi
2-yor Ni
1-xco
xsi
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1.
11. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described substrate is Ge or GOI, and described source and drain contact is epitaxially grown metal germanide, and its material is NiGe
2-y, Ni
1-xpt
xge
2-y, CoGe
2-yor Ni
1-xco
xge
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1.
12. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described substrate is SiGe, and described source and drain contact is epitaxially grown SiGe alloy, and its material is Ni (Si
1-zge
z)
2-y, Ni
1-xpt
x(Si
1-zge
z)
2-y, Co (Si
1-zge
z)
2-yor Ni
1-xco
x(Si
1-zge
z)
2-y, wherein x is all greater than 0 and is less than 1, y and is all greater than 0 and is less than 1, z and is all greater than 0 and is less than 1.
13. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described metal level comprises Ni, Co, NiPt, NiCo, and described metal layer thickness is less than 5nm.
14. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described source-drain area is the heavy-doped source drain region with LDD structure.
15. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described source-drain area is the lifting source and drain of selective epitaxial growth.
16. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, described gate stack structure width is less than or equal to 30nm.
17. method, semi-conductor device manufacturing methods as claimed in claim 9, wherein, the annealing temperature of described formation source and drain contact is 400 DEG C to 850 DEG C.
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