CN102832102B - Method for determining aging conditions of field effect transistor, field effect transistor aging method and field effect transistor screening method - Google Patents
Method for determining aging conditions of field effect transistor, field effect transistor aging method and field effect transistor screening method Download PDFInfo
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Abstract
The invention discloses a method for determining aging conditions of a field effect transistor, a field effect transistor aging method and a field effect transistor screening method. Multiple different direct current powers are applied to the field effect transistor at the preset temperature of an aging table, and peak junction temperatures corresponding to the direct current powers are further detected, so that a relation equation among the temperature of the aging table, the direct current power and the peak junction temperature can be obtained. The temperature of the aging table during aging and the direct current power value to be applied to the field effect transistor can be determined by using the obtained relation equation according to the highest allowable junction temperature of the field effect transistor, and the high-efficient aging of the field effect transistor can be further realized.
Description
Technical field
The present invention relates to device reliability technical field, particularly relate to a kind of method, field effect transistor aging method and the field effect transistor screening technique of determining field effect transistor aging condition.
Background technology
Burin-in process will be carried out after encapsulation, object has two: on the one hand device through certain condition aging after, realize stablizing component characteristic parameter, on the other hand by rejecting early failure or the device that there is inefficacy hidden danger, realize the reliability screening of device.
What the aging method of usual device adopted is steady state power aging techniques, namely device is under certain agingtable temperature conditions, within the longer time, certain direct current power is applied continuously to field effect transistor, the various physics and chemistry process of device inside is accelerated by electricity, hot comprehensive function, impel the various latent defect of device inside to expose early, thus reach the object rejecting early failure device.Wherein, agingtable temperature and the direct current power for device applying are the aging conditions of field effect transistor.
When ambient temperature-stable, the large young pathbreaker of input direct-current power directly affects the effect of burin-in process.Input direct-current power is excessive, and the Peak Junction Temperature of field effect transistor will exceed maximum allowable junction temperature, device may be caused to burn, make aging failure.If input direct-current power is too small, the Peak Junction Temperature of field effect transistor will much smaller than maximum allowable junction temperature, and device possibly cannot reach effective aging effect, is difficult to the Effective selection realizing device.That is, existing field effect transistor aging method well cannot determine aging condition, causes device to carry out effectively aging.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of and determines the method for field effect transistor aging condition, a kind of field effect transistor aging method and a kind of field effect transistor screening technique, and to realize the efficiently aging of field effect transistor and Effective selection, technical scheme is as follows:
Determine a method for field effect transistor aging condition, comprising:
At default agingtable temperature, be the drain terminal voltage that field effect transistor input is preset;
Change the grid voltage of field effect transistor;
Detect under different grid voltage, the Peak Junction Temperature of field effect transistor under the direct current power of this field effect transistor and this direct current power, obtain agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
Agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
According to the maximum allowable junction temperature of this field effect transistor, described governing equation is used to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value.
Preferably, described field effect transistor is GaN base transistor with high electronic transfer rate.
Preferably, described at default agingtable temperature, the drain terminal voltage preset for field effect transistor input is specially: at default agingtable temperature, uses the drain terminal voltage with suppressing the supply module of oscillating circuit to be preset for field effect transistor input.
Preferably, the grid voltage of described change field effect transistor is specially: use the grid voltage with suppressing the supply module of oscillating circuit to change field effect transistor.
Preferably, the method detecting this field effect transistor Peak Junction Temperature is: use infrared microscopy measuring element to detect the Peak Junction Temperature of this field effect transistor.
Preferably, described agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature, be specially: according to described many groups the agingtable temperature tackled mutually, direct current power value and Peak Junction Temperature, use this field effect transistor agingtable temperature of mathematical analysis software calculating acquisition of Origin, the governing equation between direct current power and Peak Junction Temperature.
Present invention also offers a kind of field effect transistor aging method, comprising:
The method of the determination field effect transistor aging condition of claim 1 is used to determine to need the agingtable temperature corresponding to aging field effect transistor and direct current power value;
At described agingtable temperature, for this field effect transistor input drain terminal voltage and the grid voltage adjusting described field effect transistor makes the direct current power of this field effect transistor be described direct current power value;
In preset time period, continue aging to described field effect transistor.
Preferably, described field effect transistor is GaN base transistor with high electronic transfer rate.
Preferably, to be describedly specially for this field effect transistor input drain terminal voltage: use with suppressing the supply module of oscillating circuit to input drain terminal voltage for this field effect transistor.
Preferably, the grid voltage of the described field effect transistor of described adjustment is specially: use the grid voltage with suppressing the supply module of oscillating circuit to adjust described field effect transistor.
Present invention also offers a kind of field effect transistor screening technique, comprising:
At default agingtable temperature, be the drain terminal voltage that field effect transistor input is preset;
Change the grid voltage of field effect transistor;
Detect under different grid voltage, the Peak Junction Temperature of field effect transistor under the direct current power of this field effect transistor and this direct current power, obtain agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
Agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
According to the maximum allowable junction temperature of this field effect transistor, described governing equation is used to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value;
By agingtable temperature corresponding to the maximum allowable junction temperature of this field effect transistor and this field effect transistor maximum allowable junction temperature and direct current power value input formula T
j=PR
th(j-c)+T
cin calculate the thermal resistance of this field effect transistor, wherein, T
jfor the Peak Junction Temperature of field effect transistor; P is the direct current power of field effect transistor; R
th(j-c) be the thermal resistance of field effect transistor under certain power condition; T
cfor agingtable temperature;
When the thermal resistance of field effect transistor is greater than preset value, this field effect transistor is substandard product.
By applying above technical scheme, provided by the inventionly a kind ofly determine the method for field effect transistor aging condition, a kind of field effect transistor aging method and a kind of field effect transistor screening technique, can by the agingtable temperature preset, for field effect transistor applies multiple different direct current power, and detect the Peak Junction Temperature corresponding with direct current power, thus acquisition agingtable temperature, governing equation between direct current power and Peak Junction Temperature.Only need the maximum allowable junction temperature according to field effect transistor, obtained governing equation just can be used to determine the temperature of aging middle agingtable and the direct current power value needed for field effect transistor applies, thus achieve the efficiently aging of field effect transistor.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart determining the method for field effect transistor aging condition provided by the invention;
Fig. 2 is that the Peak Junction Temperature that obtains of a kind of method determining field effect transistor aging condition provided by the invention is with the graph of a relation between direct current power;
Fig. 3 is a kind of graph of a relation determining the direct current power that the method for field effect transistor aging condition obtains and thermal resistance provided by the invention;
Fig. 4 is the flow chart of a kind of field effect transistor aging method provided by the invention;
Fig. 5 is the flow chart of a kind of field effect transistor screening technique provided by the invention.
Embodiment
Technical scheme in the present invention is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
Method, field effect transistor aging method and the field effect transistor screening technique determining field effect transistor aging condition provided by the present invention is applicable to field effect transistor, is particularly useful for GaN base transistor with high electronic transfer rate (GaN base HEMT).
As shown in Figure 1, a kind of method determining field effect transistor aging condition provided by the invention, comprising:
S101, at default agingtable temperature, be field effect transistor input preset drain terminal voltage;
Wherein, described field effect transistor can be GaN base HEMT.
It should be noted that, when default agingtable temperature is aging field effect transistor, the ambient temperature residing for field effect transistor.Certainly, under different aging requirements, device property and radiating condition, corresponding default agingtable temperature is also different.Those skilled in the art can adjust according to actual needs.
Wherein, under default ambient temperature, the drain terminal voltage preset for field effect transistor input can be specially: at default agingtable temperature, and device is fixed on the fixture of the supply module with suppression oscillating circuit, applies direct current power by DC power supply to device.Field effect transistor in working order under, certain self-oscillation can be produced, use and suppress oscillating circuit effectively can suppress self-oscillation, ensure the normal operation of field effect transistor.
The grid voltage of S102, change field effect transistor;
It will be appreciated by persons skilled in the art that the grid voltage changing field effect transistor can control the output of field effect transistor drain terminal electric current, thus according to leakage current and drain terminal voltage determination direct current power.
Wherein, the grid voltage changing field effect field effect transistor can be specially: use the grid voltage with suppressing the supply module of oscillating circuit to change field effect transistor.
S103, detect under different grid voltage, under the direct current power of this field effect transistor and this direct current power, the Peak Junction Temperature of field effect transistor, obtains agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
Wherein, direct current power can be drawn by following formulae discovery:
P＝I
dsV
ds
In above formula, P is direct current power, I
dsfor drain terminal electric current, V
dsfor drain terminal voltage.
In addition, the method detecting this field effect transistor Peak Junction Temperature can be: use infrared microscopy measuring element to detect the Peak Junction Temperature of this field effect transistor.In actual applications, infrared microscopy measuring element can be thermal microscope.Thermal microscope is distributed by the radiant energy density of detection means, is converted into the temperature value of device surface each point by computer software, thus the Temperature Distribution on determining device surface, and then the Peak Junction Temperature of determining device and the position at device surface thereof.In actual applications, the temperature distribution state of device surface also can provide foundation for the screening of field effect transistor, as: if certain field effect transistor Temperature Distribution is very uneven, occur multiple focus, then this field effect transistor is substandard product.
S104, agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
In actual applications, this field effect transistor agingtable temperature of mathematical analysis software calculating acquisition of Origin, the governing equation between direct current power and Peak Junction Temperature can be used.
It should be noted is that, Origin is a kind of mathematical analysis software, is undertaken fitting calculating, thus obtain the regularity between each parameter by quantity of parameters.It has with a high credibility, calculate feature efficiently.Certainly, in actual applications, other mathematic calculation or software also can be adopted to obtain governing equation.
Fig. 2 of the present inventionly a kind ofly determines that the method for field effect transistor aging condition obtains the Peak Junction Temperature of two kinds of field effect transistor with the graph of a relation between direct current power.Thermal resistance also embodies an important parameter of electronic reliability, in actual applications, and can also according to following equation determination thermal resistance with the relation between direct current power.
T
j＝PR
th(j-c)+T
c
Wherein, T
jfor the Peak Junction Temperature of field effect transistor; P is the direct current power of field effect transistor; R
th(j-c) be the thermal resistance of field effect field effect transistor field effect transistor under certain power condition; T
cfor agingtable temperature.
The graph of a relation of these two kinds of field effect transistor direct current powers that Fig. 3 calculates with the relation between direct current power for the Peak Junction Temperature of field effect transistor that provides according to Fig. 2 and thermal resistance.
S105, maximum allowable junction temperature according to this field effect transistor, use described governing equation to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value.
It will be appreciated by persons skilled in the art that field effect transistor is owing to making the difference of material, technique and other electric parameters, its maximum allowable junction temperature that can bear also is different.After producing, its maximum allowable junction temperature also just determines a kind of field effect transistor.
A kind of method determining field effect transistor aging condition provided by the invention, can by the agingtable temperature preset, for field effect transistor applies multiple different direct current power, and detect the Peak Junction Temperature corresponding with direct current power, thus acquisition agingtable temperature, governing equation between direct current power and Peak Junction Temperature.Only need the maximum allowable junction temperature according to field effect transistor, obtained governing equation just can be used to determine the temperature of aging middle agingtable and the direct current power value needed for field effect transistor applies, thus achieve the efficiently aging of field effect transistor.
As shown in Figure 4, present invention also offers a kind of field effect transistor aging method, comprising:
The method of the determination field effect transistor aging condition of S201, use claim 1 is determined to need the agingtable temperature corresponding to aging field effect transistor and direct current power value;
Wherein, field effect transistor can be the field effect transistor of GaN base HEMT device or other epitaxial materials.
S202, at described agingtable temperature, for this field effect transistor input drain terminal voltage and the grid voltage adjusting described field effect transistor makes the direct current power of this field effect transistor be described direct current power value;
Wherein, field effect transistor input drain terminal voltage can be specially: use with suppressing the supply module of oscillating circuit for field effect transistor input drain terminal voltage.The grid voltage of adjustment field effect transistor can be specially: use the grid voltage with the supply module adjustment field effect transistor suppressing oscillating circuit.This fixture can fixedly need to carry out aging device, and power supply is that device is powered by fixture.
S203, in preset time period, continue aging to described field effect transistor.
It will be appreciated by persons skilled in the art that the aging aging effect needing the lasting regular hour can reach predetermined of field effect transistor.The requirement of different field effect transistor to ageing time is also not quite similar, and the present invention is in this no limit.
A kind of field effect transistor aging method provided by the invention, can by the agingtable temperature preset, for field effect transistor applies multiple different direct current power, and detect the Peak Junction Temperature corresponding with direct current power, thus acquisition agingtable temperature, governing equation between direct current power and Peak Junction Temperature.Only need the maximum allowable junction temperature according to field effect transistor, obtained governing equation just can be used to determine the temperature of aging middle agingtable and the direct current power value needed for field effect transistor applies, thus achieve the efficiently aging of field effect transistor.
As shown in Figure 5, a kind of field effect transistor screening technique provided by the invention, comprising:
S301, at default agingtable temperature, be field effect transistor input preset drain terminal voltage;
The grid voltage of S302, change field effect transistor;
S303, detect under different grid voltage, the Peak Junction Temperature of field effect transistor under this direct current power of the direct current power of this field effect transistor, obtain agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
S304, agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
S305, maximum allowable junction temperature according to this field effect transistor, use described governing equation to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value;
S306, by the maximum allowable junction temperature of this field effect transistor and agingtable temperature corresponding to this field effect transistor maximum allowable junction temperature and direct current power value input formula T
j=PR
th(j-c)+T
cin calculate the thermal resistance of this field effect transistor, wherein, T
jfor the Peak Junction Temperature of field effect transistor; P is the direct current power of field effect transistor; R
th(j-c) be the thermal resistance of field effect transistor under certain power condition; T
cfor agingtable temperature;
S307, when the thermal resistance of field effect transistor is greater than preset value, this field effect transistor is substandard product.
Wherein, thermal resistance embodies an important parameter of electronic reliability, and excessive its heating of device of thermal resistance is higher, belongs to substandard product.The qualified thermal resistance standard of different field effect transistor is not quite similar, and the present invention does not also limit at this.
A kind of field effect transistor screening technique provided by the invention, can by the agingtable temperature preset, for field effect transistor applies multiple different direct current power, and detect the Peak Junction Temperature corresponding with direct current power, thus acquisition agingtable temperature, governing equation between direct current power and Peak Junction Temperature.Only need the maximum allowable junction temperature according to field effect transistor, obtained governing equation just can be used to determine the temperature of aging middle agingtable and the direct current power value needed for field effect transistor applies, then calculate the thermal resistance of this field effect transistor, thus according to thermal resistance, field effect transistor is screened.Field effect transistor screening technique of the present invention can realize the Effective selection of field effect transistor.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually see, what each embodiment stressed is the difference with other embodiments.The above is only the specific embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. determine a method for field effect transistor aging condition, it is characterized in that, comprising:
At default agingtable temperature, be the drain terminal voltage that field effect transistor input is preset;
Change the grid voltage of field effect transistor;
Detect under different grid voltage, the Peak Junction Temperature of field effect transistor under the direct current power of this field effect transistor and this direct current power, obtain agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
Agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
According to the maximum allowable junction temperature of this field effect transistor, described governing equation is used to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value;
The grid voltage of described change field effect transistor is specially: use the grid voltage with suppressing the supply module of oscillating circuit to change field effect transistor.
2. method according to claim 1, is characterized in that, described field effect transistor is GaN base transistor with high electronic transfer rate.
3. method according to claim 1, it is characterized in that, described at default agingtable temperature, the drain terminal voltage preset for field effect transistor input is specially: at default agingtable temperature, uses the drain terminal voltage with suppressing the supply module of oscillating circuit to be preset for field effect transistor input.
4. method according to claim 1, is characterized in that, the method detecting this field effect transistor Peak Junction Temperature is: use infrared microscopy measuring element to detect the Peak Junction Temperature of this field effect transistor.
5. method according to claim 1, it is characterized in that, described agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature, be specially: agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, use this field effect transistor agingtable temperature of mathematical analysis software calculating acquisition of Origin, the governing equation between direct current power and Peak Junction Temperature.
6. a field effect transistor aging method, is characterized in that, comprising:
The method of the determination field effect transistor aging condition of claim 1 is used to determine to need the agingtable temperature corresponding to aging field effect transistor and direct current power value;
At described agingtable temperature, for this field effect transistor input drain terminal voltage and the grid voltage adjusting described field effect transistor makes the direct current power of this field effect transistor be described direct current power value;
In preset time period, continue aging to described field effect transistor;
The grid voltage of the described field effect transistor of described adjustment is specially: use the grid voltage with suppressing the supply module of oscillating circuit to adjust described field effect transistor.
7. method according to claim 6, is characterized in that, described field effect transistor is GaN base transistor with high electronic transfer rate.
8. method according to claim 6, is characterized in that, is describedly specially for this field effect transistor input drain terminal voltage: use with suppressing the supply module of oscillating circuit to input drain terminal voltage for this field effect transistor.
9. a field effect transistor screening technique, is characterized in that, comprising:
At default agingtable temperature, be the drain terminal voltage that field effect transistor input is preset;
Change the grid voltage of field effect transistor;
Detect under different grid voltage, the Peak Junction Temperature of field effect transistor under the direct current power of this field effect transistor and this direct current power, obtain agingtable temperature, direct current power value and Peak Junction Temperature that many groups are corresponding;
Agingtable temperature, direct current power value and the Peak Junction Temperature corresponding according to described many groups, obtain this field effect transistor agingtable temperature, governing equation between direct current power and Peak Junction Temperature;
According to the maximum allowable junction temperature of this field effect transistor, described governing equation is used to determine this agingtable temperature corresponding to field effect transistor maximum allowable junction temperature and direct current power value;
By agingtable temperature corresponding to the maximum allowable junction temperature of this field effect transistor and this field effect transistor maximum allowable junction temperature and direct current power value input formula T
j=PR
th(j-c)+T
cin calculate the thermal resistance of this field effect transistor, wherein, T
jfor the Peak Junction Temperature of field effect transistor; P is the direct current power of field effect transistor; R
th(j-c) be the thermal resistance of field effect transistor under certain power condition; T
cfor agingtable temperature;
When the thermal resistance of field effect transistor is greater than preset value, this field effect transistor is substandard product.
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| 功率晶体管结温测量与器件筛选条件拟定;张奕轩等;《电子产品可靠性与环境试验》;20070630;第25卷(第3期);第12页第2栏第13行至第14页第2栏第42行 * |
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