CN102830749A - Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) - Google Patents
Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) Download PDFInfo
- Publication number
- CN102830749A CN102830749A CN2012103231723A CN201210323172A CN102830749A CN 102830749 A CN102830749 A CN 102830749A CN 2012103231723 A CN2012103231723 A CN 2012103231723A CN 201210323172 A CN201210323172 A CN 201210323172A CN 102830749 A CN102830749 A CN 102830749A
- Authority
- CN
- China
- Prior art keywords
- clock
- submodule
- bus
- module
- apb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001149 cognitive effect Effects 0.000 title 1
- 230000005236 sound signal Effects 0.000 claims description 6
- 238000013461 design Methods 0.000 abstract description 6
- 230000008447 perception Effects 0.000 abstract 3
- 230000005540 biological transmission Effects 0.000 description 13
- 238000012545 processing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
动态时钟控制模块及基于该模块的面向多媒体感知网络SoC的动态时钟控制系统，涉及一种动态时钟控制模块及基于该模块的面向多媒体感知网络SoC的动态时钟控制系统。它是为了实现对音视频采集的时钟实现简单、可靠、灵活的控制，并且在保证多媒体感知节点性能的同时有效降低系统的功耗。本发明通过针对于多媒体感知节点的时钟发生和控制的设计，对音视频采集的时钟进行精确控制，通过软件调度和硬件门控时钟的设计有效地降低了系统的功耗，而不会影响系统的性能。本发明适用于面向多媒体感知网络SoC的动态时钟控制。
A dynamic clock control module and a dynamic clock control system based on the module for multimedia perception network SoC relate to a dynamic clock control module and a dynamic clock control system for multimedia perception network SoC based on the module. It is to achieve simple, reliable and flexible control of the clock for audio and video acquisition, and effectively reduce the power consumption of the system while ensuring the performance of multimedia sensing nodes. The present invention precisely controls the clock for audio and video collection through the design of clock generation and control for multimedia sensing nodes, and effectively reduces the power consumption of the system through the design of software scheduling and hardware gating clock without affecting the system performance. The invention is applicable to the dynamic clock control of SoC oriented to the multimedia perception network.
Description
Technical field
The present invention relates to a kind of dynamic clock control module and reach dynamic clock control system towards multimedia sensing network SoC based on this module.
Background technology
As a branch of wireless sensor network, the multimedia sensing network need be realized on the node of energy constraint equally.Identical with traditional wireless aware node, the multimedia sensing node also is made up of three basic modules: data acquisition module, data processing module and data transmission module.Because the singularity of the deployed environment of node and the cost of changing supplying cell can not often be changed the battery of node in a short time or to the node charging, therefore just need reduce the energy consumption of wireless aware node as much as possible.
The environmental information that traditional wireless aware node is gathered generally all is the data of one dimensions such as simple temperature, humidity, illumination; With data transmission with handle that to compare the energy that the sensor acquisition environmental information consumed often very little; Usually can neglect the energy that image data consumes, optimize network topology structure to reduce the power consumption of data transmission so mainly concentrate on the low power dissipation design of traditional wireless-aware network.Different with traditional sensing node is; The collection of multimedia sensing node be the stream medium data that image and sound etc. contain much information; Need for a long time the sound image signal of outside to be sampled, and change into digital signal, therefore for the multimedia sensing node through A/D; The energy consumption of data acquisition and the energy consumption of data transmission are approximate, even surpass the energy that data transmission consumed.The problem of the energy consumption of data acquisition is not considered in the design of traditional sensor senses node, can not directly traditional wireless aware node platform be married again above the multimedia sensing network.
Summary of the invention
The present invention be for realize to the clock of audio-video collection realize simply, reliably, control flexibly; And the power consumption of effective reduction system when guaranteeing multimedia sensing node performance, thereby a kind of dynamic clock control module is provided and based on the dynamic clock control system towards multimedia sensing network SoC of this module.
The dynamic clock control module, it comprises clock selection module 1, clock frequency division module and Clock gating module; Said clock frequency division module is made up of audio frequency input submodule 21, video input submodule 22, SDRAM submodule 23, an ahb bus submodule 24 and an APB bus submodule 25; The Clock gating module is made up of No. two audio frequency input submodule 31, No. two video input submodules 32, No. two SDRAM submodules 33, No. two ahb bus submodules 34 and No. two APB bus submodules 35;
Clock selection module 1 is used for the clock source is selected, and selected clock source is exported to audio frequency input submodule 21, video input submodule 22, SDRAM submodule 23, ahb bus submodule 24, an APB bus submodule 25 respectively;
No. one audio frequency input submodule 21 is used for producing the required audio clock of system according to the clock source of receiving, and the audio clock that produces is exported to audio frequency input submodule 31 No. two;
No. one video input submodule 22 is used for producing the required video clock of system according to the clock source of receiving, and the video clock that produces is exported to video input submodule 32 No. two;
A SDRAM submodule 23 is used for producing the required SDRAM clock of system according to the clock source of receiving, and the SDRAM clock that produces is exported to SDRAM submodule 33 No. two;
An ahb bus submodule 24 is used for producing the required ahb bus clock of system according to the clock source of receiving, and the ahb bus clock that produces is exported to ahb bus submodule 34 No. two;
An APB bus submodule 25 is used for producing the required APB bus clock of system according to the clock source of receiving, and the APB bus clock that produces is exported to APB bus submodule 35 No. two;
No. two audio frequency input submodule 31 is used for according to the acoustic frequency clock signal that audio frequency input submodule 21 is sent into sound signal being exported;
No. two videos input submodule 32 is used for according to the video clock signal that video input submodule 22 is sent into vision signal being exported;
No. two SDRAM submodules 33 are used for according to the SDRAM clock signal that SDRAM submodule 23 is sent into the SDRAM signal being exported;
No. two ahb bus submodules 34 are used for to the outside ahb bus signal being provided according to the ahb bus clock signal that ahb bus submodule 24 is sent into;
No. two APB bus submodules 35 are used for to the outside APB being provided bus signals according to the APB bus clock signal that APB bus submodule 25 is sent into.
The clock of clock source for obtaining through PLL phaselocked loop 1.
It also comprises PLL configuration register 4, control register 5, frequency division register 6 and control register 7;
Said PLL configuration register 4 is used for PLL phaselocked loop 1 is carried out the clock configuration;
Based on the dynamic clock control system towards multimedia sensing network SoC of above-mentioned module, it comprises audio input interface 7, video input interface 8, Memory Controller 9, AHB-APB bridge 10, DSU debugging unit 11, LEON3 processor 12, GPIO interface 13, APB UART14, I
2C interface 15 and SPI interface 16;
AHB-APB bridge 10 all is articulated on the ahb bus with DSU debugging unit 11;
It also comprises interruptable controller 10, and said interruptable controller 10 is articulated on the APB bus.
It also comprises timer 11, and said timer 11 is articulated on the APB bus.
Module of the present invention realized the clock of audio-video collection is realized simple, reliable, control flexibly, and the dynamic clock of using this module is controlled at the power consumption of effective reduction system when guaranteeing multimedia sensing node performance.The present invention is particularly useful for the dynamic clock control of multimedia sensing network SoC.
Description of drawings
Fig. 1 is the structural representation of dynamic clock control system of the present invention; Fig. 2 is the multimedia sensing node structure and the interface synoptic diagram of multimedia sensing network; Fig. 3 is the cmos circuit power consumption principle schematic described in the embodiment two; Fig. 4 is the PLL initialization flowchart in the embodiment two; Fig. 5 is the audio frequency and video clock setting process flow diagram in the embodiment two; Fig. 6 is the system state synoptic diagram in the embodiment two.
Embodiment
Embodiment one, dynamic clock control module, it comprises clock selection module 1, clock frequency division module and Clock gating module; Said clock frequency division module is made up of audio frequency input submodule 21, video input submodule 22, SDRAM submodule 23, an ahb bus submodule 24 and an APB bus submodule 25; The Clock gating module is made up of No. two audio frequency input submodule 31, No. two video input submodules 32, No. two SDRAM submodules 33, No. two ahb bus submodules 34 and No. two APB bus submodules 35;
Clock selection module 1 is used for the clock source is selected, and selected clock source is exported to audio frequency input submodule 21, video input submodule 22, SDRAM submodule 23, ahb bus submodule 24, an APB bus submodule 25 respectively;
No. one audio frequency input submodule 21 is used for producing the required audio clock of system according to the clock source of receiving, and the audio clock that produces is exported to audio frequency input submodule 31 No. two;
No. one video input submodule 22 is used for producing the required video clock of system according to the clock source of receiving, and the video clock that produces is exported to video input submodule 32 No. two;
A SDRAM submodule 23 is used for producing the required SDRAM clock of system according to the clock source of receiving, and the SDRAM clock that produces is exported to SDRAM submodule 33 No. two;
An ahb bus submodule 24 is used for producing the required ahb bus clock of system according to the clock source of receiving, and the ahb bus clock that produces is exported to ahb bus submodule 34 No. two;
An APB bus submodule 25 is used for producing the required APB bus clock of system according to the clock source of receiving, and the APB bus clock that produces is exported to APB bus submodule 35 No. two;
No. two audio frequency input submodule 31 is used for according to the acoustic frequency clock signal that audio frequency input submodule 21 is sent into sound signal being exported;
No. two videos input submodule 32 is used for according to the video clock signal that video input submodule 22 is sent into vision signal being exported;
No. two SDRAM submodules 33 are used for according to the SDRAM clock signal that SDRAM submodule 23 is sent into the SDRAM signal being exported;
No. two ahb bus submodules 34 are used for to the outside ahb bus signal being provided according to the ahb bus clock signal that ahb bus submodule 24 is sent into;
No. two APB bus submodules 35 are used for to the outside APB being provided bus signals according to the APB bus clock signal that APB bus submodule 25 is sent into.
The clock of clock source for obtaining through PLL phaselocked loop 1.
It also comprises PLL configuration register 4, control register 5, frequency division register 6 and control register 7;
Said PLL configuration register 4 is used for PLL phaselocked loop 1 is carried out the clock configuration;
APB bus: Advanced Peripheral Bus;
Ahb bus: Advanced High performance Bus.
Embodiment two, combination Fig. 1 explain this embodiment; Based on the dynamic clock control system towards multimedia sensing network SoC of embodiment one, it comprises audio input interface 7, video input interface 8, Memory Controller 9, AHB-APB bridge 10, DSU debugging unit 11, LEON3 processor 12, GPIO interface 13, APB UART14, I2C interface 15 and SPI interface 16;
AHB-APB bridge 10 all is articulated on the ahb bus with DSU debugging unit 11;
It also comprises interruptable controller 10, and said interruptable controller 10 is articulated on the APB bus.
It also comprises timer 11, and said timer 11 is articulated on the APB bus.
Mainly accomplish collection, processing and the transmission of multimedia audio and image information towards the SoC chip of multimedia sensing network.The structure of multimedia sensing node and interface block diagram are as shown in Figure 2 among the present invention, and wherein part of data acquisition comprises the Voice & Video control interface, and the audio frequency control interface passes through I
2S bus and audio collection circuit carry out data transmission; Video interface then comprises clock, the DCB with the camera communication.Tcp data segment mainly is a spi bus interface, carries out data transmission with the wireless communication module of 2.4GHz.Data processing section is accomplished by the LEON3 soft-core processor.This external system also comprises the data storage cell of being made up of SDRAM and Flash.
It is as shown in Figure 3 that (among the figure: the implication of mark Gate is: door; The implication of mark: Subthreshold is: threshold; ), the cmos circuit power consumption mainly is made up of 3 parts: the dynamic power consumption that capacitor charge and discharge causes, the power consumption that power consumption that the knot pull-down current causes and short-circuit current cause.Wherein the proportion that accounts for of dynamic power consumption is maximum, accounts for more than 90% of total power consumption, and its computing formula is seen formula (1):
P=a×C×V
2 dd×f （1）
A is the upset probability of node in the formula, and C is a node capacitor, V
DdBe WV, f is a clock frequency.Clock gating (gated clocking) has not only reduced the clock power consumption, has also reduced the upset probability of node.
The workflow of each module and register with the effect as follows:
Clock selection module 1: start from for the performance of system and taking all factors into consideration of power consumption, the clock of the lower external crystal-controlled oscillation of frequency of utilization can be selected by system, also can obtain higher clock frequency through phaselocked loop (PLL) is set.This module is through reading on the control register selection position about the clock source, if this position is 1, the clock that then uses external crystal-controlled oscillation is as system's input clock, if 0 is used pll clock.The output clock of PLL can be set through the PLL configuration register, thereby changes the input clock of system.
Clock frequency division module: this module can produce the clock of multimedia sensing node image data and the work clock of system bus.For each submodule in the clock frequency division module; All there is a frequency division register corresponding with it; Each register can be provided with one 16 divide ratio; Module through this divide ratio is corresponding just can be carried out frequency division with the system clock of module 1 output, obtains the needed clock of module.For the multimedia sensing node, this module can provide more fine-grained clock control, and each submodule can be provided with divide ratio separately, and configuration provides bigger flexibility ratio for the clock of system.
The Clock gating module: consider the different characteristics of multimedia sensing node and traditional wireless aware node, need be to the clock of data collection according to the opening and closing that need of using.This module is enabling of control audio input clock 3.1, video input clock 3.2, SDRAM synchronous clock and AHB clock separately; And the peripheral hardware on the APB bus does not relate to the work of data acquisition; Power consumption consumption for system is not very big simultaneously, so top clock enables always.For all have on all inner submodule clock-control registers of module 3 one corresponding with it, if this position is 1, then enables corresponding clock and export.If instead be 0, then forbid corresponding clock.
In addition; Ahb bus in the clock frequency division module and APB bus submodule can be provided with the clock of corresponding bus; Like this can be under the relatively little situation of system load the clock rate of dynamic adjustments ahb bus, reduce the power consumption of system and can not influence the performance of system.
Next through concrete instance the course of work of the present invention is described:
Reset initialization: after the multimedia sensing node powered on, clock took place and control module is started working, and at first needs reset initialization PLL module 7, accomplishes the initialization flow process of PLL through PLL configuration register 6 is set, and particular flow sheet is seen Fig. 4.After the PLL initialization, the input clock of system is switched to pll clock through the clock source selection module.The value of ahb bus clock 2.4 and APB bus clock 2.5 all was 50M after module resetted, and ahb bus clock acquiescence is opened, because system program operates among the SDRAM, also enabled so the synchronous clock of SDRAM is given tacit consent to.
Produce audio, video data and gather needed clock: gather needed clock for audio, video data; The present invention's submodule 2.1 and 2.2 through correspondence in module 2 disposes; Like this acquisition clock unified management has been simplified the difficulty of clock setting, accurate control is provided Voice & Video.Obtain the corresponding needed clock of audio frequency and video through the input clock frequency division with system, divide ratio is read by the frequency division register of correspondence.Concrete clock setting flow process is seen Fig. 5.
According to the current task of sensing node enabling of clock is set:
According to the characteristics that the power consumption of multimedia sensing network consumes, the power consumption of system mainly consumes in the collection of audio, video data, the audio frequency and video clock is controlled the power consumption that can largely reduce system.Introduced in the background of invention, the wireless aware node is mainly carried out three types task, is respectively data acquisition, data processing and data transmission.Difference according to task is divided into 4 states, idle condition, acquisition state, treatment state and transmission state with system.System does not carry out any operation under idle condition, at this moment the clock of audio-video collection is closed, and system operates under the low-speed mode.When task switched to data acquisition, the state of system became acquisition state, and this moment, the clock of audio-video collection was opened, the beginning data acquisition.Switch to the data processing state when data acquisition finishes the back system, speed that can ahb bus is set at a high speed, to increase the speed of data processing, the performance of raising system.System got into transmission state after data processing finished, and this moment, radio-frequency module was started working, and carried out data transmission.System gets back to idle condition again after end of transmission (EOT), and close the clock of audio-video collection this moment, is low speed with the ahb bus frequency configuration.The state transitions of system is shown in accompanying drawing 6.
The design that the present invention takes place and controls through the clock that is directed to the multimedia sensing node; Clock to audio-video collection is accurately controlled; Reduce the power consumption of system effectively through software scheduling and hardware gate clock design, and can not influence the performance of system.
Claims (6)
1. dynamic clock control module, it is characterized in that: it comprises clock selection module (1), clock frequency division module and Clock gating module; Said clock frequency division module is made up of an audio frequency input submodule (21), video input submodule (22), a SDRAM submodule (23), an ahb bus submodule (24) and an APB bus submodule (25); The Clock gating module is made up of No. two audio frequency input submodules (31), No. two video input submodules (32), No. two SDRAM submodules (33), No. two ahb bus submodules (34) and No. two APB bus submodules (35);
Clock selection module (1) is used for the clock source is selected, and selected clock source is exported to audio frequency input submodule (21), video input submodule (22), a SDRAM submodule (23), an ahb bus submodule (24), an APB bus submodule (25) respectively;
An audio frequency input submodule (21) is used for producing the required audio clock of system according to the clock source of receiving, and the audio clock that produces is exported to audio frequency input submodule (31) No. two;
A video input submodule (22) is used for producing the required video clock of system according to the clock source of receiving, and the video clock that produces is exported to video input submodule (32) No. two;
A SDRAM submodule (23) is used for producing the required SDRAM clock of system according to the clock source of receiving, and the SDRAM clock that produces is exported to No. two SDRAM submodules (33);
An ahb bus submodule (24) is used for producing the required ahb bus clock of system according to the clock source of receiving, and the ahb bus clock that produces is exported to No. two ahb bus submodules (34);
An APB bus submodule (25) is used for producing the required APB bus clock of system according to the clock source of receiving, and the APB bus clock that produces is exported to No. two APB bus submodules (35);
No. two audio frequency input submodules (31) are used for according to the acoustic frequency clock signal that an audio frequency input submodule (21) is sent into sound signal being exported;
No. two video input submodules (32) are used for according to the video clock signal that a video input submodule (22) is sent into vision signal being exported;
No. two SDRAM submodules (33) are used for according to the SDRAM clock signal that a SDRAM submodule (23) is sent into the SDRAM signal being exported;
No. two ahb bus submodules (34) are used for to the outside ahb bus signal being provided according to the ahb bus clock signal that an ahb bus submodule (24) is sent into;
No. two APB bus submodules (35) are used for to the outside APB being provided bus signals according to the APB bus clock signal that an APB bus submodule (25) is sent into.
2. dynamic clock control module according to claim 1 is characterized in that the clock of clock source for obtaining through PLL phaselocked loop (1).
3. dynamic clock control module according to claim 2 is characterized in that it also comprises PLL configuration register (4), control register (5), frequency division register (6) and control register (70);
Said PLL configuration register (4) is used for PLL phaselocked loop (1) is carried out the clock configuration;
Control register (5) is used for that to carry out register signal mutual with clock selection module (1);
Frequency division register (6) is used for that to carry out register signal mutual with clock frequency division module;
Control register (7) is used for that to carry out register signal mutual with the Clock gating module.
4. based on the dynamic clock control system towards multimedia sensing network SoC of claim 1, Ji Tezheng is: it comprises audio input interface (7), video input interface (8), Memory Controller (9), AHB-APB bridge (10), DSU debugging unit (11), LEON3 processor (12), GPIO interface (13), APB UART (14), I
2C interface (15) and SPI interface (16);
Audio input interface (7) is used to receive the sound signal that the dynamic clock control module is sent;
Video input interface (8) is used to receive the vision signal that the dynamic clock control module is sent;
Memory Controller (9) is used to receive the SDRAM signal that the dynamic clock control module is sent; The control signal output of said Memory Controller (9) or input end input or output end with the control signal of LEON3 processor (12) and are connected;
AHB-APB bridge (10) and DSU debugging unit (11) all are articulated on the ahb bus;
GPIO interface (13), APB UART (14), I2C interface (15) and SPI interface (16) all are articulated on the APB bus.
5. the dynamic clock control system towards multimedia sensing network SoC according to claim 4, base are characterised in that it also comprises interruptable controller (10), and said interruptable controller (10) is articulated on the APB bus.
6. the dynamic clock control system towards multimedia sensing network SoC according to claim 4, base are characterised in that it also comprises timer (11), and said timer (11) is articulated on the APB bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103231723A CN102830749A (en) | 2012-09-04 | 2012-09-04 | Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103231723A CN102830749A (en) | 2012-09-04 | 2012-09-04 | Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102830749A true CN102830749A (en) | 2012-12-19 |
Family
ID=47333920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103231723A Pending CN102830749A (en) | 2012-09-04 | 2012-09-04 | Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102830749A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908310A (en) * | 2019-12-03 | 2020-03-24 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system of controller and ultrasonic equipment |
| CN115878538A (en) * | 2022-12-28 | 2023-03-31 | 上海中基国威电子股份有限公司 | Dynamic clock gating device based on ARM bus |
| CN117608388A (en) * | 2024-01-15 | 2024-02-27 | 珠海全志科技股份有限公司 | Power consumption control method and device applied to SoC system, SoC system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7640446B1 (en) * | 2003-09-29 | 2009-12-29 | Marvell International Ltd. | System-on-chip power reduction through dynamic clock frequency |
-
2012
- 2012-09-04 CN CN2012103231723A patent/CN102830749A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7640446B1 (en) * | 2003-09-29 | 2009-12-29 | Marvell International Ltd. | System-on-chip power reduction through dynamic clock frequency |
Non-Patent Citations (4)
| Title |
|---|
| 张拥军 等: "动态时钟配置下的SoC管理", 《单片机与嵌入式系统应用》, 1 April 2004 (2004-04-01), pages 1 - 5 * |
| 彭章超: "《万方学位论文》", 14 August 2007, article "基于Leon3处理器SoC低功耗设计研究", pages: 1-41 * |
| 郑朝霞 等: "无线传感器节点芯片的软硬协同低功耗设计技术", 《计算机科学》, vol. 34, no. 9, 1 September 2008 (2008-09-01), pages 19 - 21 * |
| 陈黎明 等: "应用于低功耗SoC的动态时钟管理技术", 《微电子学》, vol. 37, no. 1, 20 February 2007 (2007-02-20), pages 45 - 48 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908310A (en) * | 2019-12-03 | 2020-03-24 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system of controller and ultrasonic equipment |
| CN115878538A (en) * | 2022-12-28 | 2023-03-31 | 上海中基国威电子股份有限公司 | Dynamic clock gating device based on ARM bus |
| CN117608388A (en) * | 2024-01-15 | 2024-02-27 | 珠海全志科技股份有限公司 | Power consumption control method and device applied to SoC system, SoC system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101782791B (en) | Clock/reset and configuration controller hardcore in communication processor chip | |
| US20160363955A1 (en) | Clock gating with an asynchronous wrapper cell | |
| TW202242609A (en) | Very low power microcontroller system and power control method | |
| US10250142B1 (en) | Advanced constant off-time control for four-switch buckboost converter | |
| US11682973B2 (en) | Advanced constant off-time control for four-switch buck-boost converter | |
| US11537375B2 (en) | Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method | |
| CN202309521U (en) | Control circuit for single-inductance dual-output switching power supply | |
| CN113472382B (en) | Wireless communication method, wireless communication device, electronic tag, and storage medium | |
| CN104050973A (en) | Low power audio trigger via intermittent sampling | |
| US11895588B2 (en) | Timing precision maintenance with reduced power during system sleep | |
| TW201502786A (en) | Combined power supply and input/output system with boost capability | |
| CN102830749A (en) | Dynamic clock control module and dynamic clock control system based on the module and facing multimedia cognitive network SoC (System on Chip) | |
| US10503674B2 (en) | Semiconductor device including a clock source for generating a clock signal and a clock control circuit for controlling the clock source in hardware, a semiconductor system including the semiconductor device, and a method of operating the semiconductor device | |
| Lombardo et al. | Power management techniques in an FPGA-based WSN node for high performance applications | |
| US8010818B2 (en) | Power efficient method for controlling an oscillator in a low power synchronous system with an asynchronous I2C bus | |
| Wang et al. | A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9× faster running speed and 11× higher energy efficiency using fast power-on detection and nonvolatile radio controller | |
| US7895457B2 (en) | Memory card with power saving | |
| US20090261869A1 (en) | Clock domain data transfer device and methods thereof | |
| US10712807B2 (en) | Methods and apparatus for saving always on (AON) routing of signals across chips | |
| CN201926692U (en) | Current and voltage synchronous sampling phase automatic compensation system | |
| CN206684533U (en) | Wechat remote control chip | |
| CN106066684B (en) | Master-slave SOC chip low power consumption control circuit | |
| US9763196B2 (en) | Mobile hotspot UFI device and start-up method | |
| KR102571154B1 (en) | Semiconductor device, semiconductor system and method for operating semiconductor device | |
| CN112787656B (en) | Sample-hold control method, device and host |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C05 | Deemed withdrawal (patent law before 1993) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121219 |