CN102820966A - Serial data associated clock extraction method - Google Patents
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- CN102820966A CN102820966A CN2012102601672A CN201210260167A CN102820966A CN 102820966 A CN102820966 A CN 102820966A CN 2012102601672 A CN2012102601672 A CN 2012102601672A CN 201210260167 A CN201210260167 A CN 201210260167A CN 102820966 A CN102820966 A CN 102820966A
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Abstract
The invention relates to the field of digital communication, in particular to a serial data associated clock extraction method. The method comprises arranging a synchronous frame signal on the transmitting end for transmitting the serial data to enable a frame synchronous searching unit at the receiving end to work effectively; and generating N clocks identical in frequency but different in phases at the receiving end by using a system synchronous clock as the reference clock, thereby completing effective extraction of the associated clock.
Description
Technical field
The present invention relates to digital communicating field, refer more particularly to a kind of serial data with the road clock extraction method.
Background technology
Usually; All there is a system synchronization clock generator to concentrate transmitting terminal and receiving terminal dissemination system synchronised clock in the communication system to Serial Data Transfer Mode; With the system synchronization clock is the synchronised clock that benchmark produces serial data; Because transmission means, length of arrangement wire is inconsistent, the phase relation of the system synchronization clock of distribution and the data of serial transmission is indefinite.At receiving terminal, operate the serial data of receiving, one and serial data clock synchronized (promptly with the road clock) must be arranged.Therefore extracting with the road clock, is the very important problem in the inside, serial transmission field.
Introduce the existing technology of extracting with the road clock below:
Prior art scheme one adds a channel transfer with the road clock at the transmitting terminal and the receiving terminal of Serial Data Transfer Mode.
Prior art scheme two, Chinese invention patent " a kind of high-speed serial data with road clock transfer device " (application number is: 200410026826.1) disclose a kind of serial data with road clock transfer technology.Its concrete operations step: step 1. system synchronization clock dispensing device is to the transmitting terminal and the receiving terminal distribution synchronised clock of each high-speed serial data transmission; Step 2. inserting device with the road clock is benchmark with the synchronised clock of system's distribution, fixing m sequence is inserted in the idle time slot of parallel input of transmitting terminal serializer, gets into serializer formation serial data stream jointly with customer traffic; Step 3. the transmitting terminal of high-speed serial data transmission system sends to receiving terminal with serial data stream through universal serial bus; Step 4. with the detection window maker of road clock extracting apparatus, utilize the synchronised clock of system's distribution, produce the detection window signal; Step 5. the deserializer of high-speed serial communication system receiving terminal unstrings serial data stream, in the data flow after unstringing, utilizes the window signal of the generation in the 4th step, extracts with the road clock through sequential detector.
The existing shortcoming of technology that realizes is: though realized the extraction with the road clock, method one has increased a transmission channel, causes the multiple of interface quantity and PCB layout area to increase progressively, and has wasted resource.Though method two does not need a designated lane tranmitting data register, the window signal that produces need be contained the m sequence that receives at least, but window signal again can not be too wide, otherwise possibly cause flase drop.
Summary of the invention
To disadvantages of background technology, the invention provides a kind of serial data with the road clock extraction method, through setting up the synchronization frame signal, the frame synchronization search unit of receiving terminal is effectively worked at the transmitting terminal of Serial Data Transfer Mode; But utilize the system synchronization clock to produce N the different clock of the identical phase place of frequency at receiving terminal, thereby accomplish effective extraction with the road clock as reference clock.
Technical scheme of the present invention is: a kind of serial data with the road clock extraction method, comprise the steps:
Step 1, system synchronization clock generator are to the transmitting terminal and the receiving terminal dissemination system synchronised clock of Serial Data Transfer Mode;
The transmitting terminal of step 2, Serial Data Transfer Mode produces the serial data that has synchronization frame;
The transmitting terminal of step 3, Serial Data Transfer Mode sends to receiving terminal with the serial data that step 2 produces through serial line interface;
The timing unit of the receiving terminal of step 4, Serial Data Transfer Mode is a benchmark with the system synchronization clock; Produce N clock: CLK1 ..., CLKN; This N clock frequency all synchronised clock frequency with serial data is consistent, the phase place of adjacent clock delay than previous clock phase or leading 360 ° divided by N;
The frame synchronization search unit of the receiving terminal of step 5, Serial Data Transfer Mode respectively CLK1 ..., the rising edge of CLKN or the synchronization frame of trailing edge search string line data, and export respectively synchronization status marker FLAG1 ..., FLAGN;
The clock selecting unit of the receiving terminal of step 6, Serial Data Transfer Mode according to synchronization status marker FLAG1 ..., FLAGN select CLK1 ..., 1 tunnel among the CLKN as recover with the road clock;
The deframer of the receiving terminal of step 7, Serial Data Transfer Mode is separated frame, is recovered original serial data serial data;
N is greater than 2 in the above-mentioned steps.
Its beneficial effect is: need not take a designated lane transmission with the road clock, only need take a small amount of idle time slot in the transmission channel, can accurately realize the Clock Extraction of system receiving terminal; Need not to produce window signal, can not cause flase drop.
Aforesaid serial data with the road clock extraction method; It is characterized in that: said step 2 comprises: timing unit is that benchmark produces the serial data synchronised clock with the system synchronization clock; Data producer produces original serial data; The synchronization frame generator produces synchronization frame, and framer is inserted into synchronization frame in the idle time slot of original serial data and produces the serial data that has synchronization frame.Its beneficial effect is: guarantee the have efficient search of frame synchronization search unit to synchronization frame.
Aforesaid serial data with the road clock extraction method; It is characterized in that: said step 4 comprises: CLK1 ..., have at least among the CLKN rising edge of a clock or trailing edge very near apart from the center of serial data code element, and this N clock and serial data synchronised clock homology.Its beneficial effect is: guarantee the effective extraction with the road clock.
Aforesaid serial data with the road clock extraction method; It is characterized in that: said step 5 comprises: the synchronization status marker of N frame synchronization search unit output all is initialized as low level; If wherein 1 frame synchronization search unit searches is to synchronization frame; Then the synchronization status marker of this frame synchronization search unit output is put high level, if wherein 1 frame synchronization search unit does not search synchronization frame, then the synchronization status marker of this frame synchronization search unit output keeps low level constant.Its beneficial effect is: each synchronization status marker is indicated the validity of each clock respectively.
Aforesaid serial data with the road clock extraction method, it is characterized in that: said step 6 comprises: if FLAG1 is a high level, then select CLK1 be recover with the road clock; If FLAG1 is 0, FLAG2 be 1 select CLK2 for recover with the road clock; And the like, if FLAG1 ..., FLAG (N-1) is 0, FLAGN be 1 select CLKN for recover with the road clock.Its beneficial effect is: synchronization status marker FLAG1 ..., FLAGN priority reduces successively, and is more quick with the generation of road clock.
Aforesaid serial data with the road clock extraction method, it is characterized in that: said Serial Data Transfer Mode medium is cable or optical fiber, or the backboard universal serial bus.
Aforesaid serial data with the road clock extraction method, it is characterized in that: said N clock value is 4 clocks.Its beneficial effect is: resource occupation and Clock Extraction effect combination property are better.
Description of drawings
Fig. 1 is a hardware sketch map of the present invention;
Fig. 2 is a flow chart of the present invention;
Fig. 3 is original serial data of the present invention and the frame assumption diagram that has the serial data of synchronization frame;
Fig. 4 is the clock phase graph of a relation of CLK1 of the present invention, CLK2, CLK3, CLK4.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explanation.
Like Fig. 1 is the hardware sketch map with the road clock extraction method of a kind of serial data of the embodiment of the invention.Below be the explanation of using hardware among Fig. 1:
The system synchronization clock generator; Produce the system synchronization clock and be distributed to transmitting terminal and receiving terminal;
Transmitting terminal comprises: timing unit, data generation unit, synchronization frame generator, framer;
Receiving terminal comprises: timing unit, frame synchronization search unit, clock selecting unit, deframer.
As shown in Figure 2, may further comprise the steps of concrete serial data with the road clock extraction method:
1, the system synchronization clock generator is to the transmitting terminal and the receiving terminal distribution synchronised clock of Serial Data Transfer Mode
The system synchronization clock generator can be various clock generation circuits: can be produced through scale programmable logic device (FPGA) branch/frequency multiplication by crystal oscillator; Also can divide the frequency multiplication chip to produce through oversampling clock by crystal oscillator; Can also produce by the frequency source of special use.
2, the transmitting terminal of Serial Data Transfer Mode produces the serial data that has synchronization frame
Timing unit is that benchmark produces the serial data synchronised clock with the system synchronization clock; Data producer produces original serial data according to the serial data synchronised clock; The synchronization frame generator produces synchronization frame according to the serial data synchronised clock, and framer is inserted into synchronization frame according to the serial data synchronised clock in the idle time slot of original serial data and produces the serial data that has synchronization frame.Original serial data is as shown in Figure 3 with the frame structure of the serial data that has synchronization frame, and T0 is a frame period of serial data among the figure.
The timing unit here can be obtained by the inner phase-locked loop of scale programmable logic device (FPGA), also can be produced by scale programmable logic device (FPGA) internal logic, can also divide the frequency multiplication chip to produce by clock.
3, the transmitting terminal of Serial Data Transfer Mode sends to receiving terminal with the serial data that step 2 produces through serial line interface
The serial line interface here can be the backboard universal serial bus, can be cable, also can be optical fiber.
4, the timing unit of the receiving terminal of Serial Data Transfer Mode is a benchmark with the system synchronization clock; Produce 4 clock: CLK1, CLK2, CLK3, CLK4; These 4 clock frequencies all synchronised clock frequency with serial data are consistent, and the phase place of adjacent clock is delayed 90 ° than previous clock phase
The timing unit here can be obtained by the inner phase-locked loop of scale programmable logic device (FPGA), can be produced by scale programmable logic device (FPGA) internal logic, also can divide the frequency multiplication chip to produce by clock.
The CLK1, CLK2, CLK3, the CLK4 phase place that generate differ 90 ° successively; The phase place of CLK2 is delayed 90 ° than CLK1 phase place; The phase place of CLK3 is delayed 180 ° than CLK1 phase place, and the phase place of CLK4 is delayed 270 ° than CLK1 phase place, and these 4 clocks and serial data synchronised clock homology.The clock phase relation of CLK1, CLK2, CLK3, CLK4 is as shown in Figure 4, and T is a clock cycle of serial data among the figure.The rising edge that has a clock among CLK1, CLK2, CLK3, the CLK4 at least is near the center of serial data code element, and this clock can guarantee the efficiently sampling of serial data.
5, the frame synchronization search unit of the receiving terminal of Serial Data Transfer Mode is respectively at the synchronization frame of the rising edge search string line data of CLK1, CLK2, CLK3, CLK4, and exports synchronization status marker FLAG1, FLAG2, FLAG3, FLAG4 respectively
After the serial data transmission system energising, synchronization status marker FLAG1, FLAG2, FLAG3, FLAG4 all are initialized as low level.
With the work clock of CLK1 as the frame synchronization search unit, utilize the rising edge sampling of CLK1, when searching synchronization frame, synchronization status marker FLAG1 is changed to high level, otherwise FLAG1 keeps low level.
With the work clock of CLK2 as the frame synchronization search unit, utilize the rising edge sampling of CLK2, when searching synchronization frame, synchronization status marker FLAG2 is changed to high level, otherwise FLAG2 keeps low level.
With the work clock of CLK3 as the frame synchronization search unit, utilize the rising edge sampling of CLK3, when searching synchronization frame, synchronization status marker FLAG3 is changed to high level, otherwise FLAG3 keeps low level.
With the work clock of CLK4 as the frame synchronization search unit, utilize the rising edge sampling of CLK4, when searching synchronization frame, synchronization status marker FLAG4 is changed to high level, otherwise FLAG4 keeps low level.
The frame synchronization search unit comprises:
Detecting unit is used for the synchronization frame of search string line data;
Indicating member is used to export synchronization status marker synchronously;
The synchronization check unit is used for verification frame synchronization: get into after the synchronous regime, if do not search synchronization frame continuous 2 times, the synchronization frame of search string line data again then.
6, the clock selecting unit of the receiving terminal of Serial Data Transfer Mode according to synchronization status marker FLAG1, FLAG2, FLAG3, FLAG4 select 1 tunnel among CLK1, CLK2, CLK3, the CLK4 as recover with the road clock
Synchronization status marker FLAG1, FLAG2, FLAG3, FLAG4 priority reduce successively:
If FLAG1 is a high level, then select CLK1 be recover with the road clock, FLAG2, FLAG3, FLAG4 do not consider;
If FLAG1 is 0, FLAG2 be 1 select CLK2 for recover with the road clock, FLAG3, FLAG4 do not consider;
If FLAG1 and FLAG2 are 0, FLAG3 be 1 select CLK3 for recover with the road clock, FLAG4 does not consider;
If FLAG1, FLAG2 and FLAG3 are 0, FLAG4 be 1 select CLK4 for recover with the road clock.
1 road clock among each transmitting terminal and the selected CLK1 of receiving terminal energising, CLK2, CLK3, the CLK4 as recovery with the road clock, if transmitting terminal and receiving terminal do not cut off the power supply recovery constant with the road clock; If transmitting terminal outage or receiving terminal outage or two ends all cut off the power supply, then after energising again according to aforesaid way reselect 1 road clock wherein as recover with the road clock.
7, the deframer of the receiving terminal of Serial Data Transfer Mode is separated frame, is recovered original serial data serial data
The rising edge sampling with the road clock that utilization recovers, deframer is the synchronization frame of search string line data at first, and synchronization frame in the serial data and original serial data are separated to back level use.
Deframer comprises:
Detecting unit is used for the synchronization frame of search string line data;
Data are separated frame unit, are used to decompose synchronization frame and original serial data.
The present invention is not only applicable to transmitting terminal and receiving terminal all has only one situation, and is the same suitable with the situation of a plurality of receiving terminals, a plurality of transmitting terminal and a plurality of receiving terminals for a plurality of transmitting terminals and a receiving terminal, a transmitting terminal.
The receiving terminal timing unit produces the situation of N clock; As long as guarantee wherein to have at least the rising edge of a clock very near apart from the center of the serial data code element that has synchronization frame; Just can guarantee effective extraction, so the present invention also has following distortion with the road clock.
If N equals at 2 o'clock, it is inaccurate sampling to occur, but for the transmission line situation preferably the time, N also can equal 2.
When N more than or equal to 5 the time, appoint and get (N-1) individual clock wherein, respectively at the synchronization frame of the rising edge search string line data of this (N-1) individual clock.
When N more than or equal to 10 the time, appoint and get (N-2) individual clock wherein, respectively at the synchronization frame of the rising edge search string line data of this (N-1) individual clock.
Concluded,, appointed and get (N-m) individual clock wherein, respectively at the synchronization frame of the rising edge search string line data of this (N-m) individual clock as N the time more than or equal to 5m.Wherein m is more than or equal to 1.
Certainly; The present invention can also have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make corresponding change and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
- A serial data with the road clock extraction method, comprise the steps:Step 1, system synchronization clock generator are to the transmitting terminal and the receiving terminal dissemination system synchronised clock of Serial Data Transfer Mode;The transmitting terminal of step 2, Serial Data Transfer Mode produces the serial data that has synchronization frame;The transmitting terminal of step 3, Serial Data Transfer Mode sends to receiving terminal with the serial data that step 2 produces through serial line interface;The timing unit of the receiving terminal of step 4, Serial Data Transfer Mode is a benchmark with the system synchronization clock; Produce N clock: CLK1 ..., CLKN; This N clock frequency all synchronised clock frequency with serial data is consistent, the phase place of adjacent clock delay than previous clock phase or leading 360 ° divided by N;The frame synchronization search unit of the receiving terminal of step 5, Serial Data Transfer Mode respectively CLK1 ..., the rising edge of CLKN or the synchronization frame of trailing edge search string line data, and export respectively synchronization status marker FLAG1 ..., FLAGN;The clock selecting unit of the receiving terminal of step 6, Serial Data Transfer Mode according to synchronization status marker FLAG1 ..., FLAGN select CLK1 ..., 1 tunnel among the CLKN as recover with the road clock;The deframer of the receiving terminal of step 7, Serial Data Transfer Mode is separated frame, is recovered original serial data serial data;N is greater than 2 in the above-mentioned steps.
- 2. serial data as claimed in claim 1 with the road clock extraction method; It is characterized in that: said step 2 comprises: timing unit is that benchmark produces the serial data synchronised clock with the system synchronization clock; Data producer produces original serial data; The synchronization frame generator produces synchronization frame, and framer is inserted into synchronization frame in the idle time slot of original serial data and produces the serial data that has synchronization frame.
- 3. serial data as claimed in claim 1 with the road clock extraction method; It is characterized in that: said step 4 comprises: CLK1 ..., have at least among the CLKN rising edge of a clock or trailing edge very near apart from the center of serial data code element, and this N clock and serial data synchronised clock homology.
- 4. serial data as claimed in claim 1 with the road clock extraction method; It is characterized in that: said step 5 comprises: the synchronization status marker of N frame synchronization search unit output all is initialized as low level; If wherein 1 frame synchronization search unit searches is to synchronization frame; Then the synchronization status marker of this frame synchronization search unit output is put high level; If wherein 1 frame synchronization search unit does not search synchronization frame, then the synchronization status marker of this frame synchronization search unit output keeps low level constant.
- Serial data as claimed in claim 1 with the road clock extraction method, it is characterized in that: said step 6 comprises: if FLAG1 is a high level, then select CLK1 be recover with the road clock; If FLAG1 is 0, FLAG2 be 1 select CLK2 for recover with the road clock; And the like, if FLAG1 ..., FLAG (N-1) is 0, FLAGN be 1 select CLKN for recover with the road clock.
- As the described arbitrary serial data of claim 1 to 5 with the road clock extraction method, it is characterized in that: said Serial Data Transfer Mode medium is cable or optical fiber, or the backboard universal serial bus.
- As the described arbitrary serial data of claim 1 to 5 with the road clock extraction method, it is characterized in that: said N clock value is 4 clocks.
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| CN103684736A (en) * | 2013-11-21 | 2014-03-26 | 国网上海市电力公司 | Clock synchronization method for high-speed communication |
| WO2017059822A1 (en) * | 2015-10-08 | 2017-04-13 | 深圳市中兴微电子技术有限公司 | Inter-chip communication method, system and computer storage medium |
| CN106788955A (en) * | 2016-12-26 | 2017-05-31 | 中核控制系统工程有限公司 | A kind of four phase high speed symbol detection methods |
| CN110046125A (en) * | 2019-04-16 | 2019-07-23 | 深圳市致宸信息科技有限公司 | A kind of same frequency sequential serial method of data synchronization and device |
| CN112838860A (en) * | 2019-11-23 | 2021-05-25 | 西安诺瓦星云科技股份有限公司 | Data output method, device and system |
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