CN102820763B - High-precision pulse width division realizing method for pulse width control of power converter - Google Patents
High-precision pulse width division realizing method for pulse width control of power converter Download PDFInfo
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Abstract
The invention discloses a high-precision pulse width division realizing method for the pulse width control of a power converter. A device for realizing the method comprises a clock generating module, a pulse width metering module, a metering storage module and a division module, wherein the clock generating module is used for generating a clock signal; the pulse width metering module is used for metering pulse width; the metering storage module is used for storing a pulse width metering result; the division module is used for calculating and converting the stored pulse width metering result into simulation voltage to be output; the pulse width metering module is used for metering two pulse width signals; the clock generating module generates a fixed clock according to metered pulse width and a metered precision requirement, and the clock is output and serves as a reference clock of the pulse width metering module; the pulse width metering module respectively meters and outputs the two input pulse width signals; the metering storage module stores the output of the pulse width metering module when each period of the metered pulse width ends, keeps the output until the next period ends and plays the role of sampling and keeping; and the division module performs digital-to-analog conversion according to the digital amount of the metering storage module and simultaneously performs division operation.
Description
Technical field
The present invention relates to pulsewidth division implementation method.More particularly, the present invention relates to the enforcement of a kind of new high accuracy pulsewidth division implementation method for the various pulse width control schemes of power inverter.
Background technology
In the existing implementation that uses pulsewidth division circuit (Fig. 1), it is first to convert corresponding pulsewidth amount to corresponding analog quantity, and the division calculation that then completes these two analog quantitys by simulation division circuit is exported corresponding analog quantity quotient.Specifically, it needs first to convert corresponding pulse width signal to analog voltage signal through integrating circuit, and sampling hold circuit is sampled and kept processing this analog voltage signal; Voltage-current converter circuit is responsible for changing the analog voltage signal receiving into corresponding analog current signal.Two kinds of analog current signals (being for example ON time ton and analog current signal corresponding to cycle pulsewidth length ts described in Fig. 2) calculate output analog quantity quotient electric current by simulation division circuit.Current-to-voltage converting circuit converts above-mentioned analog quantity quotient electric current to analog quantity quotient voltage signal more again.The analog quantity quotient voltage signal of output has been used for corresponding pulse width control scheme.Due to the corresponding integrating circuit of the wide dynamic range of pulsewidth, to realize difficulty large, and high to analog sampling holding circuit precision prescribed, thereby cause corresponding sampling hold circuit area occupied large; In addition simulation division circuit and various voltage-current converter circuit be limited by that precision is low, circuit is complicated, to the high restriction of manufacturing technique requirent, the cost of realizing that these have limited the precision of pulsewidth division circuit and have greatly increased this pulsewidth division circuit.
Summary of the invention
The invention provides a kind of high accuracy pulsewidth division implementation method for power inverter pulse width control, it makes to realize for the high accuracy pulsewidth division of power inverter control, and circuit is simple, precision is high, cost is low, be applicable to different production technologies; Can carry out accurate Calculation output to different time quantums for different power inverter topological structures.
High accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention forms (as shown in Figure 3) by following functional block: the pulsewidth metering module of the clock generating module of clocking, metering pulsewidth, for storing the meter store module of pulsewidth metering result and the pulsewidth metering result of storage being calculated and changed into the division module of analog voltage output; Described pulsewidth metering module is for measuring respectively two kinds of pulse width signals.
Clock generating module produces fixing clock output according to the required precision of the pulsewidth of metering and metering, as the reference clock of metering module; According to different capacity converter topology control structure, pulsewidth metering module measures and exports two kinds of pulse width signals of input respectively; Meter store module is stored the output of pulsewidth metering module in the time that measured pulsewidth each cycle finishes, and remains to next end cycle, the effect that this module plays sampling and keeps; Division module is carried out digital simulation conversion and carries out division arithmetic simultaneously according to the digital quantity of meter store module stores; Pulse width signal measures by digital mode, and division module comprises two digital to analog converters (, D/A converter module), and the output of one of them digital to analog converter is carried out division arithmetic as the reference quantity of another one digital to analog converter.
Improvement as the high accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention: pulse width signal comprises ON time (Ton), turn-off time (Toff), interrupting time (Tdis) and cycle pulsewidth length (Ts).
Further improvement as the high accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention: division module comprises amplifier A, field effect transistor Q, weighted resistance network RA, current mirror Icouple and weighted resistance network RB; Amplifier A and field effect transistor Q and weighted resistance network RA form a current source, and the value of described current source is to be determined divided by weighted resistance network RA by reference voltage Vr; The value of this current source exports weighted resistance network RB to through current mirror Icouple coupling, produces corresponding analog voltage.
Further improvement as the high accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention: the switching network that weighted resistance network RA comprises memory control, weighted resistance network RA resistance value is with 2 system adaptability in tactics; In weighted resistance network RB, comprise another switching network of memory control, weighted resistance network RB resistance value is with 2 system adaptability in tactics.
High accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention, the various pulse width control schemes that can be used for different topological structures are used in various application scenarios, as light-emitting diode drives application and battery charging application, AC/DC convertor etc.
Tool of the present invention has the following advantages:
1, the present invention is hybrid digital analog circuit, and it makes full use of the feature of digital circuit, has simplified the simulation circuit structure in existing pulsewidth division circuit; Use again the method for analog circuit, simplified the labyrinth of digital divider;
2, can realize the pulsewidth division under wide dynamic range;
3, the present invention can realize high accuracy, low cost;
4,, by the selection to different pulsewidth measurement clock frequencies, can effectively overcome the error of limited wordlength.
Brief description of the drawings
Fig. 1 is the block diagram of existing pulsewidth division circuit;
Fig. 2 is 2 kinds of different pulse sequence diagrams;
Fig. 3 is the block diagram of the high accuracy pulsewidth division implementation method for power inverter pulse width control of the present invention;
The embodiment schematic diagram of what Fig. 4 was corresponding is in Fig. 3 clock generating module, pulsewidth metering module, meter store module;
What Fig. 5 was corresponding is the embodiment schematic diagram of the division module in Fig. 3.
Embodiment
Embodiment 1, a kind of high accuracy pulsewidth division implementation method for power inverter pulse width control, as shown in Figure 4 and Figure 5, comprise the counter of clock generation circuit, the metering pulsewidth of clocking, for storing the memory of pulsewidth metering result, above-mentioned 3 all can design according to conventional digital circuit design method.
Control method of the present invention also comprises the division module of the pulsewidth metering result of storage being calculated and changed into analog voltage output; It specifically as shown in Figure 5;
Comprise amplifier A, field effect transistor Q, weighted resistance network RA, current mirror Icouple, weighted resistance network RB; Amplifier A and field effect transistor Q and weighted resistance network RA form a current source, and the value of described current source is to be determined divided by weighted resistance network RA by reference voltage Vr; The value of this current source exports weighted resistance network RB to through current mirror Icouple coupling, produces corresponding analog voltage.The switching network that comprises a memory control in weighted resistance network RA, weighted resistance network RA resistance value is with 2 system adaptability in tactics; In like manner, also comprise the switching network of a memory control in weighted resistance network RB, weighted resistance network RB resistance value is with 2 system adaptability in tactics.
Concrete enforcement principle is as follows:
1, for example to obtain the pulse division of ts/toff, as shown in Fig. 4; Ts represents cycle pulsewidth length, and Toff represents the turn-off time; High frequency clock is produced by clock generation circuit, and measured pulsewidth is respectively Ts and Toff;
Counter is counted respectively Ts and Toff according to high frequency clock, can obtain respectively corresponding Dts and the digital quantity of Dtoff, and is stored in accordingly respectively in memory in 2 different address locations.Because adopt identical clock metering, so ts/toff=Dts/Dtoff.As shown in Figure 5, can be used for control resistor network RA obtain the result of a corresponding resistance value as digital-to-analogue conversion by digital-to-analogue conversion piece Dtoff, this resistance value can represent with Dtoff × R.In like manner, can be used for control resistor network RB by digital-to-analogue conversion piece Dts and obtain a corresponding resistance value, represent with Dts × R.Remarks explanation: Dts characterizes corresponding cycle pulsewidth digital quantity, and Dtoff characterizes corresponding turn-off time pulsewidth digital quantity.
A fixing reference voltage Vr(external world provides) can on Dtoff × R resistance string, produce a reference current I: this reference current I produces corresponding reference current I ' by current mirror Icouple, this reference current I ' acts on Dts × R resistance and obtains a voltage, as shown in Figure 5:
I =Vr /（Dtoff×R）
Vo= I’×（Dts×R）
In the time of I '=I,
Vo =Vr×（Dts×R）/（Dtoff×R)
=Vr×（Dts/Dtoff）
Vr is an any given constant, and Vo output just represents the result of ts/toff, irrelevant with the size of resistance R, obtains the output voltage of a result of division according to reference voltage simultaneously.
Seen by above-mentioned pulsewidth division implementation method, if the relative quantity of these two pulsewidth amounts (being ts, toff) differs greatly all the time, avoid the error of effective word length and ensure enough division precision, can change the corresponding clock frequency to these two pulsewidth meterings, wide pulse width is measured with standard metering clock, and narrow pulsewidth is used higher than the clock of standard metering clock K multiple and measured.Now, make I '=K I doubly; Therefore the business who draws through this division is through taking advantage of accordingly or obtaining avoiding the exact division quotient of effective word length error except corresponding multiple K.
2, for example to obtain the pulse division of Ton/Ts, as shown in Fig. 4; Ts represents cycle pulsewidth length, and Ton represents ON time; High frequency clock is produced by clock generation circuit, and measured pulsewidth is respectively Ts and Ton;
Counter is counted respectively Ts and Ton according to high frequency clock, can obtain respectively corresponding Dts and the digital quantity of Dton, and is stored in accordingly respectively in memory in 2 different address locations.Because adopt identical clock metering, so Ton/Ts=Dton/Dts.
Can be used for control resistor network RA by digital-to-analogue conversion piece Dts and obtain the result of a corresponding resistance value as digital-to-analogue conversion, this resistance value can represent with Dts × R.In like manner, can be used for control resistor network RB by digital-to-analogue conversion piece Dton and obtain a corresponding resistance value, represent with Dton × R.
Remarks explanation: Dts characterizes corresponding cycle pulsewidth digital quantity, and Dton characterizes corresponding ON time pulsewidth digital quantity.
A fixing reference voltage Vr(external world provides) can on Dts × R resistance string, produce a reference current I: this reference current I produces corresponding reference current I ' by current mirror Icouple, and this reference current I ' acts on and on Dton × R resistance, obtains a voltage:
I =Vr /（Dts×R）
Vo= I’×（Dton×R）
In the time of I '=I,
Vo =Vr×（Dton×R）/（Dts×R)
=Vr×（Dton/Dts）
Vr is an any given constant, and Vo output just represents the result of ton/ts, irrelevant with the size of resistance R, obtains the output voltage of a result of division according to reference voltage simultaneously.
Seen by above-mentioned pulsewidth division implementation method, if the relative quantity of these two pulsewidth amounts (being ts, ton) differs greatly all the time, avoid the error of effective word length and ensure enough division precision, can change the corresponding clock frequency to these two pulsewidth meterings, wide pulse width is measured with standard metering clock, and narrow pulsewidth is used higher than the clock of standard metering clock K multiple and measured.Now, make I '=K I doubly; Therefore the business who draws through this division is through taking advantage of accordingly or obtaining avoiding the exact division quotient of effective word length error except corresponding multiple K.
3, for example to obtain Toff/Ts pulse division or will obtain Toff/Ton pulse division or will obtain (Ton+Toff)/Ts pulse division, all can be equal to above-mentioned steps 1 and step 2 and operate.
Finally, it is also to be noted that, what more than enumerate is only several specific embodiments of the present invention.Obviously, the invention is not restricted to above embodiment, can also have many distortion.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention, all should think protection scope of the present invention.
Claims (3)
1. for the high accuracy pulsewidth division implementation method of power inverter pulse width control, it is characterized in that:
Comprise the pulsewidth metering module of clock generating module, the metering pulsewidth of clocking, for storing the meter store module of pulsewidth metering result and the pulsewidth metering result of storage being calculated and changed into the division module of analog voltage output; Pulsewidth metering module is used for measuring two kinds of pulse width signals;
Clock generating module produces fixing clock output according to the required precision of the pulsewidth of metering and metering, as the reference clock of pulsewidth metering module; Pulsewidth metering module measures and exports two kinds of pulse width signals of input respectively; Meter store module is stored the output of pulsewidth metering module in the time that measured pulsewidth each cycle finishes, and remains to next end cycle, the effect that described meter store module plays sampling and keeps;
Division module is carried out digital simulation conversion and carries out division arithmetic simultaneously according to the digital quantity of meter store module stores; Division module comprises two digital to analog converters, and the output of one of them digital to analog converter is carried out division arithmetic as the reference quantity of another one digital to analog converter;
Pulse width signal comprises ON time Ton, turn-off time Toff, interrupting time Tdis and cycle pulsewidth length T s;
Described division module comprises amplifier A, field effect transistor Q, weighted resistance network RA, current mirror Icouple and weighted resistance network RB; Amplifier A and field effect transistor Q and weighted resistance network RA form a current source, and the value of described current source is to be determined divided by weighted resistance network RA by reference voltage Vr; The value of this current source exports weighted resistance network RB to through current mirror Icouple coupling, produces corresponding analog voltage.
2. the high accuracy pulsewidth division implementation method for power inverter pulse width control according to claim 1, is characterized in that:
The switching network that comprises a memory control in weighted resistance network RA, weighted resistance network RA resistance value is with 2 system adaptability in tactics; In weighted resistance network RB, also comprise the switching network of a memory control, weighted resistance network RB resistance value is with 2 system adaptability in tactics.
3. the high accuracy pulsewidth division implementation method for power inverter pulse width control according to claim 2, is characterized in that:
Obtain the pulse division of ts/toff, Ts represents cycle pulsewidth length, and Toff represents the turn-off time; High frequency clock is produced by clock generation circuit, and measured pulsewidth is respectively Ts and Toff;
Counter is counted respectively Ts and Toff according to high frequency clock, obtains respectively corresponding Dts and the digital quantity of Dtoff, and is stored in accordingly respectively in memory in 2 different address locations; Because adopt identical clock metering, so ts/toff=Dts/Dtoff; Be used for control resistor network RA by digital-to-analogue conversion piece Dtoff and obtain the result of a corresponding resistance value as digital-to-analogue conversion, this resistance value represents with Dtoff × R; Be used for control resistor network RB by digital-to-analogue conversion piece Dts and obtain a corresponding resistance value, this resistance value is with representing with Dts × R;
Reference voltage Vr produces a reference current I on Dtoff × R resistance string; This reference current I produces corresponding reference current I ' by current mirror Icouple, and this reference current I ' acts on and on Dts × R resistance, obtains a voltage:
I＝Vr/(Dtoff×R)
Vo＝I’×(Dts×R)
In the time of I '=I,
Vo＝Vr×(Dts×R)/(Dtoff×R)
＝Vr×(Dts/Dtoff)；
Described Vo output just represents the result of ts/toff, irrelevant with the size of resistance R; Obtain the output voltage of a result of division according to reference voltage Vr.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1402908A (en) * | 1999-11-30 | 2003-03-12 | 雅马哈株式会社 | Digital-to-analog converter |
| CN101452023A (en) * | 2007-12-06 | 2009-06-10 | 亚全科技股份有限公司 | Pulsewidth regulating action cycle detecting circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1402908A (en) * | 1999-11-30 | 2003-03-12 | 雅马哈株式会社 | Digital-to-analog converter |
| CN101452023A (en) * | 2007-12-06 | 2009-06-10 | 亚全科技股份有限公司 | Pulsewidth regulating action cycle detecting circuit |
Non-Patent Citations (2)
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| 一种新型模拟除法器及其应用;韩国栋等;《仪器仪表学报》;20011031;第22卷(第5期);527-529 * |
| 韩国栋等.一种新型模拟除法器及其应用.《仪器仪表学报》.2001,第22卷(第5期),527-529. |
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