CN102820269B - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
- Publication number
- CN102820269B CN102820269B CN201210179353.3A CN201210179353A CN102820269B CN 102820269 B CN102820269 B CN 102820269B CN 201210179353 A CN201210179353 A CN 201210179353A CN 102820269 B CN102820269 B CN 102820269B
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- chip
- furcella
- electrode
- semiconductor device
- pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides and can realize semiconductor device that the few flip-chip of heat transfer loss between chip and printed base plate installs and manufacture method thereof.This semiconductor device has: printed base plate, its interarea is configured with the electrode of substrate pad being formed with the multiple furcellas be made up of graphite on surface; And chip, the interarea of itself and electrode of substrate pad subtend is configured with surface configuration have with furcella before the chip electrode pad of electroconductive resin film of end in contact.
Description
Technical field
The present invention relates to the semiconductor device and manufacture method thereof that have on printed base plate, carried out the chip that flip-chip is installed.
Background technology
As the method chip being formed with semiconductor element is installed on printed base plate, employ flip-chip and install.Such as, by carrying out flip-chip installation to light-emitting diode (LED), the electrode be configured in LED light-emitting area can be reduced.Therefore, the luminous efficiency of LED improves.
In order to carry out flip-chip installation to LED, have studied and be configured at (for example, referring to patent documentations 1) such as the methods that the electrode on LED formed projection.By by the projection be formed on LED, be electrically connected with the pad be configured on printed base plate, LED is electrically connected with printed base plate.
About projection generation type, there are ball bonding method, print process etc.Such as, at printed on electrodes soldering paste, after coating flux, carry soldered ball.Further, by reflux technique ,/melting is heated to solder, electrode is connected with pad.Therefore, grafting material is various solders, engages " wetability " on composition surface when principle is solder heating and " the metal alloy formation " for composition surface.
[patent documentation 1] Japan is real is willing to flat 11-7004 publication
But, when being installed on printed base plate by flip-chip chip by projection, owing to generating bonding interface (contact resistance) between grafting material and pad, therefore there is the problem that heat transfer loss is large.
Summary of the invention
The present invention completes in view of the above problems, its object is to, and provides and can realize semiconductor device that the few flip-chip of heat transfer loss between chip and printed base plate installs and manufacture method thereof.
According to a mode of the present invention, provide semiconductor device, it has: (A) printed base plate, its interarea is configured with electrode of substrate pad, and this electrode of substrate pad is formed with the multiple furcellas be made up of graphite on surface; And (B) chip, its interarea relative with electrode of substrate pad is configured with chip electrode pad, this chip electrode pad surface configuration have with furcella before the electroconductive resin film of end in contact.
According to other modes of the present invention, provide the manufacture method of semiconductor device, comprise the steps: that (A) forms electroconductive resin film on the surface being configured at the chip electrode pad on chip; (B) on printed base plate, form electrode of substrate pad, this electrode of substrate pad is formed with the multiple furcellas be made up of graphite on surface; And (C) makes chip electrode pad relative with electrode of substrate pad, the front end of furcella is contacted with electroconductive resin film, make chip and printed base plate electrical connection.
According to the present invention, can provide and can realize semiconductor device that the few flip-chip of heat transfer loss between chip and printed base plate installs and manufacture method thereof.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the structure of the semiconductor device that embodiments of the present invention are shown.
Fig. 2 is the block diagram (one) of the manufacture method for illustration of the semiconductor device shown in Fig. 1.
Fig. 3 is the block diagram (its two) of the manufacture method for illustration of the semiconductor device shown in Fig. 1.
Fig. 4 is the block diagram (its three) of the manufacture method for illustration of the semiconductor device shown in Fig. 1.
Fig. 5 is the block diagram (its four) of the manufacture method for illustration of the semiconductor device shown in Fig. 1.
Fig. 6 is the photo of the shape of the furcella formed on semiconductor devices that embodiments of the present invention are shown.
Fig. 7 is the enlarged photograph of the furcella of the semiconductor device of embodiments of the present invention.
Fig. 8 is the schematic diagram of the structure of the semiconductor device that other execution modes of the present invention are shown.
Fig. 9 is the block diagram of the example of the autofrettage of the semiconductor device that embodiments of the present invention are shown.
Figure 10 is the schematic diagram of the structure of the semiconductor device that comparative example is shown.
Figure 11 is the table that the thermal conductivity of grafting material and the comparison of specific insulation are shown.
Figure 12 is the table of the comparison of the specific insulation that electroconductive resin film is shown.
Figure 13 is the schematic diagram of the structure of the semiconductor device that other execution modes of the present invention are shown.
Symbol description
1 ... semiconductor device
20 ... printed base plate
21 ... electrode of substrate pad
30 ... furcella
40 ... electroconductive resin film
50 ... chip
51 ... chip electrode pad
60 ... pillar
100 ... solder projection
210 ... substrate mask
300 ... vapor-deposited film
310 ... particle
Embodiment
Then, with reference to accompanying drawing, embodiments of the present invention are described.In the record of following accompanying drawing, same or similar part encloses same or similar symbol.But accompanying drawing is the figure of signal, the ratio of the thickness of each several part etc. should be noticed different from reality.Therefore, concrete thickness and size should be considered the following description to judge.Further, size relationship each other or the different part of ratio is certainly also comprised each other at accompanying drawing.
Further, execution mode shown below, exemplified with the apparatus and method for specializing technological thought of the present invention, in embodiments of the present invention, the material, shape, structure, configuration etc. of component parts are not limited to following content.Various change can be implemented within the scope of the claims to embodiments of the present invention.
As shown in Figure 1, the semiconductor device 1 of embodiments of the present invention has: printed base plate 20, and it is configured with electrode of substrate pad 21 on interarea 201, and this electrode of substrate pad 21 is formed with the multiple furcellas 30 be made up of graphite on surface; And chip 50, it is configured with chip electrode pad 51 on interarea 501, and this chip electrode pad 51 is at the conductive resin molding 40 of surface configuration.In the example depicted in figure 1, the vapor-deposited film 300 being formed with multiple furcella 30 is configured on electrode of substrate pad 21.As described later, vapor-deposited film 300 is made up of carborundum (SiC) film.
As shown in Figure 1, with the chip electrode pad 51 mode configuring chip 50 relative with electrode of substrate pad 21 and printed base plate 20.By making the front end of furcella 30 contact with electroconductive resin film 40, chip 50 is electrically connected with printed base plate 20.
Chip 50 is formed with the semiconductor elements such as LED, at printed base plate 20 flip-chip-on, chip 50 is installed.Such as when chip 50 is LED, make the face beyond the light-emitting area of LED relative with printed base plate 20.Thereby, it is possible to improve the luminous efficiency of LED.
Printed base plate 20 has the structure such as defining metal wiring on aluminum oxide substrate.Be configured with electrode of substrate pad 21 being formed at the assigned position on the metal wiring on printed base plate 20 (diagram slightly).
Below, the example of the manufacture method of the semiconductor device 1 shown in key diagram 1.In addition, the manufacture method of the semiconductor device 1 of the following stated is an example, certainly comprises its variation, can be realized by the various manufacture methods beyond these.
As may be appreciated in the cross-sectional view of figure 2, on the chip electrode pad 51 on the interarea 501 being configured at chip 50, such as, by printing coatings such as silk screen printings, form electroconductive resin film 40 according to mask pattern.Or, also can be coated with by spreader and form electroconductive resin film 40.The thickness of electroconductive resin film 40 is such as less than 1 μm.
Now, as shown in Figure 2, the surface of chip electrode pad 51 is preferably configured to dig as the shape against cone shape in the mode that central part is lower than periphery.Such as, by chemical etching process and machining, the surface of chip electrode pad 51 is formed as concave shape.
On the other hand, on the electrode of substrate pad 21 on the interarea 201 of printed base plate 20, form the vapor-deposited film 300 be made up of carborundum (SiC) film.The position that printed base plate 20 is formed vapor-deposited film 300 is specified by mask pattern, with corresponding with the position of chip electrode pad 51.Such as employ physical vapour deposition (PVD) (PVD) sputtering method etc. of substrate mask, assigned position is formed vapor-deposited film 300.
Specifically, as shown in Figure 3, only to expose the mode in the region being configured with electrode of substrate pad 21, patterned substrate mask 210 on the interarea 201 of printed base plate 20.Further, by PVD sputtering method, SiC particle is piled up in the region of exposing of the interarea 201 of printed base plate 20, as shown in Figure 4, form the vapor-deposited film 300 be made up of SiC.
Afterwards, processed by the reactive ion etching (RIE) based on plasma etching apparatus etc., carry out the shaggy process making vapor-deposited film 300.Thus, as shown in Figure 5, the surface of vapor-deposited film 300 is formed the multiple furcellas 30 be made up of graphite.
Formed in the reactive ion etch process of furcella 30 on the surface of vapor-deposited film 300, as etching gas, such as effectively Nitrogen trifluoride (NF
3) gas, carbon tetrafluoride (CF
4) gas etc.By the NF based on high frequency plasma
3gas or CF
4downstream etch (the Down Flow Etching) process of the free radicals such as gas, makes silicon (Si) turn to hexa-fluoride (SiF from SiC crystal (polycrystalline) gas on vapor-deposited film 300 surface
6) etc. and gasify.Thus, the surface of vapor-deposited film 300 is formed as shown in Figure 6, multiple furcellas 30 of being made up of graphite.Length and the thickness of furcella 30 can be adjusted by etchant gas flow, concentration, etching period.
The example being exaggerated furcella 30 is shown at Fig. 7.The size of furcella 30, such as, be highly more than 5 μm, and the diameter of bottom is 0.1 μm ~ about 1.0 μm.In addition, the distance between adjacent furcella 30 is 0.1 μm ~ about 1.0 μm.Because furcella 30 is formed close, even if therefore the diameter of chip electrode pad 51 is such as about 30 μm, also chip electrode pad 51 and electrode of substrate pad 21 can be connected by the furcella 30 of quantity sufficient.
After the surface of vapor-deposited film 300 defines furcella 30, remove substrate mask 210.
Then, in the mode that chip electrode pad 51 is relative with electrode of substrate pad 21, the aligning of chip 50 and printed base plate 20 is carried out.Further, the front end of furcella 30 is made to contact with the electroconductive resin film 40 be configured on chip electrode pad 51 surface.
Reflux under the state that furcella 30 contacts with electroconductive resin film 40.Such as, chip 50 and printed base plate 20 are put into heating oven, make electroconductive resin film 40 and furcella 30 thermo-contact sclerosis.Backflow is carried out at 80 DEG C ~ 120 DEG C.Now, also can apply weak load from chip 50 side, thus carry out the bonding of electroconductive resin film 40 and furcella 30 more reliably.
Thus, complete the electrical connection between chip 50 and printed base plate 20, complete the semiconductor device 1 shown in Fig. 1.
In above-mentioned, describe method as described below: define the vapor-deposited film 300 be made up of SiC on the electrode of substrate pad 21 being configured at the assigned position on printed base plate 20 after, form furcella 30 on the surface of vapor-deposited film 300.But, as shown in Figure 8, by being bonded on electrode of substrate pad 21 by the particle 310 being formed with furcella 30, also multiple furcella 30 can be formed on the surface of electrode of substrate pad 21.Particle 310 has the structure defining furcella 30 at SiC film and core 31.
Particle 310 is such as formed in the manner as described below.By hot-press arrangement under the high temperature of 1000 DEG C ~ 2500 DEG C and 50 ~ 200kg/cm
2condition of high voltage under, the SiC particulate of tens nm ~ hundreds of μm diameter is sintered.Further, by processing machine, sintering disk is shaped to suitable grain shape as pad.
In order to form the furcella 30 be made up of graphite on the surface of the particle 310 be made up of SiC, processed particle 310 by HF vapor-gas phase cleaning machine etc., the oxide-film carrying out surface is removed.Afterwards, in the same manner as the method illustrated, by plasma-etching apparatus etc., reactive ion etch process is carried out to the face needed for the electrical connection of particle 310, the surface of particle 310 is formed multiple furcella 30.
When chip 50 is carried printed base plate 20, need to make to maintain a certain distance between chip 50 and printed base plate 20.Example shown in Fig. 9 is example as described below: between chip 50 and printed base plate 20, configure pillar 60, and the distance between chip 50 and printed base plate 20 is kept constant.The height of pillar 60 is that the mode contacted with electroconductive resin film 40 with the front end of furcella 30 sets.Afterwards, such as, between chip 50 and printed base plate 20, inject the underfill agent such as insulative resin, fix chip 50 and printed base plate 20.
The furcella 30 be made up of graphite has elastic force.Therefore, even if when multiple chip electrode pads 51 of height different from each other are configured on chip 50, also highly different chip electrode pads 51 can be connected with electrode of substrate pad 21 simultaneously.Fig. 9 illustratively illustrates the situation that chip electrode pad 51B is higher than chip electrode pad 51A.
According to said method, the front end of furcella 30 can be made stably to contact with electroconductive resin film 40.Therefore, it is possible to avoid the front end of furcella 30 not arrive electroconductive resin film 40, or furcella 30 entirety is buried to the medium problem of electroconductive resin film 40.The entirety of furcella 30 is buried in electroconductive resin film 40 thermal diffusivity that can reduce on furcella 30, is therefore worthless.
In the flip-chip in the past relevant with semiconductor elements such as LED is installed, as shown in Figure 10, the electrode of substrate pad 21 of the chip electrode pad 51 and printed base plate 20 that are formed with the chip 50 of semiconductor element is engaged by solder projection 100.That is, by solder projection 100, be formed in the electrical connection between semiconductor element and the Wiring pattern formed on printed base plate 20 that chip 50 is formed.
In the flip-chip shown in Figure 10 is installed, when solder projection 100 melting, space can occur in existence formation and part stripping etc. engage bad drawback.And, in joint technology, the position skew between electrode pad can be produced when solder projection 100 melting, there is degradation problem under positioning precision.
In contrast, in the semiconductor device 1 of embodiments of the present invention, use and different materials is installed to improve characteristic from existing flip-chip.Namely, there is structure as described below: replace solder projection and use the furcella 30 be made up of graphite, SiC film is employed for pad.
As mentioned above, in semiconductor device 1, by being formed in the furcella 30 of the aciculiform shape be made up of graphite on SiC film, chip 50 and printed base plate 20 are electrically connected.Therefore, according to semiconductor device 1, the electrical connection occurred on the flip-chip employing solder projection can be reduced bad.The formation in space when namely, there will not be solder projection to dissolve and position skew that is bad from joints such as bonding plane strippings and adhesive surface.And, in semiconductor device 1, owing to being realized connecting by the point cantact of multiple furcella 30, therefore there will not be the stripping in part face.
As shown in figure 11, the thermal conductance of graphite fibre is about 20 times of solder projection.The thermal conductance of SiC particle, for retaining SiC film and poorer than graphite fibre, but height more abundant than solder projection.Therefore, in the semiconductor device 1 of furcella 30 using graphite, the good and low-resistance electrical connection of thermal diffusivity can be realized.
And as illustrated, furcella 30 is directly formed from the surface portion of SiC film by etch processes, be not formed by the deposition juncture as carbon nano-tube (CNT) etc.Therefore, furcella 30 does not exist joint interface, the quantity of the bonding interface between chip 50 and printed base plate 20 reduces.Thus, suppress the heat transfer loss produced through interface, reduce the heat transfer loss on furcella 30.That is, the thermal diffusivity of semiconductor device 1 is improved.
In addition, by adopting high thermal conductivity material to electroconductive resin film 40, thus reducing based on the deviation of the heat transfer area of the Multi-contact between furcella 30 and chip electrode pad 51, improving thermal diffusivity.When considering from the resistivity of each material shown in Figure 12, such as copper cream etc. are suitable for electroconductive resin film 40.
In addition, graphite is threadiness and has elastic force.Therefore, when employing the furcella 30 be made up of graphite, be difficult to produce the crackle based on the junction of thermal expansion/contraction and stripping when joint with chip electrode pad 51 of electrode of substrate pad 21.
Printed base plate 20 is formed vapor-deposited film 300 situation and on electrode of substrate pad 21 bonding particle 310, the bottom of furcella 30 also exists each furcella 30 the SiC film that shares.Therefore, furcella 30 can not come off as CNT, and hot strength is larger than CNT.
In addition, by the surface of chip electrode pad 51 is formed as concave shape, the cementability function between furcella 30 and chip electrode pad 51 can be improved.Namely, when by the surface contact of the front end of furcella 30 and chip electrode pad 51, the central portion of furcella 30 when not scattering to chip electrode pad 51 is close.Therefore, furcella 30 is suppressed to be given prominence to from chip electrode pad 51.Its result, reliably can connect chip 50 and printed base plate 20 further.
And, by the surface of chip electrode pad 51 is formed as concave shape, easily the electroconductive resin film 40 playing the bonding agent effect connecting chip 50 and printed base plate 20 is injected into the surface of chip electrode pad 51.In addition, electroconductive resin film 40 is difficult to spill from the surface of chip electrode pad 51.In addition, in order to prevent electroconductive resin film 40 from hanging down from chip electrode pad 51, also chip 50 and printed base plate 20 can be connected being configured in by printed base plate 20 under the state above chip 50.
In addition, because the inside entirety of concave shape is chip electrode pad 51, therefore also conducting is contributed to when furcella 30 connects with the side of concave shape.
The thickness of electroconductive resin film 40, under the state being mounted on printed base plate 20 by chip 50, the very thin entirety being formed as furcella 30 can not bury the degree in electroconductive resin film 40.Thereby, it is possible to guarantee the heat radiation on furcella 30.The thickness of electroconductive resin film 40 is such as less than 1 μm.
When being electrically connected chip 50 and printed base plate 20 by electroconductive resin film 40, such as, can adopt method as described below.Namely, be coated on chip electrode pad 51 as the wire-conducting performance bonding agent of electroconductive resin film 40 by hardening at subcritical temerature type.Further, by carrying out dry fixed bonding in the drier being set as about 100 DEG C, bonding furcella 30 and electroconductive resin film 40.In contrast, when chip 50 and printed base plate 20 being electrically connected in use gold (Au) and solder, the temperature of chip 50 is about 200 DEG C.
Therefore, hardening at subcritical temerature can be carried out by using electroconductive resin film 40, the temperature of the chip 50 when flip-chip is installed can be reduced.Its result, can suppress the impact of heat on chip 50, reduce the heat load of chip 50.
In addition, also can in the front end of furcella 30 applying conductive resin molding 40 instead of chip electrode pad 51 in advance.Due to the front end close-packed arrays of furcella 30, therefore, it is possible to electroconductive resin film 40 to be coated on the front end of furcella 30.
As mentioned above, the thermal conductance of the furcella 30 be made up of graphite is very high.Therefore, as shown in figure 13, also multiple furcella 30A can be configured on the interarea 502 relative with printed base plate 20 of chip 50.In the semiconductor device 1 shown in Figure 13, to be made up of the graphite that thermal conductance is good and the large furcella 30A of surface area by using, to carry out the heat radiation of chip 50 efficiently.
As described above, in the semiconductor device 1 of embodiments of the present invention, on the surface of the electrode of substrate pad 21 on the interarea 201 being configured at printed base plate 20, be formed with the furcella 30 be made up of graphite.Further, carry out the electroconductive resin film 40 of configuration on the chip electrode pad 51 on the interarea 501 of chip 50 and aiming at of furcella 30, thus chip 50 and printed base plate 20 are electrically connected.Its result, in the semiconductor device 1 shown in Fig. 1, the flip-chip that can realize heat transfer loss between chip 50 and printed base plate 20 few is installed.
In addition, according to semiconductor device 1, owing to being the point cantact based on multiple furcella 30, even if therefore substrate vibration etc. are also difficult to junction surface stripping occurs.In addition, high-precision aligning is not needed.Therefore, in semiconductor device 1, be difficult to that joint occurs bad.
As mentioned above, describe the present invention by execution mode, but should not be construed as and form the description of a part of this disclosure and accompanying drawing limits the present invention.Those skilled in the art can from the clearly various alternate embodiments of the disclosure, embodiment and application technology.
Such as, embodiments of the present invention, except carrying except LED on printed base plate 20, can also application in the flip-chip of semiconductor discrete block is installed.In addition, for printed base plate 20, also beyond aluminum oxide substrate, such as glass epoxy substrate can be used.
In addition, also can form the furcella 30 be made up of graphite on chip electrode pad 51, the surface of electrode of substrate pad 21 is formed as concave shape, by furcella 30, chip electrode pad 51 and electrode of substrate pad 21 are electrically connected.
As mentioned above, the present invention comprises the various execution modes etc. do not recorded certainly herein.Therefore, technical scope of the present invention is only determined by the specific item of the invention of suitable claim from above-mentioned explanation.
Claims (7)
1. a semiconductor device, is characterized in that having:
Printed base plate, its interarea is configured with electrode of substrate pad, and this electrode of substrate pad is formed with silicon carbide film on surface; And
Chip, its interarea relative with described electrode of substrate pad is configured with chip electrode pad, this chip electrode pad surface configuration have with multiple furcella before the electroconductive resin film of end in contact, described multiple furcella is made up of graphite, and is formed on the surface of described silicon carbide film.
2. semiconductor device according to claim 1, is characterized in that,
The surface being configured with described electroconductive resin film of described chip electrode pad is concave shape.
3. semiconductor device according to claim 1, is characterized in that,
Described multiple furcella makes silicon gasify from the surface gas of described silicon carbide film by carrying out reactive ion etch process, thus is formed at the surface of described silicon carbide film.
4. a manufacture method for semiconductor device, is characterized in that having following steps:
Electroconductive resin film is formed on the surface being configured at the chip electrode pad on chip;
Printed base plate is formed electrode of substrate pad, and this electrode of substrate pad is formed with silicon carbide film on surface, and this silicon carbide film is formed with the multiple furcellas be made up of graphite on surface; And
Make described chip electrode pad relative with described electrode of substrate pad, the front end of described furcella is contacted with described electroconductive resin film, make described chip and the electrical connection of described printed base plate.
5. the manufacture method of semiconductor device according to claim 4, is characterized in that,
The surface being formed with described electroconductive resin film of described chip electrode pad is formed as concave shape.
6. the manufacture method of the semiconductor device according to claim 4 or 5, is characterized in that,
The step forming described multiple furcella has following steps:
Described electrode of substrate pad is piled up carborundum particle to form described silicon carbide film; And
Make by carrying out reactive ion etch process silicon gasify from the surface gas of described silicon carbide film, thus form described multiple furcella on the surface of described silicon carbide film.
7. the manufacture method of the semiconductor device according to claim 4 or 5, is characterized in that,
The step forming described multiple furcella has following steps:
By the particles stick that is made up of described silicon carbide film on described electrode of substrate pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011-127979 | 2011-06-08 | ||
| JP2011127979A JP2012256665A (en) | 2011-06-08 | 2011-06-08 | Semiconductor device and manufacturing method of the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102820269A CN102820269A (en) | 2012-12-12 |
| CN102820269B true CN102820269B (en) | 2015-09-09 |
Family
ID=47304298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210179353.3A Expired - Fee Related CN102820269B (en) | 2011-06-08 | 2012-06-01 | Semiconductor device and manufacture method thereof |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2012256665A (en) |
| CN (1) | CN102820269B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014109711A1 (en) * | 2013-01-10 | 2014-07-17 | Heptagon Micro Optics Pte. Ltd. | Opto-electronic modules including features to help reduce stray light and/or optical cross-talk |
| US9496402B2 (en) | 2014-10-17 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate with silicon sidewall spacers |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3322446A (en) * | 1963-08-16 | 1967-05-30 | Conradty Fa C | Method of screw connecting carbon or graphite electrodes |
| EP0559109A1 (en) * | 1992-03-02 | 1993-09-08 | E.I. Du Pont De Nemours And Company | Tantalum solid electrolytic capacitor |
| CN100484343C (en) * | 2004-01-13 | 2009-04-29 | 侯松发 | Method of graphite electrode dip treating |
-
2011
- 2011-06-08 JP JP2011127979A patent/JP2012256665A/en not_active Withdrawn
-
2012
- 2012-06-01 CN CN201210179353.3A patent/CN102820269B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3322446A (en) * | 1963-08-16 | 1967-05-30 | Conradty Fa C | Method of screw connecting carbon or graphite electrodes |
| EP0559109A1 (en) * | 1992-03-02 | 1993-09-08 | E.I. Du Pont De Nemours And Company | Tantalum solid electrolytic capacitor |
| CN100484343C (en) * | 2004-01-13 | 2009-04-29 | 侯松发 | Method of graphite electrode dip treating |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102820269A (en) | 2012-12-12 |
| JP2012256665A (en) | 2012-12-27 |
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