CN102800652A - Overlay mark and method for fabricating the same - Google Patents
Overlay mark and method for fabricating the same Download PDFInfo
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- CN102800652A CN102800652A CN2011102014151A CN201110201415A CN102800652A CN 102800652 A CN102800652 A CN 102800652A CN 2011102014151 A CN2011102014151 A CN 2011102014151A CN 201110201415 A CN201110201415 A CN 201110201415A CN 102800652 A CN102800652 A CN 102800652A
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- Prior art keywords
- width
- overlapping mark
- separator
- overlapping
- mark
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The invention provides an overlay mark and a method for fabricating the same. The method for fabricating the overlay mark includes the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein each mark element forming region comprises two column recesses and a plurality of row recesses, and the row recesses connect the two column recesses; growing a mark material from the sidewalls of the column recesses and the row recesses so that the mark material merges in the column recesses and the row recesses; and removing the patterned layer. Consequently, an overlay mark including mark elements with high image contrast is fabricated.
Description
Technical field
The present invention relates to a kind of overlapping mark and preparation method thereof, particularly a kind of overlapping mark that is used for separator double patterning technology (spacer double patterning process) and preparation method thereof.
Background technology
Along with integrated circuit (Integrated Circuit, IC) live width of technology continues to dwindle, (critical dimension, control CD) is more and more important for the critical size of element.When technology need two zones that formation pattern arrangement kenel is different on a wafer layer, must carry out the different double exposure of conditions of exposure to the photoresist layers in two zones, that is carry out double exposure technology, make each zone have predetermined critical size respectively.When the spacing (pitch) of formation pattern during, can use this moment double exposure technology to make the satisfactory size of spacing of the pattern that forms less than the resolution of single exposure.
For making good IC products, carry out repeatedly pattern transfer processes usually, integrated circuit patterns is transferred to each layer (non-processing layer) that is untreated, to form IC apparatus.Therefore, when the critical size of semiconductor device is more and more little, the pattern of continuous pattern layer is aimed to reduce just fractal key more of dislocation.
Overlapping mark can be used for guaranteeing the alignment precision between the continuous pattern layer.That is to say, after forming continuous patterned layer, can carry out the step of confirming the overlapping mark alignment precision through overlapping mark with reference to said a plurality of continuous pattern layers.
Yet traditional indicia patterns is too thin and have a picture contrast extremely low with respect to the background material layer.That is, be difficult to by too thin indicia patterns identification overlapping mark.Therefore, for separator double patterning technology, be difficult to use traditional overlapping mark to keep watch on the performance of plyability.In addition, traditional overlapping mark can not be used for the measurement of plyability.
As stated, existing overlapping mark exists many problems.Therefore, be necessary to provide new overlapping mark and preparation method thereof, to address the above problem.
Summary of the invention
The purpose of this invention is to provide a kind of overlapping mark and a kind of overlapping mark preparation method, to solve above-mentioned the problems of the prior art.
The present invention provides a kind of overlapping mark; In one embodiment of this invention; This overlapping mark is arranged on the substrate, and it comprises a plurality of indexing units, and wherein each indexing unit comprises two staves and a plurality of lateral direction element; Said a plurality of lateral direction element connects said a plurality of stave to form a plurality of holes, and said a plurality of holes appear the part substrate between this two stave.
The present invention provides a kind of overlapping mark preparation method in addition.In one embodiment of this invention; This overlapping mark is the preparation method may further comprise the steps: form a patterned layer on a substrate; Wherein this patterned layer comprises that at least one indexing unit forms the zone; Each indexing unit forms the zone and comprises two vertical recess and a plurality of lateral recess, and said a plurality of lateral recess connect said a plurality of vertical recess; By the sidewall of said a plurality of vertical recesses and the said a plurality of lateral recess marker material of growing up, make this marker material in said a plurality of vertical recesses and said a plurality of lateral recess, merge linking; And remove this patterned layer.
Because the width of the indexing unit of overlapping mark of the present invention is greater than the width of the indexing unit of existing overlapping mark, therefore overlapping mark of the present invention can have higher picture contrast.That is, for separator double patterning technology, the performance of plyability can be kept watch on effectively, and the measurement of plyability can be overlapping mark of the present invention can be used for through overlapping mark of the present invention.
Preceding text are summarized technical characterictic of the present invention quite widely, are able to obtain preferable understanding so that the present invention of hereinafter describes in detail.Other technical characterictic that constitutes claim target of the present invention will be described in hereinafter.Under the present invention in the technical field those of ordinary skill should be appreciated that the notion that can quite easily utilize hereinafter to disclose can be used as modification with specific embodiment or designs other structure or technology and realize the purpose identical with the present invention.Those of ordinary skill also should be appreciated that the equivalent construction of this type can't break away from the appended the spirit and scope of the present invention that claim defined in the affiliated technical field of the present invention.
Description of drawings
Fig. 1 shows the top view of the partially patterned layer on one embodiment of the invention one substrate;
Fig. 2 shows along the cross sectional side view of Fig. 1 center line 1-1, vertical recess of its shows patterned metal layer;
Fig. 3 shows along the cross sectional side view of Fig. 1 center line 2-2, the lateral recess of its shows patterned metal layer;
Fig. 4 shows the sketch map of one embodiment of the invention growth marker material in patterned layer;
Fig. 5 shows along the cross sectional side view of Fig. 4 center line 3-3;
Fig. 6 shows along the cross sectional side view of Fig. 4 center line 4-4;
Fig. 7 shows the top view of the mark of overlapping of one embodiment of the invention;
Fig. 8 shows along the cross sectional side view of Fig. 7 center line 5-5;
Fig. 9 shows along the cross sectional side view of Fig. 7 center line 6-6;
Figure 10 shows the top view that has the multiple arrangement zone on the present invention's one substrate;
Figure 11 shows that one embodiment of the invention is positioned at the partial enlarged drawing of the overlapping mark in the overlapping alignment zone on this substrate; And
Figure 12-Figure 14 shows the sketch map that the difference of indexing unit of the present invention is arranged.
Wherein, description of reference numerals is following:
5 overlapping marks of the present invention
10 patterned layers
12 indexing units form the zone
16 vertical recesses
18 lateral recess
20 blocks
22 marker materials
30 silicon substrates
40 substrates
42 device zones
44 overlapping alignment zone
52 marked regions
54 indexing units
56 staves
58 lateral direction elements
60 holes
561,562 first separators
581,582 second separators
The width of X stave
X ' is the width of recess vertically
The width of Y lateral direction element
The width of Y ' lateral recess
The width of S1 first separator
The width of S2 second separator
Embodiment
Fig. 1-9 shows the overlapping mark preparation method's of one embodiment of the invention sketch map.Fig. 1 shows the top view of the partially patterned layer on one embodiment of the invention one substrate; Fig. 2 shows along the cross sectional side view of Fig. 1 center line 1-1, vertical recess of its shows patterned metal layer; Fig. 3 shows along the cross sectional side view of Fig. 1 center line 2-2, the lateral recess of its shows patterned metal layer.
With reference to figure 1-3, a patterned layer 10 (for example: Silicon Wafer) is formed at a silicon substrate 30.This patterned layer 10 can be a photoresist layer.This patterned layer 10 comprises that at least one indexing unit forms zone 12.In the present embodiment, each indexing unit forms zone 12 and comprises two vertical recess 16 and a plurality of lateral recess 18, and said a plurality of lateral recess 18 connects said a plurality of vertical recesses 16.
Each vertical recess 16 has a width X ', and the width X ' of this vertical recess 16 is less than 2 times first separator 561 or 562 width S 1 (by user's definition) (with reference to figure 5).Each lateral recess 18 has a width Y ', and the width Y ' of this lateral recess 18 is less than 2 times second separator 581 or 582 width S 2 (by user's definition) (with reference to figure 6).Be noted that the width S 2 of this second separator 581 or 582 can be same as or be different from the width S 1 of this first separator 561 or 562.
In the present embodiment, each indexing unit forms zone 12 and comprises a plurality of blocks (segments) 20 in addition, and said a plurality of blocks 20 are arranged between said a plurality of vertical recess 16 and the said a plurality of lateral recess 18 and the space.Said a plurality of block 20 is polygon or circle, or its combination, but not as limit.
Fig. 4 shows the sketch map of one embodiment of the invention growth marker material in patterned layer; Fig. 5 shows along the cross sectional side view of Fig. 4 center line 3-3; Fig. 6 shows along the cross sectional side view of Fig. 4 center line 4-4.With reference to figure 4-6,, make this marker material 22 in said a plurality of vertical recesses 16 and said a plurality of lateral recess 18, merge linking by the sidewall of said a plurality of vertical recesses 16 and said a plurality of lateral recess 18 marker material 22 of growing up.In an embodiment of the present invention, this marker material 22 is formed by SiGe, silica or silicon nitride.Except that above-mentioned material, this marker material 22 also can be formed by any suitable material.It is in an embodiment of the present invention, preferable that (low temperature chemical vapor deposition, LTCVD) method forms this marker material 22 with low temperature chemical vapor deposition.
Fig. 7 shows the top view of the mark of overlapping of one embodiment of the invention; Fig. 8 shows along the cross sectional side view of Fig. 7 center line 5-5; Fig. 9 shows along the cross sectional side view of Fig. 7 center line 6-6.With reference to figure 7-9, after forming this marker material 22, utilize an etching solution to remove this patterned layer 10.This etching solution can be acetone.So, can prepare completion overlapping mark of the present invention.
Figure 10 shows the top view that has multiple arrangement zone 42 on the present invention's one substrate 40; Figure 11 shows that one embodiment of the invention is positioned at the partial enlarged drawing of the overlapping mark 5 in the overlapping alignment zone 44 on this substrate 40.Be noted that Fig. 7 can be regarded as the part of Figure 11.With reference to Figure 10 and 11; In order to reach preferable overlapping alignment; This overlapping mark 5 that comprises a plurality of indexing units 54 is formed at this substrate, and (for example: a Silicon Wafer) on 40, in one embodiment of this invention, this indexing unit 54 is formed by SiGe, silica or silicon nitride.Except that above-mentioned material, this indexing unit 54 also can be formed by any suitable material.In an embodiment of the present invention, this overlapping mark 5 comprises a plurality of marked regions 52, and each marked region 52 comprises a plurality of indexing units 54.In the present embodiment, the arrangement mode of said a plurality of indexing units 54 is shown in figure 11, yet the arrangement mode of said a plurality of indexing unit 54 also can be like Figure 12, Figure 13 or shown in Figure 14, but not as limit.
Again with reference to figure 7-9; Each indexing unit 54 comprises two staves 56 and a plurality of lateral direction element 58; Said a plurality of lateral direction element 58 connects said a plurality of staves 56 to form a plurality of holes 60, and said a plurality of holes 60 appear the part substrate 30 of 56 of this two staves.Be noted that said a plurality of hole 60 can be polygon or circle, or its combination, but not as limit.
Each stave 56 has a width X, and the width X of this stave 56 is less than 2 times (with reference to figure 8) of the width S 1 of first separator 561 or 562, and wherein, each stave 56 is merged to be connected by 2 first separators 561 and 562 and forms.Each lateral direction element 58 has a width Y, and the width Y of this lateral direction element 58 is less than 2 times (with reference to figure 9) of the width S 2 of second separator 581 or 582, and wherein, each lateral direction element 58 is merged to be connected by 2 second separators 581 and 582 and forms.Be noted that the width S 2 of this second separator 581 or 582 can be same as or be different from the width S 1 of this first separator 561 or 562.
Because the width of the indexing unit 54 of overlapping mark 5 of the present invention is greater than the width of the indexing unit of existing overlapping mark, therefore overlapping mark 5 of the present invention can have higher picture contrast.That is, for separator double patterning technology, the performance of plyability can be kept watch on effectively, and the measurement of plyability can be overlapping mark 5 of the present invention can be used for through overlapping mark 5 of the present invention.
Technology contents of the present invention and technical characterstic have disclosed as above; Yet those of ordinary skill should be appreciated that in the affiliated technical field of the present invention; In the spirit and scope of the invention that does not deviate from accompanying claims and defined, teaching of the present invention and disclose and can do all replacements and modification.For example, many technologies that preceding text disclose can diverse ways be implemented or are replaced with other technology, perhaps adopt the combination of above-mentioned two kinds of modes.
In addition, claim scope of the present invention is not limited to technology, board, the manufacturing of the specific embodiment that preceding text disclose, composition, device, method or the step of material.Those of ordinary skill should be appreciated that in the affiliated technical field of the present invention; Based on teaching of the present invention and disclose composition, device, method or the step of technology, board, manufacturing, material; No matter existed now or developer in the future; It carries out the essence identical functions with the content that the embodiment of the invention discloses with the identical mode of essence, and reaches the identical result of essence, also can be used in the present invention.Therefore, following claim system is in order to contain composition, device, method or the step in order to this type of technology, board, manufacturing, material.
Claims (19)
1. an overlapping mark (5); Be positioned on the substrate; Comprise a plurality of indexing units (54), it is characterized in that each said indexing unit (54) comprises two staves (56) and a plurality of lateral direction element (58); Said a plurality of lateral direction element (58) connects said a plurality of staves (56) to form a plurality of holes (60), and said a plurality of holes (60) appear the part substrate between this two stave (56).
2. overlapping mark as claimed in claim 1 (5) is characterized in that, this overlapping mark (5) is formed on the silicon substrate (30).
3. overlapping mark as claimed in claim 1 (5) is characterized in that, this overlapping mark (5) is formed by SiGe, silica or silicon nitride.
4. overlapping mark as claimed in claim 1 (5) is characterized in that, each stave (56) is merged to be connected by 2 first separators (561,562) and forms.
5. overlapping mark as claimed in claim 4 (5); It is characterized in that; This first separator (561,562) has a width (S1), and this stave (56) has a width (X), and the width (X) of this stave (56) is less than two times of the width (S1) of this first separator (561,562).
6. overlapping mark as claimed in claim 1 (5) is characterized in that, each lateral direction element (58) is merged to be connected by 2 second separators (581,582) and forms.
7. overlapping mark as claimed in claim 6 (5); It is characterized in that; This second separator (581,582) has a width (S2), and this lateral direction element (58) has a width (Y), and the width (Y) of this lateral direction element (58) is less than two times of the width (S2) of this second separator (581,582).
8. overlapping mark as claimed in claim 1 (5) is characterized in that, this hole (60) is polygon or circle, or its combination.
9. an overlapping mark preparation method is characterized in that, comprises following steps:
Form a patterned layer (10) on a substrate; Wherein this patterned layer (10) comprises that at least one indexing unit forms zone (12); Each said indexing unit forms zone (10) and comprises two vertical recesses (16) and a plurality of lateral recess (18), and said a plurality of lateral recess (18) connect said a plurality of vertical recesses (16);
By the sidewall of said a plurality of vertical recesses (16) and said a plurality of lateral recess (18) marker material (22) of growing up, make this marker material (22) in said a plurality of vertical recesses (16) and said a plurality of lateral recess (18), merge linking; And
Remove this patterned layer (10).
10. overlapping mark preparation method as claimed in claim 9 is characterized in that, this patterned layer (10) is a photoresist layer.
11. overlapping mark preparation method as claimed in claim 10 is characterized in that, this patterned layer is that (10) utilize an etching solution to remove.
12. overlapping mark preparation method as claimed in claim 11 is characterized in that, this etching solution is an acetone.
13. overlapping mark preparation method as claimed in claim 9 is characterized in that this overlapping mark is formed by SiGe, silica or silicon nitride.
14. overlapping mark preparation method as claimed in claim 1; It is characterized in that; The step of this marker material (22) of growing up comprises by the sidewall of said a plurality of vertical recesses (16) first separator (561,562) of growing up, and by the sidewall of said a plurality of lateral recess (18) second separator (581,582) of growing up.
15. overlapping mark preparation method as claimed in claim 14; It is characterized in that; This first separator (561,562) has a width (S1); This vertical recess (16) has a width (X '), and the width (X ') of this vertical recess (16) is less than two times of the width (S1) of this first separator (561,562).
16. overlapping mark preparation method as claimed in claim 14; It is characterized in that; This second separator (581,582) has a width (S2); This lateral recess (18) has a width (Y '), and the width (Y ') of this lateral recess (18) is less than two times of the width (S2) of this second separator (581,582).
17. overlapping mark preparation method as claimed in claim 9 is characterized in that, each said indexing unit forms zone (10) and comprises a plurality of blocks (20), is arranged between said a plurality of vertical recesses (16) and the said a plurality of lateral recess (18) and the space.
18. overlapping mark preparation method as claimed in claim 17 is characterized in that, this block (20) is polygon or circle, or its combination.
19. overlapping mark preparation method as claimed in claim 9 is characterized in that, this marker material (22) forms with the low temperature chemical vapor deposition method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/116,585 | 2011-05-26 | ||
| US13/116,585 US20120299204A1 (en) | 2011-05-26 | 2011-05-26 | Overlay mark and method for fabricating the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102800652A true CN102800652A (en) | 2012-11-28 |
Family
ID=47199716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011102014151A Pending CN102800652A (en) | 2011-05-26 | 2011-07-19 | Overlay mark and method for fabricating the same |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20120299204A1 (en) |
| CN (1) | CN102800652A (en) |
| TW (1) | TW201248820A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149401A1 (en) * | 2014-04-01 | 2015-10-08 | 深圳市华星光电技术有限公司 | Method for designing and manufacturing alignment mark of tft lcd array |
| CN109817516A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Semiconductor device with overlapping pattern |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI730050B (en) * | 2017-02-15 | 2021-06-11 | 聯華電子股份有限公司 | Overlay mark and method for evaluating stability of semiconductor manufacturing process |
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| JP2004134473A (en) * | 2002-10-09 | 2004-04-30 | Nikon Corp | Mark for detecting position, position detector, position detecting method, aligner, and aligning method |
| TW591784B (en) * | 2003-06-25 | 2004-06-11 | Macronix Int Co Ltd | Overlay mark and method for making the same |
| CN1658071A (en) * | 2003-11-24 | 2005-08-24 | 三星电子株式会社 | Overlay mark for measuring and correcting alignment errors |
| JP2007324371A (en) * | 2006-06-01 | 2007-12-13 | Ebara Corp | Overlay mark for overlay inspection and mark for lens aberration investigation |
| CN101162368A (en) * | 2006-10-10 | 2008-04-16 | Asml荷兰有限公司 | Method, an alignment mark and use of a hard mask material |
| US20090134531A1 (en) * | 2007-11-26 | 2009-05-28 | Macronix International Co., Ltd. | Overlay mark and method for forming the same |
| US20100052191A1 (en) * | 2008-08-29 | 2010-03-04 | Qimonda Ag | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method |
| CN101957566A (en) * | 2009-07-14 | 2011-01-26 | 南亚科技股份有限公司 | Integrated alignment and overlay mark |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224057A (en) * | 2002-01-30 | 2003-08-08 | Hitachi Ltd | Method of manufacturing semiconductor device |
| JP5685811B2 (en) * | 2009-12-25 | 2015-03-18 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
-
2011
- 2011-05-26 US US13/116,585 patent/US20120299204A1/en not_active Abandoned
- 2011-06-30 TW TW100123003A patent/TW201248820A/en unknown
- 2011-07-19 CN CN2011102014151A patent/CN102800652A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134473A (en) * | 2002-10-09 | 2004-04-30 | Nikon Corp | Mark for detecting position, position detector, position detecting method, aligner, and aligning method |
| TW591784B (en) * | 2003-06-25 | 2004-06-11 | Macronix Int Co Ltd | Overlay mark and method for making the same |
| CN1658071A (en) * | 2003-11-24 | 2005-08-24 | 三星电子株式会社 | Overlay mark for measuring and correcting alignment errors |
| JP2007324371A (en) * | 2006-06-01 | 2007-12-13 | Ebara Corp | Overlay mark for overlay inspection and mark for lens aberration investigation |
| CN101162368A (en) * | 2006-10-10 | 2008-04-16 | Asml荷兰有限公司 | Method, an alignment mark and use of a hard mask material |
| US20090134531A1 (en) * | 2007-11-26 | 2009-05-28 | Macronix International Co., Ltd. | Overlay mark and method for forming the same |
| US20100052191A1 (en) * | 2008-08-29 | 2010-03-04 | Qimonda Ag | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method |
| CN101957566A (en) * | 2009-07-14 | 2011-01-26 | 南亚科技股份有限公司 | Integrated alignment and overlay mark |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149401A1 (en) * | 2014-04-01 | 2015-10-08 | 深圳市华星光电技术有限公司 | Method for designing and manufacturing alignment mark of tft lcd array |
| CN109817516A (en) * | 2017-11-21 | 2019-05-28 | 三星电子株式会社 | Semiconductor device with overlapping pattern |
| CN109817516B (en) * | 2017-11-21 | 2024-02-02 | 三星电子株式会社 | Semiconductor device with overlapped pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201248820A (en) | 2012-12-01 |
| US20120299204A1 (en) | 2012-11-29 |
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Application publication date: 20121128 |