CN102789762A - Driving circuit, array substrate and display device - Google Patents
Driving circuit, array substrate and display device Download PDFInfo
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- CN102789762A CN102789762A CN2012102793282A CN201210279328A CN102789762A CN 102789762 A CN102789762 A CN 102789762A CN 2012102793282 A CN2012102793282 A CN 2012102793282A CN 201210279328 A CN201210279328 A CN 201210279328A CN 102789762 A CN102789762 A CN 102789762A
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Abstract
The invention provides a driving circuit, an array substrate and a display device. The driving circuit comprises a time schedule controller and a plurality of grid drivers, wherein the time schedule controller is directly connected with a first grid driver through a time schedule control signal transmission line; in the grid drivers, the first grid driver is closest to the time schedule controller; and the time schedule controller is also directly connected with at least one second grid driver except the first grid driver in the grid drivers through the time schedule control signal transmission line. In the driving circuit, the time schedule controller is directly connected with the grid drivers through the time schedule control signal transmission line, and the time schedule control signals transmitted to the grid drivers by the time schedule controller are differently controlled, so that the delay problem of the control signals received by the grid drivers caused by too big impedance of panel glass of a liquid crystal array substrate is effectively avoided.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of driving circuit, array base palte and display device.
Background technology
Be illustrated in figure 1 as the structural representation that is used for the driving circuit of array base palte of the prior art; This driving circuit comprises: 101 and two gate drivers of time schedule controller (TCON) (Gate driver) (gate drivers 102a and gate drivers 102b); Wherein, time schedule controller 101 can be exported the control signal that STV signal (frame start signal), OE signal (output enable signal) and CPV signal (clock signal) etc. are used for control gate driver 102a and gate drivers 102b.
As can be seen from Figure 1; In the prior art; The signal transmssion line (103a, 103b, 103c, 103d) that is used to transmit STV signal, OE signal and CPV signal all is that the face glass that gets into array base palte is inner, gets into the gate drivers 102a near time schedule controller 101 then by time schedule controller 101 beginnings; Get into the glass substrate inside of array base palte again by gate drivers 102a, get into gate drivers 102b at last away from time schedule controller 101.That is to say that gate drivers 102a and gate drivers 102b are serially connected.Among Fig. 1, signal transmssion line 103a, 103b, 103c, 103d are respectively applied for transmission STV2, STV1, OE and CPV signal.
There is following problem in above-mentioned driving circuit: because gate drivers 102a is that the serial connection mode is connected with gate drivers 102b; Control signal need be passed through after the gate drivers 102a; Could get into and be positioned at gate drivers 102b; Thereby when the base plate glass impedance of array base palte is too big; The control signal that can cause gate drivers 102a and gate drivers 102b to receive produces and postpones, thereby makes the output waveform in proper order (G on) of gate drivers 102a and gate drivers 102b output produce unmatched problem.
Summary of the invention
In view of this; The present invention provides a kind of driving circuit, array base palte and display device; Can solve in the prior art because the base plate glass impedance of array base palte is too big; The control signal that causes the gate drivers of a plurality of series connection to receive produces and postpones, thereby causes the output waveform in proper order of different gate drivers outputs to produce unmatched problem.
For addressing the above problem; The present invention provides a kind of driving circuit; Comprise: time schedule controller and a plurality of gate drivers; Wherein, Said time schedule controller directly is connected through the timing control signal transmission line with the nearest first grid driver of the said time schedule controller of distance in said a plurality of gate drivers, said time schedule controller also with said a plurality of gate drivers at least one the second grid driver except that said first grid driver directly be connected through the timing control signal transmission line.
Preferably, said time schedule controller all directly is connected through the timing control signal transmission line with all second grid drivers except that said first grid driver in said a plurality of gate drivers.
Preferably, said time schedule controller comprises: corresponding with said timing control signal transmission line, be used for the working storage that the control timing control signal exports said timing control signal transmission line to.
Preferably, said driving circuit also comprises:
Be used for the frame start signal of said time schedule controller output is transferred to the frame start signal transmission line of said gate drivers.
Preferably, said frame start signal transmission line comprises:
The first frame start signal transmission line, said time schedule controller directly is connected through the said first frame start signal transmission line respectively with said second grid driver with said first grid driver.
Preferably, said frame start signal transmission line also comprises:
The second frame start signal transmission line, the said second frame start signal transmission line is connected with said time schedule controller, and successively said a plurality of gate drivers is connected in series.
Preferably, said frame start signal transmission line also comprises:
The 3rd frame start signal transmission line, an end of said the 3rd frame start signal transmission line is connected with said time schedule controller, the other end directly with said a plurality of gate drivers in the said time schedule controller of distance gate drivers farthest be connected.
Preferably, connect through said timing control signal transmission line respectively between the adjacent said gate drivers.
Preferably, said timing control signal transmission line comprises: be used to the timing control signal transmission line that transmits the timing control signal transmission line of OE signal and be used to transmit the CPV signal.
The present invention also provides a kind of array base palte, comprises above-mentioned driving circuit.
The present invention also provides a kind of display device, comprises above-mentioned array base palte.
The present invention has following beneficial effect:
Time schedule controller directly is connected through the timing control signal transmission line with gate drivers; Can the timing control signal that time schedule controller is transferred to gate drivers be carried out differential control; Thereby can effectively avoid because of the substrate impedance of array base palte is too big, the control signal that causes gate drivers to receive produces the problem that postpones.
Description of drawings
Fig. 1 is the structural representation of driving circuit of the prior art;
Fig. 2 is the structural representation of the driving circuit of embodiments of the invention one;
Fig. 3 is the structural representation of the driving circuit of embodiments of the invention two;
Fig. 4 is the structural representation of the driving circuit of embodiments of the invention three;
Fig. 5 is the structural representation of the driving circuit of embodiments of the invention four;
Fig. 6 is the structural representation of the driving circuit of embodiments of the invention five;
Fig. 7 is the structural representation of the driving circuit of embodiments of the invention six.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.
Embodiment one:
Be illustrated in figure 2 as the structural representation of the driving circuit of embodiments of the invention one; This driving circuit is applied to array basal plate; This driving circuit comprises: time schedule controller 201 and two gate drivers (gate drivers 202a and gate drivers 202b); Said time schedule controller 201 with near directly being connected with timing control signal transmission line 203b through timing control signal transmission line 203a between the gate drivers 202a of said time schedule controller 201; Said time schedule controller 201 with away from directly being connected with timing control signal transmission line 203d through timing control signal transmission line 203c between the gate drivers 202b of said time schedule controller 201, promptly directly be connected through the timing control signal transmission line respectively between time schedule controller 201 and two gate drivers.Among this embodiment, gate drivers 202a is the first grid driver, and gate drivers 202b is the second grid driver
As can be seen from Figure 2, the timing control signal transmission line that is connected with gate drivers all is that the substrate that gets into array base palte is inner, is directly connected to corresponding said gate drivers then by said time schedule controller 201 beginnings.
In the present embodiment; Be to comprise that with driving circuit two gate drivers are that example describes; Certainly, in other embodiments of the invention, driving circuit also can comprise more a plurality of gate drivers; When comprising in the driving circuit, can directly be connected through the timing control signal transmission line respectively equally between the time schedule controller in the driving circuit and these a plurality of gate drivers more than two gate drivers.
The driving circuit that provides through the foregoing description; Time schedule controller all directly is connected through the timing control signal transmission line with all gate drivers; But not all gate drivers are together in series; Thereby can the timing control signal that time schedule controller is transferred to each gate drivers be carried out differential control; Effectively avoided because of the glass substrate impedance of array base palte is too big, caused the control signal that gate drivers receives under the serial connection mode to produce delay, and then caused the output waveform in proper order of different gate drivers outputs to produce unmatched problem.Certainly, array base palte can be selected the substrate of unlike material as required for use, like glass substrate, quartz base plate or plastics etc., also can adopt the driving circuit of present embodiment.
Embodiment two:
Be illustrated in figure 3 as the structural representation of the driving circuit of embodiments of the invention two; This driving circuit is applied to array basal plate; This driving circuit comprises: time schedule controller 201 and three gate drivers (gate drivers 202a, gate drivers 202b and gate drivers 202c); Directly be connected with timing control signal transmission line 203b through timing control signal transmission line 203a between said time schedule controller 201 and the gate drivers 202a (being the first grid driver) near said time schedule controller 201; Said time schedule controller 201 with directly be connected with timing control signal transmission line 203d through timing control signal transmission line 203c between the said time schedule controller 201 gate drivers 202b farthest; The gate drivers 202c that mediates connects through timing control signal transmission line 203e and timing control signal transmission line 203f with said gate drivers 202a, and gate drivers 202b and gate drivers 202c are the second grid driver.
In the present embodiment; With time schedule controller 201 with all directly be connected apart from the nearest gate drivers 202a of this time schedule controller 201 and apart from this time schedule controller gate drivers 202b farthest through the timing control signal transmission line; But not all gate drivers are together in series; Thereby can the timing control signal that time schedule controller is transferred to gate drivers 202a and gate drivers 202b be carried out differential control, the control signal of having avoided receiving apart from time schedule controller 201 gate drivers 202b farthest produces and postpones.
In the present embodiment, also can be together in series between gate drivers 202b and the gate drivers 202c through one group of timing control signal transmission line.When gate drivers 202b both direct-connected with time schedule controller 201; When connecting with adjacent gate drivers again; Gate drivers 202b might receive the identical timing control signal of two set types simultaneously; When gate drivers 202b received the identical timing control signal of two set types, one group of timing control signal in can selecting these two groups according to concrete needs used.
In the foregoing description; When driving circuit has a plurality of gate drivers; Time schedule controller also with apart from this time schedule controller gate drivers farthest directly is connected through the timing control signal transmission line except with the first grid driver nearest apart from this time schedule controller directly is connected through the timing control signal transmission line.In addition; In other embodiments of the invention; When driving circuit has a plurality of gate drivers; Time schedule controller can also directly be connected through the timing control signal transmission line with any one or more second grid drivers except that this first grid driver in these a plurality of gate drivers except with the gate drivers nearest apart from this time schedule controller directly is connected through the timing control signal transmission line.
Being used in the foregoing description connects time schedule controller and gate drivers; The one group of timing control signal transmission line that perhaps is used to connect adjacent gate drivers includes two timing control signal transmission lines: one is the timing control signal transmission line that is used to transmit the OE signal, and another is the timing control signal transmission line that is used to transmit the CPV signal.
Certainly; In other embodiments of the invention; Be used to connect time schedule controller and gate drivers, the one group of timing control signal transmission line that perhaps is used for connecting adjacent gate drivers also can comprise one or more timing control signal transmission lines (more than two).
Time schedule controller is except to gate drivers output timing control signal; Also be used for to gate drivers output frame start signal (STV signal); Thereby, in the present embodiment, also need be connected with the STV signal transmssion line that is used to transmit the STV signal between time schedule controller and the gate drivers.The STV signal transmssion line can adopt set-up mode of the prior art, and the set-up mode of STV signal transmssion line also can be identical with above-mentioned clock signal transmission line.
Embodiment three:
The set-up mode of STV signal transmssion line can be identical with above-mentioned clock signal transmission line.
Be illustrated in figure 4 as the structural representation of the driving circuit of the embodiment of the invention three; The difference of the driving circuit among driving circuit in the present embodiment and the embodiment shown in Figure 2 is; Also comprise: the first frame start signal line; The said first frame start signal line comprises STV signal transmssion line 204a and STV signal transmssion line 204b; Between time schedule controller 201 and the gate drivers 202a except directly being connected through timing control signal line 203a, 203b; Also directly connect, except directly being connected, also directly connect between time schedule controller 201 and the gate drivers 202b through STV signal transmssion line 204b through timing control signal line 203c, 203d through STV signal transmssion line 204a.
Among the embodiment three; Be to comprise that with driving circuit two gate drivers are that example describes; Certainly, in other embodiments of the invention, driving circuit can also comprise the gate drivers more than two; When comprising in the driving circuit, all can directly be connected between time schedule controller and a plurality of gate drivers through the first frame start signal transmission line more than two gate drivers.
Embodiment four:
The STV signal transmssion line also can adopt set-up mode of the prior art.
Be illustrated in figure 5 as the structural representation of the driving circuit of the embodiment of the invention four; The difference of the driving circuit among driving circuit in the present embodiment and the embodiment shown in Figure 2 is; Also comprise: STV signal transmssion line 205; Said STV signal transmssion line 205 is connected with said time schedule controller 201, and successively gate drivers 202a and gate drivers 202b is connected in series.For the ease of difference, among this embodiment, the STV signal transmssion line can be called the second frame start signal transmission line.
Among the embodiment four; Be to comprise that with driving circuit two gate drivers are that example describes; Certainly, in other embodiments of the invention, driving circuit can also comprise the gate drivers more than two; When comprising in the driving circuit, can be connected in series through the second frame start signal transmission line between time schedule controller and a plurality of gate drivers more than two gate drivers.
Embodiment five:
When the STV signal transmssion line adopts method to set up shown in Figure 5, because at first being transferred to, the STV signal demand is positioned at the gate drivers 202a of below, thereby only can the corresponding grid line of gate drivers 202a of below begins scanning from being positioned at.And in some cases, also possibly begin scanning from the corresponding grid line of gate drivers 202b that is positioned at the top, thereby; For satisfying this demand; As shown in Figure 6, on the basis of embodiment shown in Figure 5, said driving circuit can also comprise: STV signal transmssion line 206; One end of said STV signal transmssion line 206 is connected with said time schedule controller 201, and the other end directly is connected with the said time schedule controller 201 of distance gate drivers 202b farthest.For the ease of difference, among this embodiment, the STV signal transmssion line can be called the 3rd frame start signal transmission line.
Embodiment six:
The delay of the control signal that receives when a plurality of gate drivers hour also can keep design of the prior art, with being connected in series through the timing control signal transmission line between a plurality of gate drivers in the driving circuit.
Be illustrated in figure 7 as the structural representation of the driving circuit of embodiments of the invention six; Driving circuit in the present embodiment is compared difference and is with the driving circuit of embodiment shown in Figure 6 five, be connected with timing control signal transmission line 203h through timing control signal transmission line 203g respectively between adjacent gate drivers 202a and the gate drivers 202b.
When timing control signal transmission line between gate drivers 202a and the gate drivers 202b connects; Gate drivers 202b might receive the identical timing control signal of two set types simultaneously; Wherein, One group of timing control signal is transmitted by timing control signal transmission line 203c, 203d direct-connected between time schedule controller 201 and the gate drivers 202b; Another group timing control signal is transferred to by time schedule controller 201 and is positioned at the gate drivers 202a of below, and then the gate drivers 202a of below transmits through timing control signal transmission line 203g, 203h by being positioned at.When gate drivers 202b received the identical timing control signal of two set types, one group of timing control signal in can selecting these two groups according to concrete needs used.
Time schedule controller among above-mentioned each embodiment all can comprise: one is corresponding with said timing control signal transmission line, is used for the working storage that the control timing control signal exports said timing control signal transmission line to.
Certainly, among other embodiment of the present invention, said time schedule controller is not got rid of other modes of employing yet the output of timing control signal is controlled.
The embodiment of the invention also provides a kind of array base palte, and this array base palte comprises the driving circuit among above-mentioned arbitrary embodiment.Array base palte can be selected the substrate of unlike material as required for use, like glass substrate, quartz base plate or plastics etc.
The embodiment of the invention provides a kind of display device, has the array base palte of the described arbitrary characteristics of the foregoing description.This display device can be liquid crystal indicator, comprises the array base palte that color membrane substrates and the foregoing description proposed of opposing parallel setting, and is filled in the liquid crystal between said color membrane substrates and the array base palte; This display device also can be the OLED display device, comprises the array base palte that the foregoing description proposes, and luminous organic material and the encapsulation cover plate of vapor deposition on this array base palte.
The liquid crystal indicator that the embodiment of the invention provides, said liquid crystal indicator can not limit for product or the present invention of portion that LCD, LCD TV, DPF, mobile phone, panel computer etc. have a Presentation Function.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (11)
1. driving circuit; Comprise: time schedule controller and a plurality of gate drivers; Wherein, Said time schedule controller directly is connected through the timing control signal transmission line with the nearest first grid driver of the said time schedule controller of distance in said a plurality of gate drivers, it is characterized in that, said time schedule controller also with said a plurality of gate drivers at least one the second grid driver except that said first grid driver directly be connected through the timing control signal transmission line.
2. driving circuit as claimed in claim 1 is characterized in that, said time schedule controller all directly is connected through the timing control signal transmission line with all second grid drivers except that said first grid driver in said a plurality of gate drivers.
3. according to claim 1 or claim 2 driving circuit is characterized in that said time schedule controller comprises: corresponding with said timing control signal transmission line, be used for the working storage that the control timing control signal exports said timing control signal transmission line to.
4. according to claim 1 or claim 2 driving circuit is characterized in that, also comprises:
Be used for the frame start signal of said time schedule controller output is transferred to the frame start signal transmission line of said gate drivers.
5. driving circuit as claimed in claim 4 is characterized in that, said frame start signal transmission line comprises:
The first frame start signal transmission line, said time schedule controller directly is connected through the said first frame start signal transmission line respectively with said second grid driver with said first grid driver.
6. driving circuit as claimed in claim 4 is characterized in that, said frame start signal transmission line also comprises:
The second frame start signal transmission line, the said second frame start signal transmission line is connected with said time schedule controller, and successively said a plurality of gate drivers is connected in series.
7. driving circuit as claimed in claim 6 is characterized in that, said frame start signal transmission line also comprises:
The 3rd frame start signal transmission line, an end of said the 3rd frame start signal transmission line is connected with said time schedule controller, the other end directly with said a plurality of gate drivers in the said time schedule controller of distance gate drivers farthest be connected.
8. according to claim 1 or claim 2 driving circuit is characterized in that, connects through said timing control signal transmission line respectively between the adjacent said gate drivers.
9. according to claim 1 or claim 2 driving circuit is characterized in that said timing control signal transmission line comprises: be used to the timing control signal transmission line that transmits the timing control signal transmission line of OE signal and be used to transmit the CPV signal.
10. an array base palte is characterized in that, comprises each described driving circuit of claim 1-9.
11. a display device is characterized in that, comprises the described array base palte of claim 10.
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| CN201210279328.2A CN102789762B (en) | 2012-08-07 | 2012-08-07 | Driving circuit, array base palte and display device |
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| CN201210279328.2A CN102789762B (en) | 2012-08-07 | 2012-08-07 | Driving circuit, array base palte and display device |
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| CN103531169A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Display drive circuit, drive method thereof as well as display device |
| CN110942724A (en) * | 2019-12-19 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | Folding display panel and display device |
| CN112614464A (en) * | 2019-10-04 | 2021-04-06 | 晶门科技（中国）有限公司 | Display panel with distributed driver network |
| CN113936603A (en) * | 2021-10-28 | 2022-01-14 | 京东方科技集团股份有限公司 | Display device, data transmission method, apparatus, and storage medium |
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