CN102789755A - Display panel - Google Patents

Abstract

The invention discloses a display panel, which comprises a display area, a non-display area and at least one compensation module. The display area has a plurality of pixels. The non-display area is disposed outside the display area and includes a near-end sub-area. The near-end sub-region has a plurality of signal lines. The signal lines extend toward the display region. A driving circuit charges and discharges the pixels through the signal lines in the display region and the near-end sub-region. The compensation module is used for compensating the influence caused by the signal lines with different lengths. When the non-display area further comprises a reverse terminal area, the compensation module is arranged in at least one of the display area and the reverse terminal area. When both ends of the signal line extend to the counter terminal area, the compensation module is disposed in the display area.

Description

display panel

technical field

The present invention relates to a display panel, in particular to a display panel capable of compensating the influence caused by signal lines of different lengths.

Background technique

In general, flat panel displays can be classified into non-self-luminous displays and self-luminous displays. Liquid crystal display (LCD) is a kind of non-self-luminous display. The self-luminous display includes a plasma display panel (PDP), a field emission display (FED), an electroluminescent (EL) display, and an organic light emitting diode display (OLED).

Whether it is a non-self-luminous display or a self-luminous display, the display panel can generally be divided into a display area and a non-display area. As shown in the figure, the non-display area 110 has at least one driving circuit 120 . The driving circuit 120 can be a driving IC. The driving circuit 120 charges and discharges the pixels P ₁₁ -P _mn in the display area 140 through the signal line module 130 . As shown in the figure, the signal line module 130 is coupled to the driving circuit 120 and the pixels P ₁₁ -P _mn in a fan-out manner.

However, the fan-out structure will cause the signal lines in the signal line module 130 to have different lengths, thus resulting in different charging and discharging speeds of the pixels. For example, the length of the signal line 131 is greater than the length of the signal line 133 . Therefore, when the driving circuit 120 provides the same signal to the signal lines 131 and 133, the charging/discharging speed of the pixels P ₁₁ -P _1n in the first row (vertical direction) may be slower than that of the pixels in the third row (vertical direction). The charging/discharging speeds of P ₃₁ ˜P _3n cause the luminance displayed by the pixels P ₁₁ ˜P _1n to be different from the luminance presented by the pixels P ₃₁ ˜P _3n .

Contents of the invention

The invention provides a display panel, which includes a display area, a non-display area and at least one compensation module. The display area has a plurality of pixels. The non-display area is set outside the display area and includes a terminal-near area. The near-terminal area has a plurality of signal lines. The signal line extends toward the display area. A driving circuit performs charging and discharging operations on the pixels through the signal lines in the display area and the near-terminal area. The compensation module is coupled to a first signal line among the signal lines, and is used for compensating the influence caused by the first signal line on the charging and discharging operation. When the non-display area further includes an anti-terminal area, the compensation module is disposed in at least one of the display area and the anti-terminal area. When both ends of the signal line extend to the anti-terminal area, the compensation module is arranged in the display area.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a known display panel.

2 and 4 are possible embodiments of the display panel of the present invention.

3A-3D are schematic diagrams of a possible structure of the compensation module of the present invention.

Description of main component symbols:

100, 200, 400: display panel;

110: non-display area;

120, 211, 411: driving circuit;

130: signal line module;

131, 133, A～D: signal lines;

140, 250, 450: display area;

210, 410: near the terminal area;

231～233, 431～433: anti-terminal area;

261～272, 461～463: compensation module;

310 _A ~ 310 _C , 330 _A : extended area;

P ₁₁ ～P _mn , P _A1 ～P _D6 : pixels;

C _A1 ～C _C5 , C _A ～C _C : capacitors;

SE, DE _A ~ DE _D , PE, CE _A : electrodes.

Detailed ways

FIG. 2 is a possible embodiment of the display panel of the present invention. As shown in the figure, the display panel 200 has a display area (Active Area; AA) 250, a non-display area and at least one compensation module (such as 261-272). The present invention does not limit the type of the display panel 200 . In a possible embodiment, the display panel 200 is a liquid crystal display (LCD) panel.

The display area 250 is used to present images and has a plurality of signal lines and a plurality of pixels. For convenience of description, FIG. 2 only shows the signal lines A˜D and the pixels P _A1 ˜P _D6 . Each pixel is coupled to a corresponding signal line. For example, the pixels P _A1 -P _A6 are coupled to the signal line A. Referring to FIG. Since the circuit structures in the pixels P _{A1 -PD6} are well known by those skilled in the art, details are not repeated here.

In this embodiment, the signal lines A˜D are made of conductive material, such as metal. In addition, the present invention does not limit the types of signal lines. In a possible embodiment, the signal lines AD are all scan electrodes for transmitting scan signals. In other possible embodiments, the signal lines AD may be data electrodes or common electrodes for transmitting data signals or common voltages.

Areas outside the display area 250 are called non-display areas. In this embodiment, the non-display area includes the near-terminal area 210 and the anti-terminal areas 231 - 233 . The near-terminal area 210 has a plurality of signal lines, and for convenience of illustration, only four signal lines A-D are shown in FIG. 2 .

The signal lines AD extend to the display area 250 for transmitting the driving signal provided by a driving circuit to the pixels P _{A1 -PD6} in the display area 250 . In this embodiment, the area with the signal line segment that transmits the driving signal from the driver to the display area is called the near-terminal area (such as 210) of the signal line, and the area without such a signal line segment is called the signal line segment. The anti-terminal area of the line (such as 231~233).

The driving circuit 211 in the near-terminal area 210 performs a charging and discharging operation on the pixels P _{A1 -PD6} through the signal lines A-D in the near-terminal area 210 and the display area 250 . In this embodiment, a chip-on-glass (COG) technology is used to integrate the driving circuit 211 to provide driving signals to the signal lines A-D for charging and discharging the pixels P _A1 -P _A6 . In another possible embodiment, a tape automatic bonding (TAB) and a chip on film (COF) bonding technology (Chip On Film; COF) can be used to integrate the driving circuit 211 to provide driving signals to the signal lines. A~D.

The invention does not limit the quantity and type of driving circuits. In a possible embodiment, when the signal lines AD are scan electrodes, the driving circuit 211 is a scan driver, which is used to provide a plurality of scan signals to the pixels P _A1 -P _D6 to start to perform charging or discharging action. In another possible embodiment, when the signal lines AD are data electrodes, the driving circuit 211 is a data driver for providing multiple data signals to the pixels P _A1 -P _D6 , so that the pixels P _A1 The capacitor in ~P _D6 stores the corresponding charge.

If the signal line segments in a non-display area (such as area 210) (such as the line segments of signal lines A to D located in area 210) are used to transmit the signal of the driving circuit to the display area (such as 250), then this non-display The region is called the near-terminal region of the signal line. If the non-display area (for example, areas 231-233) does not contain the signal line segment that transmits the driving signal to the display area, it is collectively referred to as the anti-terminal area of the signal line.

For example, assuming that a scan driver only provides scan signals to the display area from the right side of the display area (such as area 231), then in terms of scan electrodes, the non-display area on the right side of the display area is the vicinity of the scan electrodes. The terminal area, regardless of whether the scan electrode extends from the display area to the left non-display area (such as area 233), the left non-display area is the opposite terminal area of the scan electrode. Assuming a structure in which scan signals are provided to the display area from both sides of the display area, the non-display areas on both sides are near terminal areas of the scan electrodes.

Similarly, assume that a data driver transmits data signals to the display area only from the upper side of the display area (such as area 232), and a scan driver transmits scan signals to the display area only from the right side of the display area (such as area 231). , the non-display area on the upper side of the display is the near-terminal area of the data electrode and the opposite terminal area of the scan electrode. Similarly, the non-display area on the right side of the display is the near-terminal area of the scan electrode and the opposite terminal area of the data electrode.

In this embodiment, the signal lines AD are arranged in a fan-out manner to transmit the signals provided by the driving circuit 211 to the pixels P _A1 -P _D6 , therefore, the lengths of the signal lines AD are not the same ( In particular, the lengths of the line segments located in the near-terminal region 210 are not the same). Since the lengths of the signal lines AD will affect the charging and discharging speeds of the pixels P _{A1 -PD6} , in order to equalize the charging and discharging speeds of the pixels on each signal line, the compensation modules 261 - 272 are coupled to the corresponding signal lines ( Such as A-D), which are used to compensate the influence caused by the different lengths of the signal lines A-D on the charging and discharging operation of the pixels.

In this embodiment, the signal line D has no compensation module, but the signal line A has compensation modules 261 - 266 , the signal line B has compensation modules 267 - 269 , and the signal line C has compensation modules 270 - 272 . Since the lengths of the signal lines A to D are different, different compensation levels need to be provided for different signal lines. For example, the length of the signal line A is shorter than that of the signal line B, so the total compensation degree of the compensation modules 261 - 266 is greater than the total compensation degree of the compensation modules 267 - 269 .

The present invention does not limit the number of compensation modules on each signal line. In a possible embodiment, the number of compensation modules depends on the length of the corresponding signal lines and the compensation capability of the compensation modules. For example, when the compensation capability of each compensation module is the same, the shorter the signal line, the more compensation modules are required, or in the shorter signal line, a compensation module with a larger compensation capability is set, and in In a longer signal line, a compensation module with a smaller compensation capability is provided.

The present invention does not limit the arrangement of the compensation module. In a possible embodiment, each pixel on the same signal line is configured with a compensation module. For example, the pixels P- _A1 -P _A6 on the signal line A are all configured with a compensation module (eg, 261 - 266 ). In another possible embodiment, a compensation module may be configured every N pixels, as shown by the signal lines B and C. Taking the signal line B as an example, a compensation module is configured every other pixel. In other embodiments, a compensation module is provided every fixed distance.

In this embodiment, although the number of compensation modules of the signal lines B and C is the same (both have 3 compensation modules), their compensation capabilities are different. For example, since the length of the signal line B is shorter than the length of the signal line C, the compensation capabilities of the compensation modules 267-269 are greater than the compensation capabilities of the compensation modules 270-272, so that the different lengths of the signal lines B and C can be equalized. The impact (charge and discharge speed).

In addition, the compensation capabilities of the compensation modules on the same signal line may be all different, all the same, or partially the same. In a possible embodiment, the compensation capabilities of the compensation modules on the same signal line may decrease or increase gradually. In another possible embodiment, the closer the compensation module is to the center of the signal line, the higher the compensation capability is.

In this embodiment, the number of compensation modules of the signal lines B and C is the same, but different from the number of compensation modules coupled to the signal line A. In other embodiments, the numbers of the compensation modules of different signal lines may be all the same, all different, or some of them are the same while others are different. As long as the number of compensation modules and the compensation capability of the compensation modules are properly adjusted, the influence caused by the signal lines A to D of different lengths can be compensated.

The present invention does not limit the structures of the compensation modules 261-272. In this embodiment, the compensation modules 261 - 272 are capacitors C _{A1 -CC6} respectively. In a possible embodiment, the capacitors C _A1 -C _C6 may all be Metal-Insulator-Metal (MIM) structures or cascade MIM structures. In other possible embodiments, some capacitors of the capacitors C _A1 -C _C6 are MIM structures, while other capacitors are series-connected MIM structures.

As long as the area of the metal structure of each capacitor is properly controlled, the capacitance of each capacitor can be properly controlled. In this embodiment, the metal structure of each capacitor receives a voltage potential. The present invention does not limit the magnitude of the voltage potential, as long as the potential does not affect the image quality, it can be supplied to the capacitor.

FIG. 3A is a schematic diagram of a possible structure of the compensation module of the present invention. For convenience of description, FIG. 3A only shows a schematic layout of the compensation module and part of the display area. In this embodiment, the signal lines AD are respectively the data electrodes DE _A -D _D . The pixels P _{A1 -PD1} are not only coupled to the data electrodes DE _A -D _D respectively, but also coupled to the scan electrode SE. Since the structures of the pixels P _{A1 -PD1} are well known by those skilled in the art, details are not repeated here.

As shown in FIG. 3A , the scan electrodes SE extend toward a direction D1 , and the data electrodes DE extend toward a direction D2 , wherein the direction D1 is perpendicular to the direction D2 . In addition to extending toward the direction D1, the scan electrode SE further has an extension region 310 _A - 310 _C .

In order to compensate the influence caused by the different lengths of the data electrodes DE _A ˜ D _D , the extension regions 310 _A ˜ 310 _C extend in the direction D2 and overlap the data electrodes DE _A ˜ D _D . Capacitors C A1 , C _B1 and C _C1 can be defined by overlapping regions of the extension regions 310 _A ˜ 310 _C and the data electrodes DE _{A ˜} DE _C .

By controlling the overlapping areas of the extension regions _310A - _310C and the data electrodes _DEA - _DEC , the capacitances of the capacitors C _A1 , C _B1 and C _C1 can be controlled, thereby adjusting the compensation degree. For example, the overlapping area between the extension area 310 _A and the data electrode DE _A is the largest, and the overlapping area between the extension area 310 _C and the data electrode _DEC is the smallest, so the capacitance of the capacitor C _A1 is greater than that of the capacitor C _C1 . Therefore, the compensation capability of the capacitor C _A1 is greater than that of the capacitor C _C1 .

In addition, the present invention does not limit the shapes of the extension regions _310A - _310C , and the design principle is based on the aperture ratio (Aperture Ratio) that does not damage the display region. In this embodiment, the extension regions _310A - _310C have the same shape and are elongated. In other embodiments, the extension regions _310A - _310C have different shapes, and may be in any shape.

Furthermore, the present invention does not limit the types of electrodes constituting the capacitors C _A1 , C _B1 and C _C1 . In order to compensate the data electrodes DE _A ˜ _DEC , in this embodiment, the capacitors C _A1 , C _B1 and _{C C1} are formed by the data electrodes DE _A ˜ DEC and the scan electrode SE. In other possible embodiments, the capacitors C _A1 , C _B1 and C _C1 may be formed by the data electrodes DE _A ˜ _DEC and a compensation electrode, wherein the compensation electrode may be a common electrode or an additional electrode.

In a possible embodiment, the compensation capacitor on the same signal line can be composed of different electrode layers. For example, the capacitor C _A1 in Figure 3A is composed of the data electrode DE _A and the scanning electrode extension region 310 _A , but the same Another capacitor (such as C _A2 ) for compensating the data electrode DE _A may be formed by a common electrode (not shown) and the data electrode DE _A ; and another capacitor (such as C _A3 ) for compensating the data electrode DE _A is also It may be composed of an additional electrode and data electrode DE _A.

In a possible embodiment, the additional electrode and the scan electrode SE are formed by the same process, and the additional electrode and the scan electrode SE have the same material. In another possible embodiment, the additional electrode is formed by the same yellowing process as the pixel electrodes P _{A1 -PD1} , and has the same material as the pixel electrodes P _{A1 -PD1} .

The present invention does not limit the voltage potential of the additional electrode. The additional electrode may be electrically connected to the scan electrode SE, or receive a common voltage (Vcom), a ground voltage (GND) and other possible voltages. As long as the sizes of the capacitors C _A1 , C _B1 and C _C1 are properly designed, the compensation effect can be achieved.

In other embodiments, if it is desired to compensate the influence caused by the different lengths of the scan electrodes in the display area, the capacitor can be formed by the scan electrodes and a compensation electrode. The invention does not limit the type of the compensation electrode. In a possible embodiment, other electrodes (such as data electrodes or common electrodes) existing in the display area, or an additional conductive layer can be used to form the compensation capacitor.

Likewise, if it is desired to compensate the influence caused by the different lengths of the common electrodes, the compensation capacitor can be composed of a common electrode and a compensation electrode (such as a scan electrode, a data electrode or an additional electrode).

Although the capacitors C _A1 , C _B1 and C _C1 are disposed in the display area 250 , the degree of compensation can be controlled by adjusting the size of the overlapping area. Furthermore, the design of the capacitor can avoid the opening area (for example, it is disposed under the black matrix layer of the panel), so it does not affect the aperture ratio of the display panel. The capacitors C _A1 , C _B1 and C _C1 are formed by the original electrodes (such as the data electrodes, the source electrodes and the common electrodes), so the utilization rate of the electrodes can be improved without increasing the production cost.

FIG. 3B is a schematic diagram of another possible structure of the compensation module of the present invention. For convenience of illustration, FIG. 3B only shows the structure of capacitor C _A1 . In FIG. 3A, the capacitor C _A1 is formed by the extension region 310 _A of the scan electrode SE and the data electrode DE _A. However, in FIG. 3B, the capacitor C _A1 is formed by an extension region 330 _A of the data electrode DE _A and the scan electrode SE. In other embodiments, the extension region 330 _A of the data electrode DE _A can also be used to form a corresponding compensation device (such as a capacitor) with other compensation electrodes (such as a common electrode or an additional electrode).

FIG. 3C is a schematic diagram of another possible structure of the compensation module of the present invention. In this embodiment, both the scan electrode SE and the data electrode DE _A have an extension area for defining a capacitor. As shown in FIG. 3C , the scan electrode SE has an extension region 310 _A , and the data electrode DE _A has an extension region 330 _A . Capacitor _CA1 is formed where extension _310A overlaps extension _330A .

In this embodiment, the extension region _310A and the extension region _330A have the same shape and area, but this is not intended to limit the present invention. In other embodiments, the shape of the extension region _310A may be different from that of the extension region _330A , or the area of the extension region _310A may be different from that of the extension region _330A .

FIG. 3D is a schematic diagram of another possible structure of the compensation module of the present invention. In this embodiment, the capacitor C _A1 is a serial MIM structure. As shown in the figure, the capacitor C _A1 is composed of the extension region 310 _A of the scan electrode SE, the data electrode DE _A and the compensation electrode CE _A.

In this embodiment, the capacitor C _A1 is located in the display area. In another possible embodiment, the capacitor C _A1 may be located in the non-display area, such as in the near terminal area or in the opposite terminal area. In other embodiments, part of the capacitor C _A1 is located in the display area, while the other part is located in the non-display area.

For example, the overlapping area of the extension area _310A and the data electrode DE _A (or the data electrode DE _A and the compensation electrode CE _A ) is located in the display area, and the data electrode DE _A and the compensation electrode CE _A (or the extension area The overlapping area of 310 _A and the data electrode DE _A ) is located in the non-display area. In other embodiments, the partial overlapping area between the extension region _310A and the data electrode DE _A (or the data electrode DE _A and the compensation electrode CE _A ) is located in the display region, and the extension region _310A and the data electrode DE _A (or The other overlapping area of the data electrode DE _A and the compensation electrode CE _A is located in the non-display area.

In addition, the present invention does not limit the overlapping regions of the extension region 310 _A and the data electrode DE _A , and the data electrode DE _A and the compensation electrode CE _A. In a possible embodiment, the area of the overlapping region of the extension region 310 _A and the data electrode DE _A may be equal to, smaller than or larger than the area of the overlapping region of the data electrode DE _A and the compensation electrode CE _A.

In order to control the voltage potential of the compensation electrode CE _A , in this embodiment, the compensation electrode CE _A has a contact hole for electrically connecting the scan electrode SE. By connecting the MIM (metal insulator metal) structure in series, the capacitance of the capacitor C _A1 can be increased in a limited space, thereby increasing the compensation capability.

In a possible embodiment, materials of the compensation electrode CE _A and the pixel electrode PE are transparent conductive oxide (Transparent Conducting Oxide; TCO). Therefore, the compensation electrode CE _A and the pixel electrode PE can be formed by the same photomask process without adding additional process steps.

In FIG. 3D , the capacitor C _A1 is formed by the extension region 310 _A of the scan electrode SE, the data electrode DE _A and the compensation electrode CE _A , but it is not intended to limit the present invention. In other possible embodiments, the capacitor C _A1 is composed of a first conductive layer, a second conductive layer and a third conductive layer, and the three conductive layers are separated from each other by an insulating layer, wherein the second conductive layer It is the electrode to be compensated by the capacitor C _A1 , and the first and third conductive layers essentially function as compensation electrodes, and are respectively located on the first side and the second side of the second conductive layer. For example, in FIG. 3D, the data electrode DE _A and the compensation electrode CE _A are located on the first side and the second side (upper and lower sides) of the scan electrode SE respectively and are used to compensate the scan electrode SE, wherein the compensation electrode CE _A , the data electrode SE The electrode DE _A and the scanning electrode SE are separated by an insulating layer, and the data electrode DE _A and the compensation electrode CE _A are electrically connected through a connection hole, so as to improve the charging time caused by the uneven length of the scanning electrode near the terminal area. average problem.

For example, if the capacitor C _A1 intends to compensate the influence caused by the different lengths of the data electrodes, the second conductive layer is the data electrodes. Similarly, if the capacitor C _A1 is to compensate the influence caused by different lengths of the scanning electrodes or the common electrodes, the second conductive layer is the scanning electrodes or the common electrodes.

In a possible embodiment, both the first and the third conductive layers may be additionally added, or electrodes that do not need to be compensated in the display area. For example, if the data electrodes are to be compensated, the first or third conductive layer can be an electrode that does not need to be compensated in the display area (such as a scan electrode or a common electrode), or an additional electrode added.

If the existing electrodes in the display area are used as compensation electrodes, the usage of the electrodes can be increased. In addition, if the additional electrodes are formed through the existing process, the compensation effect can be achieved without increasing the steps of the process. For example, while forming the scan electrode, the data electrode, the common electrode, and the pixel electrode, an additional electrode can be formed to compensate for one or more corresponding electrodes.

In a possible embodiment, one of the first and third conductive layers may be formed by the same process as the pixel electrode. Furthermore, the material of one of the first and third conductive layers may be the same as that of the pixel electrode. In other embodiments, the first and third conductive layers may be electrically connected to the same voltage source, such as a common voltage (Vcom) or a ground voltage (GND), or the first to third conductive layers may not be electrically connected to each other. connected, each of which receives a corresponding voltage.

Likewise, the capacitors formed by the first to third conductive layers can be disposed in the display area or the non-display area, such as in the near-terminal area or in the opposite-terminal area. In addition, part of the electrode of at least one of the first to third conductive layers is located in the anti-terminal region. For example, the overlapping area of the first and second conductive layers may be located in the display area, while the overlapping area of the second and third conductive layers is located in the non-display area.

FIG. 4 is another possible embodiment of the display panel of the present invention. Figure 4 is similar to Figure 2, the difference is that the compensation modules 261-272 in Figure 2 are set in the display area 250, and the compensation modules 461-463 in Figure 4 are set in the opposite terminal area 432 of the non-display area , and connect the ends of the corresponding signal lines A~C.

In this embodiment, the compensation modules 461 - 463 are respectively capacitors _CA - _CC , one end of which is coupled to the signal lines A - C respectively, and the other end receives a voltage potential V _CM . In a possible embodiment, the voltage potential V _CM is the same as the potential of the scan electrodes in the display area 450 , but this is not intended to limit the invention. In other embodiments, the voltage potential V _CM is different from the potential of the scan electrodes.

In addition, a compensation electrode (such as CE _A in FIG. 3D ) can be formed while forming the pixel electrode (such as PE in FIG. 3D ) in the display region 450 . Therefore, the formation of the compensation electrode does not increase the manufacturing steps. In this embodiment, capacitors 461 - 463 are provided in overlapping regions of the compensation electrodes and the signal lines AC. By controlling the voltage potentials of the compensation electrodes and the signal lines A˜C, the capacitors C _A˜CC can have _a compensation effect.

When the space of the display area 250 is insufficient, the compensation modules 461 - 463 may also be disposed in at least one of the opposite terminal areas 431 - 433 . Furthermore, since the signal lines A˜D do not extend to the driving circuits of the anti-terminal areas 431˜433, the available space of the display panel 400 is larger, and capacitors with larger capacitances can be designed.

The present invention does not limit the installation position of the compensation module. In a possible embodiment, not only the anti-terminal area 432 has the compensation modules 461 - 463 , but also the display area 450 also has the compensation modules. In addition, if both ends of a signal line extend into the non-display area and are connected to the driving circuit (that is, the non-display areas on both sides of the signal line are close to the terminal area), then the compensation module coupled to the signal line will It is only set in the display area 450 . In other possible embodiments, in addition to the display area 450 and the anti-terminal areas 431 - 433 , the compensation module can also be disposed in the near-terminal area 410 .

Since the location of the compensation module is quite flexible, it can achieve higher compensation efficiency and even out the influence (charging and discharging time of pixels) caused by signal lines of different lengths. In addition, in other embodiments, when the compensation module is sufficient to even out the problems caused by signal lines of different lengths, the signal lines can adopt a sheet structure instead of a serpentine (z-shaped) structure, so that the signal line can be reduced. The area of the substrate occupied by the lines can be reduced, and the borders of the near-terminal regions 210 and 410 can be narrowed.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (20)

1. display panel comprises:

One viewing area has a plurality of pixels;

One non-display area is arranged on outside this viewing area, and comprises a near-end subarea; This near-end subarea has a plurality of signal wires; Said signal wire extends toward this viewing area, and one drive circuit sees through the said signal wire in this near-end subarea and this viewing area, said pixel is carried out one discharge and recharge action; And

At least one compensating module couples one first signal wire in the said signal wire, in order to compensate this first signal wire this is discharged and recharged the influence that action causes;

Wherein when this non-display area more comprises an anti-terminal region, this compensating module is arranged among at least one of this viewing area and this anti-terminal region, and when the two ends of this first signal wire all extended to this anti-terminal region, then this compensating module was arranged among this viewing area.

2. display panel as claimed in claim 1 is characterized in that, this compensating module is connected between this first signal wire and the compensating electrode.

3. display panel as claimed in claim 2 is characterized in that, this first signal wire is a data electrode, and this compensating electrode is the one scan electrode.

4. display panel as claimed in claim 2 is characterized in that, this first signal wire is a data electrode, and this compensating electrode is a common electrode.

5. display panel as claimed in claim 2 is characterized in that, this first signal wire is the one scan electrode, and this compensating electrode is a data electrode.

6. display panel as claimed in claim 2 is characterized in that this viewing area more comprises a plurality of pixel electrodes, and the material of said pixel electrode and this compensating electrode is a transparent conductive oxide, and said pixel electrode and this compensating electrode are insulated from each other.

7. display panel as claimed in claim 1 is characterized in that, this compensating module tool comprises one first side that one first conductive layer is arranged at this first signal wire, and one second conductive layer is arranged at one second side of this first signal wire.

8. display panel as claimed in claim 7 is characterized in that, this first conductive layer and this second conductive layer are electrical connected.

9. display panel as claimed in claim 7 is characterized in that this viewing area more comprises a plurality of pixel electrodes, and said pixel electrode and this first conductive layer are to be formed by same gold-tinted processing procedure.

10. display panel as claimed in claim 1; This compensating module comprises one first capacitor and one second capacitor; This first capacitor is to be made up of one first compensating electrode and this first signal wire, and this second capacitor is to be made up of this first signal wire and one second compensating electrode.

11. display panel as claimed in claim 10 is characterized in that, the appearance value of this first capacitor is different from the appearance value of this second capacitor.

12. display panel as claimed in claim 10 is characterized in that, this first compensating electrode and second compensating electrode are electrical connected.

13. display panel as claimed in claim 12 is characterized in that, this first capacitor is positioned at this non-display area, and this second capacitor is positioned at this viewing area.

14. display panel as claimed in claim 13 is characterized in that, this first capacitor is positioned at this anti-terminal region.

15. display panel as claimed in claim 10 is characterized in that, the part of at least one of this first compensating electrode and second compensating electrode is arranged in anti-terminal region.

16. display panel as claimed in claim 10 is characterized in that, this viewing area more comprises a plurality of pixel electrodes, and this first compensating electrode and said pixel electrode are to be formed by same gold-tinted processing procedure.

17. display panel as claimed in claim 16 is characterized in that, the material of this first compensating electrode and said pixel electrode is identical.

18. display panel as claimed in claim 16 is characterized in that, this first signal wire is a data electrode, and this second compensating electrode is the one scan electrode, and the material of this first compensating electrode material and said pixel electrode is identical.

19. display panel as claimed in claim 18 is characterized in that, this first compensating electrode is positioned at this non-display area.

20. display panel as claimed in claim 19 is characterized in that, this first compensating electrode is positioned at this anti-terminal region.

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