CN102779794B - For controlling the method and structure of warpage of packaging assembly - Google Patents
For controlling the method and structure of warpage of packaging assembly Download PDFInfo
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- CN102779794B CN102779794B CN201110324836.3A CN201110324836A CN102779794B CN 102779794 B CN102779794 B CN 102779794B CN 201110324836 A CN201110324836 A CN 201110324836A CN 102779794 B CN102779794 B CN 102779794B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
The invention provides a kind of method, the method comprises the warpage determining integrated circuit (IC) package design.IC package design comprises substrate, and this substrate has top solder mask on the first major surface and the bottom soldering-resistance layer on second first type surface relative with the first first type surface.First first type surface has the IC tube core be arranged on above top solder mask.Revise this design, comprise the average thickness of revised and comprise in the group of top solder mask and bottom soldering-resistance layer.IC encapsulation is manufactured and designed according to what revise.
Description
Technical field
The disclosure relates to semiconductor packages.
Background technology
Flip-chip utilizes the pedestal be deposited on IC pad, makes the method for the circuit interconnection in semiconductor device (such as integrated circuit (IC) chip) and package substrate.During wafer-process, deposit weld salient point on the IC pad on the top side of wafer.After cutting (singulation), upset IC chip so that its top surface is downward, and makes IC chip align so that its pad aligns with the coupling pad in package substrate, then makes flow of solder material to form interconnection.Introduce underfill in space between IC and substrate, make it around soldered ball.The space that flip-chip utilizes is less than in fact the space that wire-bonded utilizes, and the method can manufacture wafer-level package.
Flip-Chip Using substrate must have very flat surface, being heated and cooling due to plate, and maintenance surfacing may be more difficult.And soldered ball syndeton is stone.If IC and package substrate have different thermal coefficient of expansions (CTE), when encapsulation is heated and cool, different expansions can be produced.Different expansions makes that soldered ball syndeton has larger stress, and this can make syndeton cracked or separate with substrate, or makes package substrate warpage.
When flip-chip is included in three-dimensional (3D)-IC structure (such as stack package structure), also have other challenge.In stack package structure, in two IC packaging parts (such as application-specific integrated circuit (ASIC) (ASIC) and storage enclosure) is arranged on another top.Such as, top encapsulation can be greater than bottom package, and can have the welded ball array around this top encapsulation periphery, and this array is for the formation of the connection of the package substrate with bottom package.The structure of this such as stacked package adds the possibility of package substrate warpage.
Summary of the invention
According to an aspect of the present invention, a kind of packaging part is provided, wherein, described packaging part comprises: substrate, described substrate has top solder mask on the first major surface and the bottom soldering-resistance layer on second first type surface relative with described first first type surface, wherein said first first type surface has conductive welding disk, and the average thickness of wherein said bottom soldering-resistance layer is different from the average thickness of described top solder mask; And integrated circuit lead, described integrated circuit lead is arranged on above described top solder mask, and wherein said tube core has the pedestal being connected to described conductive welding disk.
Preferably, described top solder mask has the basic uniform thickness of the thickness being greater than described bottom soldering-resistance layer.Preferably, described top solder mask has at least one top channel in the position of one of described conductive welding disk, and described bottom soldering-resistance layer has at least one undercut.
Preferably, described undercut has multiple side, and described multiple side comprises the corresponding side surface of each respective side being parallel to described substrate.
Preferably, described undercut is arranged between the interior projected square part of described bottom soldering-resistance layer and the outer square frame part of described bottom soldering-resistance layer.
Preferably, described soldering-resistance layer is zero at the thickness at described undercut place.
Preferably, described bottom soldering-resistance layer has Part I and Part II, and the thickness of described Part I is greater than the thickness of described Part II.
Preferably, described top solder mask has the basic uniform thickness being less than described bottom soldering-resistance layer thickness.
Preferably, described packaging part comprises the second packaging part further, and described second packaging part is arranged on above described tube core, and described second packaging part is connected to the described substrate in stack package structure.
According to a further aspect in the invention, provide a kind of method, wherein said method comprises: arrange top solder mask across the first major surface of the substrate, and wherein said first first type surface has conductive welding disk; Second first type surface of described substrate arranges bottom soldering-resistance layer, and described second first type surface is relative with described first first type surface, and the average thickness of wherein said bottom soldering-resistance layer is different from the average thickness of described top solder mask; Be arranged on by integrated circuit lead above described top solder mask, wherein said tube core has pedestal; And connect described pedestal and described conductive welding disk.
Preferably, described top solder mask has the basic uniform thickness of the thickness being greater than described bottom soldering-resistance layer.
Preferably, described top solder mask is set and comprises: form at least one top channel in the position of one of described conductive welding disk, and arrange described bottom soldering-resistance layer comprise formed at least one undercut.
Preferably, described undercut has multiple side, and described multiple side comprises the corresponding side surface of each respective side being parallel to described substrate.
Preferably, described bottom soldering-resistance layer has Part I and Part II, and the thickness of described Part I is greater than the thickness of described Part II.
Preferably, described method comprises further and being arranged on described tube core by the second packaging part, and is connected to the described substrate in stack package structure.
In accordance with a further aspect of the present invention, a kind of method is provided, described method comprises: the warpage determining integrated circuit (IC) package design, wherein said IC package design comprises substrate, described substrate has top solder mask on the first major surface and the bottom soldering-resistance layer on second first type surface relative with described first first type surface, and wherein said first first type surface has the IC tube core be arranged on above described top solder mask; Revise described design, comprise the average thickness of revised and comprise in the group of described top solder mask and described bottom soldering-resistance layer, to reduce warpage; And manufacture IC encapsulation according to described amendment design.
Preferably, if determined warpage is convex, described correction comprises the average thickness increasing top solder mask, or reduces the average thickness of described bottom soldering-resistance layer.
Preferably, if determined warpage is matrix, described correction comprises the average thickness increasing described bottom soldering-resistance layer, or reduces the average thickness of described top solder mask.
Preferably, describedly determine to comprise: manufacture and design IC packaging part according to described; And the warpage that the IC measuring described manufacture encapsulates.
Preferably, the described computer execution model determining the stress distribution comprised in the described IC packaging part of operation.
Accompanying drawing explanation
Fig. 1 is the sectional view at the turning of the flip-chip installing tube core;
Fig. 2 A is the sectional view encapsulated in Fig. 1, this encapsulation have first bottom soldering-resistance layer thickness;
Fig. 2 B is the warpage profile encapsulated in Fig. 2 A;
Fig. 2 C is the isopleth map encapsulated in Fig. 2 B;
Fig. 3 A is the sectional view of the encapsulation of Fig. 1, this encapsulation have second bottom soldering-resistance layer thickness;
Fig. 3 B shows the warpage profile encapsulated in Fig. 3 A;
Fig. 3 C is the isopleth map encapsulated in Fig. 3 B;
Fig. 4 A-4C shows the fluted embodiment of tool in the soldering-resistance layer of bottom.Fig. 4 A is upward view, and Fig. 4 B is end view, and Fig. 4 C is the partial enlarged drawing of Fig. 4 B.
Fig. 5 A-5C shows the embodiment in the soldering-resistance layer of bottom with window.Fig. 5 A is upward view, and Fig. 5 B is end view, and Fig. 5 C is the partial enlarged drawing of Fig. 5 B.
Fig. 6 shows the example utilizing stack package structure;
Fig. 7 is the flow chart of the method manufacturing IC encapsulation; And
Fig. 8 is the flow chart of the method that Design and manufacture IC encapsulates.
Embodiment
Description for exemplary embodiment is intended to connection with figures and reads, and accompanying drawing is considered to a part for whole written description.In the description, relational language such as " lower ", " higher ", " level ", " vertical ", " in ... top ", " in ... below ", " upwards ", " downward " " top " and " bottom ", and its derivatives (such as, " flatly ", " down ", " up " etc.) should make an explanation with reference to the direction shown in accompanying drawing discussed below.These relational languages, for ease of describing object, not require to explain or operating means according to specific direction.About engaging, connecting and similar term, such as " connection " and " interconnection ", refer to mutually directly or by the relation between the structure of intermediate structure fixing or connection indirectly.
Contrary unless expressly stated, in the accompanying drawings, identical reference number represents same element.
Inventor determines, in multiple embodiments of IC encapsulation, can arrange the average soldering-resistance layer thickness of top solder mask and/or bottom soldering-resistance layer, or the pattern of bottom soldering-resistance layer, to control warpage of packaging assembly and stress levels.Therefore, packaging technology window and reliability can be improved.This technology, for various encapsulation, includes but are not limited to 3D IC encapsulation (such as those have the encapsulation of stack package structure) all very useful.
Fig. 1 is the side sectional view of encapsulation 100.Encapsulation 100 comprises package substrate dielectric layer 140, the dielectric such as FR-4 (woven design glass and epoxy resin) of package substrate dielectric layer 140 can be formed, or other preimpregnation materials (such as FR-2 (phenolic aldehyde cotton paper), FR-3 (cotton paper and epoxy resin), FR-5 (woven design glass and epoxy resin), FR-6 (frosted glass and polyester fiber), G-10 (woven design glass and epoxy resin), CEM-1 (cotton paper and epoxy resin), CEM-2 (cotton paper and epoxy resin), CEM-3 (woven design glass and epoxy resin), CEM-4 (woven design glass and epoxy resin), CEM-5 (woven design glass and polyester fiber).In other embodiments, substrate 140 can be made up of politef.
Each first type surface of substrate 140 is formed conductive layer 130,150.Conductive layer can be made up of thin copper foil (such as thickness is 15um).
As shown, supplemental dielectric layer 120 and 160 can be formed on the relative side of conductive layer 150 with 130.Insulating barrier 120 and 160 can be formed by the dielectric stacked together with such as epoxy prepreg, can also have the conductive trace be formed at wherein.
Coated polymer soldering-resistance layer on two sides of insulated substrate layer 120,160, be included in the top solder mask 170 on the first first type surface (top in Fig. 1), and the bottom soldering-resistance layer 110 on the second first type surface (it is relative with the first first type surface).Top solder mask 170 has thickness TT, and bottom soldering-resistance layer 110 has thickness TB, substrate can not have solder resist (soldering-resistance layer) coating by soldered region overlay.This solder resist prevents solder bridging to be connected between welding conductors and produces short circuit.Soldering-resistance layer 110,170 can be by the epoxy resin liquid of pattern silk-screen on substrate 140.In some embodiments, soldering-resistance layer can be formed by solder mask material, the PSR-4000 AUS703 that the TAIYO AMERICA Co., Ltd in the Carson city of this material such as Nevada sells.
Alternatively, in some embodiments, soldering-resistance layer 110,170 can be formed by liquid photosensitive solder resist (LPSM) ink.LPSM can silk-screen or sputter on substrate 140, pattern can be exposed to and development to be provided for the opening in the pattern of the parts by being soldered to copper pad.In other embodiments, soldering-resistance layer 110,170 can be formed by the photic solder resist of dry film (DFSM).Utilize vacuum to be stamped in by DFSM on printed circuit board (PCB) (PCB), then make it expose and develop.The thickness of soldering-resistance layer 110,170 can be about 12 to about 40 microns, but as discussed below, this thickness can change.In some embodiments, thickness TB can be controlled as at least 20 microns, and be less than 40 microns.
First first type surface (top) of substrate has multiple conductive welding disk 162, and contact 164 is formed on conductive welding disk 162.IC190 is mounted in the flip-chip above soldering-resistance layer 170, and makes the pedestal 182 of IC190 reflux to be formed and the electrical connection of contact 164 and mechanical connection.Backflow can be performed by such as body wave-soldering (bulk wave soldering) or reflow soldering.Utilize underfill 180 ring type filling around the space of salient point 182, and fill the gap between tube core 190 and package substrate 140.Underfill 180 forms the sealing of low warpage, and sealing can dissipate the stress on solder joint and can play thermal circulation performance.
Various technology can be utilized to form IC190.IC190 can be formed in silicon substrate, III-V substrate, silicon/germanium (SiGe) substrate, silicon-on-insulator (SOI) substrate or similar.
The thickness of top solder mask 170 and/or bottom soldering-resistance layer 110 can be changed, to control the warpage of package substrate 140.By adopting different average thickness TT and TB of top solder mask 170 and bottom soldering-resistance layer 110, the warpage type of warpage of packaging assembly in laminated substrates 140 can be changed.
Such as, as shown in figures 2 a-c, tube core attachment (die attach) backflow and substrate is cooled to after 25 DEG C, if the average thickness TB of bottom soldering-resistance layer 110 equals T1 substantially, and the average thickness TT that T1 equals top solder mask 170 equals 40um, result is convex warpage of packaging assembly.Such as, if TT=TB=40um, result is matrix warpage.
On the other hand, as shown in figs. 3 a-3 c, if the average thickness TB of bottom soldering-resistance layer 110 is T2, this thickness is less than the average thickness TT of top solder mask 170, and result is matrix warpage of packaging assembly.Such as, if TT=40um, and TB=20um to 25um, result is exactly matrix warpage.
In some embodiments, top solder mask 10 has basic uniform thickness TT, and this thickness is different from the basic uniform thickness TB of bottom soldering-resistance layer 110.Such as, the uniform thickness TB of bottom soldering-resistance layer 110 is decreased to and is more than or equal to 12um and the thickness being less than 40um (thickness of top solder mask 170), to reduce the concavity of substrate warpage.
In the encapsulation 200 of Fig. 6, the second encapsulation 192 is arranged on IC190, and is connected to the substrate in stack package structure.In the structure shown here, the low-density I/O ball grid array (BGA) of soldered ball 184 connects the conductive welding disk 162 on tube core 192 and substrate 140.Fig. 6 also show bottom soldering-resistance layer 110 and has the average thickness (it can be uniform thickness) being less than top solder mask 170.In an encapsulating products, warpage control is a key factor of process window, so the ability controlling warpage is very useful instrument.In stack package structure, soldering-resistance layer 110 can contact the PCB that packaging part is mounted thereon subsequently.Therefore, the warpage of regulation control substrate 140 is better than the warpage of the substrate (not shown) controlled in encapsulation 192.
Fig. 4 A-4C shows another embodiment substrate 400, in this substrate, controls the average thickness of bottom soldering-resistance layer 410,411,420 to control warpage of packaging assembly.Fig. 4 A is the upward view of substrate 400.Fig. 4 B and Fig. 4 C is side cross-sectional, view, illustrated therein is top solder mask 470 and have at least one top channel 472 in the position of one of conductive welding disk 162, and bottom soldering-resistance layer 410,411 has at least one undercut 420.The thickness of top solder mask 470 can be 40 microns, and takies the substrate gross area of 40%.Undercut 420 has multiple side (Fig. 4 A), comprises the corresponding side surface of each respective side being parallel to substrate 400.Therefore, undercut 420 is in the soldering-resistance layer of bottom between projected square part 411 and the outer square frame part 410 of bottom soldering-resistance layer.Bottom soldering-resistance layer 410,411,420 has Part I 410,411 and second (groove) part 420, and wherein the thickness of Part I 410,411 is greater than the thickness of second (groove) part 420.
In some embodiments, the thickness of soldering-resistance layer 410,420,411 in undercut 420 is zero, exposes dielectric layer 120 completely.(not shown) in other embodiments, the thickness of undercut 420 is greater than zero, and is less than the thickness of the Part I 410,411 of bottom soldering-resistance layer.The area of groove 420 can be changed, to control the average thickness of soldering-resistance layer 410,411,420.Such as, groove 420 can be formed by the substrate lower surface gross area of 10% to 60%.
In the example of Fig. 4 B-Fig. 4 C, groove 420 is set directly at the below of the groove 472 in top solder mask 470.Although with example, Fig. 4 B and Fig. 4 C illustrates that groove 420 and 472 has identical width G W, in other embodiments, the width of undercut 420 can be greater than or less than the width of top channel 472.Such as, for obtaining convex warped shapes, top channel can take the gross area of 40%, and undercut can take the gross area of 10%.For matrix warpage, the area percentage that undercut 420 takies is greater than the area percentage that top channel 472 takies.
Fig. 5 A-Fig. 5 C shows another embodiment substrate 500, wherein controls the average thickness of bottom soldering-resistance layer 410,520 to control warpage of packaging assembly.Fig. 5 A is the upward view of substrate 500.Fig. 5 B and Fig. 5 C is side cross-sectional, view, show top solder mask 470 and have at least one top channel 472 in the position of one of conductive welding disk 162, and bottom soldering-resistance layer 410 has at least one bottom windows 520.Bottom windows 520 has multiple side (Fig. 5 A), comprises the corresponding side surface of each respective side being parallel to substrate 500.Bottom soldering-resistance layer 410,520 has Part I 410 and second (window) part 520, and wherein the thickness of Part I 410 is greater than the thickness of second (window) part 520.In some embodiments, the thickness of soldering-resistance layer 410,520 in bottom windows 520 is zero, fully exposes dielectric layer 120.(not shown) in other embodiments, the thickness of bottom windows 520 is greater than zero, but is less than the thickness of the Part I 410 of bottom soldering-resistance layer.The area of window 520 can change, to control the average thickness of soldering-resistance layer.Such as, window 520 can be formed by the substrate lower surface gross area of 10% to 60%.
For any concrete package application, those of ordinary skill in the art are easy to determine whether the groove 420 of (by simulating or testing) Fig. 4 A-Fig. 4 C or the window 520 of Fig. 5 A-Fig. 5 C provide warping effect and the grade of expectation.It has been generally acknowledged that, this groove structure and window can provide good coplanar control to strengthen, and window structure can strengthen routability.For the encapsulation such as trace configurations with salient point, this groove is more favourable.
Fig. 7 is the flow chart of the method for the manufacture of IC encapsulation.
In step 700, arrange top solder mask across the first major surface of the substrate, this first first type surface has conductive welding disk.In some embodiments, the position that step 700 is included in one of conductive welding disk forms at least one top channel.
In step 702, second first type surface relative with the first first type surface of substrate arranges bottom soldering-resistance layer.The average thickness of bottom soldering-resistance layer is different from the average thickness of top solder mask.In some embodiments, step 702 comprises at least one undercut of formation.In some embodiments, undercut has multiple side, comprises the corresponding side surface of each respective side being parallel to substrate.In some embodiments, bottom soldering-resistance layer has Part I and Part II, and the thickness of Part I is greater than the thickness of Part II.In some embodiments, top solder mask has the basic uniform thickness (not comprising salient point area) being greater than bottom soldering-resistance layer thickness.
In step 704, be arranged on by integrated circuit lead above top solder mask, this tube core has pedestal.
In step 706, the second encapsulation is arranged on the tube core in stack package structure alternatively.In other embodiments, the second encapsulation (such as, as shown in Fig. 1, Fig. 4 B, Fig. 5 B) is eliminated.
In step 708, pedestal is connected to conductive welding disk.
Fig. 8 is the flow chart of the method for Design and manufacture IC encapsulation.
The method is from step 800.
In step 802, determine it is use the test data from the packaging part manufactured, or mechanical computer analogue data.
In step 804, if use test data, IC encapsulation just can be manufactured.IC package design comprises substrate, and this substrate has top solder mask on the first major surface, and the bottom soldering-resistance layer on second first type surface relative with the first first type surface.First first type surface has the IC tube core be arranged in top solder mask.
In step 806, measure the warpage of IC encapsulation.
In step 808, if use computer simulation data, with regard to computer simulations.Determine stress distribution and the displacement of each point in three dimensions.
In step 810, based on test data or computer simulation, determine the warpage that IC encapsulates.
In step 812, determine that this warpage is convex or matrix.
In step 814, if warpage is convex, so revise the average thickness comprising and increase top solder mask, or reduce the average thickness of bottom soldering-resistance layer.
In step 816, if warpage is matrix, so revise the average thickness comprising and reduce top solder mask, or increase the average thickness of bottom soldering-resistance layer.
As in Fig. 8 pointed by dotted line, after this design of correction, step 802-816 can be repeated alternatively in closed loop process, until test result or simulation show that the warpage achieving expectation reduces.
Alternatively, in ring-opening process embodiment, based on empirical data, step 802-816 can only be performed once, and based on the calculating that thickness changes, or based on the table lookup in the relation table from the warpage of previously having tested and top and bottom soldering-resistance layer, select the final soldering-resistance layer thickness revised.
In step 818, revise this design, comprise the average thickness of revised and comprise in the group of top solder mask and bottom soldering-resistance layer, to reduce warpage.Then IC encapsulation is manufactured and designed according to what be corrected.
In example described above, the warpage of encapsulation is symmetrical, and the soldering-resistance layer revised also is symmetrical.In other embodiments, there will be asymmetric warpage, adopt two different soldering-resistance layer thickness to reduce the asymmetric of warpage.
In some embodiments, encapsulation comprises substrate, and this substrate has top solder mask on the first major surface, and the bottom soldering-resistance layer on second first type surface relative with the first first type surface.First first type surface has conductive welding disk.The average thickness of bottom soldering-resistance layer is different from the average thickness of top solder mask.Integrated circuit lead is arranged in top solder mask.This tube core has the pedestal being connected to conductive welding disk.
In some embodiments, method comprises: arrange top solder mask across the first major surface of the substrate, and this first first type surface has conductive welding disk; Second first type surface relative with the first first type surface of substrate arranges bottom soldering-resistance layer, and the average thickness of bottom soldering-resistance layer is different from the average thickness of top solder mask; The integrated circuit lead with pedestal is arranged on above top solder mask; And connecting welding salient point and conductive welding disk.
In some embodiments, method comprises: the warpage determining integrated circuit (IC) package design, this IC package design comprises substrate, this substrate comprises top solder mask on the first major surface, and the bottom soldering-resistance layer on second first type surface relative with the first first type surface, this first first type surface has the IC tube core be arranged in top solder mask; Revise this design, comprise the average thickness of revised and comprise in the group of top solder mask and bottom soldering-resistance layer, to reduce warpage; And manufacture and design IC encapsulation according to what be corrected.
Although describe theme according to exemplary embodiment, but these exemplary embodiments are not for restriction.On the contrary, the claim of enclosing should be explained the most widely, to comprise other modification and embodiment that those of ordinary skill in the art can make.
Claims (19)
1. a packaging part, wherein, described packaging part comprises:
Substrate, described substrate has top solder mask on the first major surface and the bottom soldering-resistance layer on second first type surface relative with described first first type surface, wherein said first first type surface has conductive welding disk, and the average thickness of wherein said bottom soldering-resistance layer is different from the average thickness of described top solder mask; And
Integrated circuit lead, described integrated circuit lead is arranged on above described top solder mask, and wherein said tube core has the pedestal being connected to described conductive welding disk,
Described bottom soldering-resistance layer has at least one undercut,
Described undercut is arranged between the interior projected square part of described bottom soldering-resistance layer and the outer square frame part of described bottom soldering-resistance layer, and described undercut is that side is circlewise around described interior projected square part;
Change the area of described undercut, to control the average thickness of described bottom soldering-resistance layer.
2. packaging part according to claim 1, wherein said top solder mask has the basic uniform thickness of the thickness being greater than described bottom soldering-resistance layer.
3. packaging part according to claim 1, wherein said top solder mask has at least one top channel in the position of one of described conductive welding disk.
4. packaging part according to claim 3, wherein said undercut has multiple side, and described multiple side comprises the corresponding side surface of each respective side being parallel to described substrate.
5. packaging part according to claim 3, wherein said soldering-resistance layer is zero at the thickness at described undercut place.
6. packaging part according to claim 1, wherein said bottom soldering-resistance layer has Part I and Part II, and the thickness of described Part I is greater than the thickness of described Part II.
7. packaging part according to claim 1, wherein said top solder mask has the basic uniform thickness being less than described bottom soldering-resistance layer thickness.
8. packaging part according to claim 1, wherein said packaging part comprises the second packaging part further, and described second packaging part is arranged on above described tube core, and described second packaging part is connected to the described substrate in stack package structure.
9. a method, wherein said method comprises:
Arrange top solder mask across the first major surface of the substrate, wherein said first first type surface has conductive welding disk;
Second first type surface of described substrate arranges bottom soldering-resistance layer, described second first type surface is relative with described first first type surface, the average thickness of wherein said bottom soldering-resistance layer is different from the average thickness of described top solder mask, bottom soldering-resistance layer forms at least one undercut, between the interior projected square part that undercut is arranged on bottom soldering-resistance layer and the outer square frame part of bottom soldering-resistance layer, undercut is that side is circlewise around described interior projected square part; Change the area of described undercut, to control the average thickness of described bottom soldering-resistance layer;
Be arranged on by integrated circuit lead above described top solder mask, wherein said tube core has pedestal; And
Connect described pedestal and described conductive welding disk.
10. method according to claim 9, wherein said top solder mask has the basic uniform thickness of the thickness being greater than described bottom soldering-resistance layer.
11. methods according to claim 9, wherein arrange described top solder mask and comprise: form at least one top channel in the position of one of described conductive welding disk.
12. methods according to claim 9, wherein said undercut has multiple side, and described multiple side comprises the corresponding side surface of each respective side being parallel to described substrate.
13. methods according to claim 9, wherein said bottom soldering-resistance layer has Part I and Part II, and the thickness of described Part I is greater than the thickness of described Part II.
14. methods according to claim 9, wherein said method comprises further and being arranged on described tube core by the second packaging part, and is connected to the described substrate in stack package structure.
15. 1 kinds of methods, described method comprises:
Determine the warpage of IC package design, wherein said IC package design comprises substrate, described substrate has top solder mask on the first major surface and the bottom soldering-resistance layer on second first type surface relative with described first first type surface, wherein said first first type surface has the integrated circuit lead be arranged on above described top solder mask, bottom soldering-resistance layer has at least one undercut, between the interior projected square part that undercut is arranged on bottom soldering-resistance layer and the outer square frame part of bottom soldering-resistance layer, undercut is that side is circlewise around described interior projected square part,
Revise described design, comprise the average thickness of revised and comprise in the group of described top solder mask and described bottom soldering-resistance layer, to reduce warpage; Change the area of described undercut, to control the average thickness of described bottom soldering-resistance layer, and
Integrated antenna package is manufactured according to described amendment design.
16. methods according to claim 15, if wherein determined warpage is convex, described correction comprises the average thickness increasing top solder mask, or reduces the average thickness of described bottom soldering-resistance layer.
17. methods according to claim 15, if wherein determined warpage is matrix, described correction comprises the average thickness increasing described bottom soldering-resistance layer, or reduces the average thickness of described top solder mask.
18. methods according to claim 15, wherein saidly determine to comprise: manufacture and design ic package according to described; And measure the warpage of integrated antenna package of described manufacture.
19. methods according to claim 15, the wherein said computer execution model determining the stress distribution comprised in the described ic package of operation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/105,360 US8519535B2 (en) | 2011-05-11 | 2011-05-11 | Method and structure for controlling package warpage |
| US13/105,360 | 2011-05-11 |
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| CN102779794A CN102779794A (en) | 2012-11-14 |
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| US (1) | US8519535B2 (en) |
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| US10194537B2 (en) | 2013-03-25 | 2019-01-29 | International Business Machines Corporation | Minimizing printed circuit board warpage |
| KR102320046B1 (en) | 2014-09-19 | 2021-11-01 | 삼성전자주식회사 | Semiconductor Packages Having a Cascaded Chip Stack |
| US10319619B2 (en) | 2014-12-05 | 2019-06-11 | Samsung Electronics Co., Ltd. | Equipment for manufacturing semiconductor devices and method for use of same for manufacturing semiconductor package components |
| JP2019168315A (en) * | 2018-03-23 | 2019-10-03 | 三菱電機株式会社 | Measurement device, circuit board, display device, and method for measurement |
| CN109190152B (en) * | 2018-07-23 | 2023-04-07 | 桂林电子科技大学 | CSP welding spot structural parameter optimization method for reducing stress under power cycle-harmonic response coupling |
| CN109926112A (en) * | 2019-04-10 | 2019-06-25 | 中南大学 | The layered manufacturing method of three-dimensional microstructures polymeric micro-fluidic chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101432876A (en) * | 2006-04-27 | 2009-05-13 | 住友电木株式会社 | Semiconductor device and semiconductor device manufacturing method |
| US7602062B1 (en) * | 2005-08-10 | 2009-10-13 | Altera Corporation | Package substrate with dual material build-up layers |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6882045B2 (en) * | 1999-10-28 | 2005-04-19 | Thomas J. Massingill | Multi-chip module and method for forming and method for deplating defective capacitors |
| US20040084206A1 (en) * | 2002-11-06 | 2004-05-06 | I-Chung Tung | Fine pad pitch organic circuit board for flip chip joints and board to board solder joints and method |
| TWI221664B (en) * | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
| TWI245381B (en) * | 2003-08-14 | 2005-12-11 | Via Tech Inc | Electrical package and process thereof |
| KR100601881B1 (en) | 2004-01-28 | 2006-07-19 | 삼성전자주식회사 | Apparatus and method for routing path setting between routers in a chip |
| US7075016B2 (en) | 2004-02-18 | 2006-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Underfilling efficiency by modifying the substrate design of flip chips |
| JP4601365B2 (en) * | 2004-09-21 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US20060076681A1 (en) | 2004-10-13 | 2006-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package substrate for flip chip packaging |
| TWI249470B (en) * | 2005-03-09 | 2006-02-21 | Univ Nat Central | Structure and method of thermal stress compensation |
| JP5378707B2 (en) * | 2008-05-29 | 2013-12-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8350377B2 (en) * | 2008-09-25 | 2013-01-08 | Wen-Kun Yang | Semiconductor device package structure and method for the same |
| US8278214B2 (en) * | 2009-12-23 | 2012-10-02 | Intel Corporation | Through mold via polymer block package |
| US8604614B2 (en) * | 2010-03-26 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor packages having warpage compensation |
| US8183696B2 (en) * | 2010-03-31 | 2012-05-22 | Infineon Technologies Ag | Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads |
-
2011
- 2011-05-11 US US13/105,360 patent/US8519535B2/en active Active
- 2011-09-15 TW TW100133139A patent/TWI464834B/en active
- 2011-10-19 CN CN201110324836.3A patent/CN102779794B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602062B1 (en) * | 2005-08-10 | 2009-10-13 | Altera Corporation | Package substrate with dual material build-up layers |
| CN101432876A (en) * | 2006-04-27 | 2009-05-13 | 住友电木株式会社 | Semiconductor device and semiconductor device manufacturing method |
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| TW201246470A (en) | 2012-11-16 |
| CN102779794A (en) | 2012-11-14 |
| US20120286417A1 (en) | 2012-11-15 |
| US8519535B2 (en) | 2013-08-27 |
| TWI464834B (en) | 2014-12-11 |
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