TWI501352B - Integrated circuit packaging system with warpage control system and method of manufacture thereof - Google Patents

Integrated circuit packaging system with warpage control system and method of manufacture thereof Download PDF

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Publication number
TWI501352B
TWI501352B TW099109032A TW99109032A TWI501352B TW I501352 B TWI501352 B TW I501352B TW 099109032 A TW099109032 A TW 099109032A TW 99109032 A TW99109032 A TW 99109032A TW I501352 B TWI501352 B TW I501352B
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TW
Taiwan
Prior art keywords
substrate
patterned layer
patterned
layer
underfill
Prior art date
Application number
TW099109032A
Other languages
Chinese (zh)
Other versions
TW201044505A (en
Inventor
Rajendra D Pendse
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/412,303 priority Critical patent/US8217514B2/en
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW201044505A publication Critical patent/TW201044505A/en
Application granted granted Critical
Publication of TWI501352B publication Critical patent/TWI501352B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Description

Integrated circuit packaging system with warpage control system and manufacturing method thereof

The present invention is generally directed to an integrated circuit packaging system, and more particularly to an integrated circuit warping control system.

In the electronics industry, reducing the size of electronic devices (such as camcorders and portable phones) while increasing performance and speed has been a trend. Integrated circuit packages for complex systems typically include a plurality of interconnected integrated circuit chips. The integrated circuit wafers are typically fabricated from a semiconductor material such as germanium or gallium arsenide. The integrated circuit wafers can be mounted in a package that is then mounted on a printed circuit board.

This increased integrated circuit density has led to the development of multi-chip packages, package in packages (PIP), package on packages (POPs), or combinations thereof, which can package more than one Integrated circuit. Each package provides mechanical support for the individual integrated circuits and one or more interconnects that electrically connect the integrated circuit to the surrounding circuitry.

Typically, packages having integrated semiconductor wafers thereon typically include a substrate or other chip-mounting device. The substrate is a component that provides a mechanical base support and an electrical interface in the form of a package that will allow external access to the device housed within the package.

Today's multi-chip packages (also commonly referred to as multi-wafer modules) typically consist of a substrate to which a separate set of integrated circuit components are attached. It has been found that such a multi-chip package can increase the density and miniaturization of the integrated circuit, improve the signal transmission speed, reduce the size and weight of the entire bulk circuit, improve the performance, and reduce the cost. All of the above are the main goals of the integrated circuit industry. Modern trends.

Unfortunately, package warpage is a key issue in multi-wafer and multi-package packages, as well as single-die packages of large size. Especially for the package-on-package (PoP) technology, which typically utilizes flip chip interconnects to interconnect the semiconductor wafer to the base package, the warp of the base package has become such that it cannot be used for such packages. A significant limitation of the usual warpage specifications of the piece.

In a typical flip chip package, a negative curvature ("crying" warpage) occurs after the wafer attach and underfill process is completed. This is an expected result due to a mismatch in coefficient of thermal expansion (CTE) between the semiconductor wafer and the substrate. The goal of warpage control is to make the bonding of the wafer to the substrate as flat as possible. Since it is impossible to achieve absolute flatness, strict warpage specifications are usually applied. The curvature 俾 mentioned above is difficult to achieve the warpage specification, especially in the case of a 3-dimensional (3D) package such as a PoP base package (PoPb), the specifications are very strict.

Therefore, there is still a need to cater to the recent trends in semiconductor fabrication and packaging, to achieve better control and package warpage, and to increase package density. Finding answers to these questions is critical given the ever-increasing commercial competitive pressures and the reduced opportunities for growing consumers to expect meaningful product differentiation in the marketplace. In addition, the need to reduce costs, increase efficiency and effectiveness, and meet competitive pressures has increased the urgency to the critical need to find answers to these questions.

The answers to these questions have been considered for a long time, but previous developments have not taught or suggested any answers, and thus the answers to these questions have long plagued those of ordinary skill in the art to which the present invention pertains.

The present invention provides a method of fabricating an integrated circuit package system comprising: providing a substrate; and placing a patterned layer over the substrate to substantially remove crying warpage from the substrate.

The present invention provides an integrated circuit package system comprising: a substrate; and a patterned layer over the substrate for substantially removing crying warpage from the substrate.

Some embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. These steps or elements will become apparent to those of ordinary skill in the art in the <RTIgt;

The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It will be appreciated that other embodiments will be apparent, and that changes in the system, process, or mechanism can be made without departing from the scope of the invention.

Numerous specific details are set forth in the description which follows. However, it is understood that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some conventional circuits, system configurations, and process steps will not be disclosed in detail.

The drawings of the embodiments of the present invention are a part of the illustrations and are not to scale, and in particular, some of the dimensions are exaggerated in the drawings for clarity. Similarly, although the drawings in the drawings generally show similar directions for convenience of description, the representations in the drawings are largely undefined. In general, the invention can operate in any direction.

The various embodiments disclosed and described are to be considered in a For the convenience of description, the embodiments have been described as the first embodiment, the second embodiment, and the like, and are not intended to have any other meaning or to limit the present invention.

For the purposes of this description, the term "horizontal" as used herein is defined as a plane parallel to the plane or surface of a semiconductor substrate, regardless of its orientation. The term "vertical" is about the direction perpendicular to the level just defined. For example, "above", "below", "bottom", "top", "side" (such as "sidewall"), "higher" The terms "higher", "lower", "upper", "over", and "under" are relative to those shown in the figure. This horizontal plane is defined. The phrase "on" means that there is direct contact between components.

As used herein, the term "processing" includes the deposition, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist required to form the structure or photoresist.

Referring now to Fig. 1, there is shown a cross-sectional view of the semiconductor package system of the first embodiment of the present invention taken along line 1--1 of Fig. 2.

The illustrated semiconductor package 100 has a semiconductor wafer 102 that is attached to a substrate 104 via interconnect solder bumps 106. The semiconductor wafer 102 can be a flip chip or other type of semiconductor wafer. The substrate 104 can be a single structure or a laminated structure. The interconnect solder bumps 106 are sometimes encapsulated in a die attach adhesive or underfill 108.

A patterned resin layer 110 is formed on the substrate 104. In the simplest form, the pattern of the patterned resin layer 110 has a square or rectangle 112 centered about the semiconductor wafer 102, with the semiconductor wafer 102 placed as a barrier to prevent underfill 108. Overflow. In a more complex form, the patterned resin layer has additional openings 114 for attaching additional components 116 over the substrate 104. The additional component 116 can be attached by soldering.

The patterned resin layer 110 may be made of a number of different resins including a solder resist material, which is commonly used in substrate fabrication. It has been found that two or more layups of the solder resist material can be a cost effective way of laying the patterned resin layer 110.

In a typical configuration involving flip chip, there will be a result of "crying" warping or negative curvature of the edge of the substrate 104 that curves downward from the center of the substrate 104. This result is expected due to a mismatch in thermal expansion coefficient (CTE) between the turns of the semiconductor wafer 102 and the single or laminated structure of the substrate 104. This can result in poor or defective yields of the finished package.

The goal of the package is to make the bond of the semiconductor wafer 102 and the substrate 104 as flat as possible. Since it is impossible to achieve absolute flatness, strict warpage specifications are usually applied. The curvature mentioned above makes it difficult to achieve warpage specifications, especially in the case of 3D packages where the specifications are very severe.

In an embodiment of the invention, the patterned resin layer 110 is added to substantially remove the weeping warp. It has been found that the CTE value, filler loading, curing shrinkage factor, thickness, and coverage area of the resin material can be used to cause effective offset or neutralization of initial crying. The "reverse" warpage of the effects of warpage and the resulting substantially warped package.

It has also been found that by forming a layer of resin material having a desired pattern, modifying one of the variables, and observing the removal result of the weeping warp from the final package, all of the resin material can be determined without undue experimentation. Appropriate combination of CTE value, filler loading, hardening shrinkage factor, thickness, and coverage area.

In general, it has been found that increased CTE values, lower filler loading, higher hardening shrinkage factor, greater thickness, and increased coverage area have a tendency to increase back warpage, but for different substrates and semiconductors. Chip combinations, some combinations are better than others.

It has been found that the application of the patterned resin layer 110 effectively solves the problem of crying warpage, promotes and facilitates the implementation of warpage specifications, and enhances the reliability of the semiconductor package system.

Accordingly, it has been discovered that the integrated circuit package system of the present invention provides important and hitherto unknown and unobtainable solutions and capabilities for increased functional integration, increased package density, reduced processing and manufacturing complexity, reduced cost, and improved reliability. And functional aspects.

A base package solder ball 118 is attached to the bottom surface of the substrate 104 as a further step of assembly.

Referring now to Figure 2, there is shown a top plan view of a semiconductor package system in accordance with a first embodiment of the present invention.

The illustrated semiconductor package 100 has a semiconductor wafer 102 on the underfill 108. The patterned resin layer 110 is also shown around the semiconductor wafer 102. The shape and layout of the patterned resin layer 110 is designed to remove warpage of the package. The shape and layout of the patterned resin layer 110 will vary depending on the particular needs of the various packaging systems.

Referring now to Fig. 3, there is shown a cross-sectional view of Fig. 1 of a semiconductor package system 100 similar to the first embodiment of the present invention after the resin patterning stage of the process.

The substrate 104 is provided. The patterned resin layer 110 is then formed over the substrate 104. The formation of the patterned resin layer 110 can be achieved by a screen printing process. Also shown is a patterned solder resist layer 110' which is an optional solder resist layer deposited on the patterned solder resist layer 110' to counteract the weeping warp. The material of the patterned resin layer 110 and the patterned solder resist layer 110' may be different or the same.

The other openings 114 in the patterned resin layer 110 may be different in size from the solder openings 114' in the patterned solder resist layer 110'. It has been found that a difference in size between the other opening 114 and the solder opening 114' will help prevent solder from "wicking" out of the solder opening 114' because the solder opening 114' is a cylinder In the case of a box shape, the surface tension of the solder tends to form a sphere. By making the other opening 114 larger than the opening 114', a large number of spherical openings are formed to prevent the solder from sucking up.

Other processes may also be used to form the patterned resin layer 110.

Referring now to Figure 4, there is shown a cross-sectional view of Figure 3 after the wafer attachment phase of the process.

The semiconductor wafer 102 is then attached to the substrate 104 by the interconnect solder bumps 106. The semiconductor wafer 102 can be a flip chip.

Referring now to Figure 5, there is shown a cross-sectional view of Figure 4 after the underfill phase of the process.

The interconnect solder bumps 106 are encapsulated using the die attach adhesive or underfill 108. The die attach adhesive or underfill 108 can be of the resin type.

It has been found that the patterned resin layer 110 suitably designed to have a suitable thickness can be used to provide a "dam" for limiting the diffusion of the die attach adhesive or underfill 108, thereby resulting in reliability of the semiconductor package system. improve.

By determining the thickness of the patterned resin layer 110 such that the die attach adhesive or underfill 108 will stop flowing over the patterned resin layer 110, an undue experimentation may be required to determine the appropriate thickness.

Conversely, the number of die attach adhesives or underfills 108 can be tested to determine the amount by which the patterned resin layer will not overflow.

It has been found that by increasing the thickness of the patterned resin layer 110 to increase the height of the dam, the rectangle 112 around the semiconductor wafer 102 can be made smaller. This means that the die attach adhesive or underfill 108 occupies less area on the substrate 104, and further means that the semiconductor package can be made smaller.

It has been found that the patterned resin layer 110 can position the additional component 116 and control the collapse height of the solder bumps on the additional component 116. Both the size of the other opening 114 and the thickness of the patterned resin layer 110 will set the height of the additional component 116 above the substrate 104.

Referring now to Figure 6, there is shown a cross-sectional view of Figure 5 after the solder ball attachment stage of the process.

The base package solder ball 116 is then attached to the bottom surface of the substrate 104. There is a connection between the bottom surface and the top surface, but is not shown for clarity of illustration.

Referring now to Fig. 7, there is shown a cross-sectional view of Fig. 1 of a semiconductor package system similar to the second embodiment of the present invention after the wafer attachment stage of the process.

The illustrated semiconductor package 700 has a semiconductor wafer 102 attached to the substrate 104 via the interconnect solder bumps 106.

Referring now to Figure 8, there is shown a cross-sectional view of Figure 7 after the underfill phase of the process.

The die attach adhesive or underfill 108 is then used to encapsulate the interconnect solder bumps 106. The die attach adhesive or underfill 108 can be of the resin type.

Referring now to Figure 9, there is shown a cross-sectional view of Figure 8 after the resin patterning stage of the process.

Next, a patterned resin layer 902 is formed over the substrate 104. The formation of the patterned resin layer 902 may be a line dispenser process by placing a strip-shaped patterned resin layer 902. Opening 904 The square and rectangle will be formed around the semiconductor wafer 102 and the underfill 108, while the other openings 906 will be formed to attach the additional component 116 to a square or rectangle above the substrate 104.

Other processes may also be used to form the patterned resin layer 902.

Referring now to Figure 10, there is shown a cross-sectional view of Figure 9 after the solder ball attachment stage of the process.

The base package solder ball 118 is then attached to the bottom surface of the substrate 104.

Referring now to Figure 11, a flowchart of a method 1100 of fabricating an integrated circuit package system in a further embodiment of the present invention is shown. The method 1100 includes, in block 1102, providing a substrate; in block 1104, mounting a semiconductor wafer on the substrate; and in block 1106, placing a patterned material surrounding the semiconductor wafer on the substrate to remove Warpage of the substrate.

The resulting methods, processes, equipment, devices, products, and/or systems are straightforward, cost effective, uncomplicated, highly versatile, and effective, and can be modified by modifying known techniques. It is unexpectedly unrealistic to implement, and is therefore immediately suitable for efficiently and economically manufacturing semiconductor packaging systems that are fully compatible with conventional manufacturing processes and techniques.

Another important aspect of the present invention is that it greatly supports and helps to reduce costs, simplify systems, and enhance historical trends in performance.

These and other important aspects of the invention thus facilitate the state of the technology to at least the next level.

Although the present invention has been described in connection with the specific embodiments thereof, it is understood that many alternatives, modifications, and variations are apparent to those of ordinary skill in the art. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variations as fall within the scope of the appended claims. All matters presented herein or illustrated in the drawings are intended to be interpreted

100, 700. . . Semiconductor package

102. . . Semiconductor wafer

104. . . Substrate

106. . . Interconnect solder bump

108. . . Die attach adhesive or underfill

110, 902. . . Patterned resin layer

110’. . . Patterned solder resist

112. . . Square or rectangular

114, 904, 906. . . Opening

114’. . . Solder opening

116. . . Component

118. . . Base package solder ball

1--1. . . line

1100. . . method

1102, 1104, 1106. . . Square

1 is a cross-sectional view of the semiconductor package system of the first embodiment of the present invention taken along line 1--1 of FIG. 2;

2 is a plan view of a semiconductor package system of a first embodiment of the present invention;

Figure 3 is a cross-sectional view of a first embodiment of the semiconductor package system of the first embodiment of the present invention after the resin patterning stage of the process;

Figure 4 is a cross-sectional view of Figure 3 after the wafer attachment stage of the process;

Figure 5 is a cross-sectional view of Figure 4 after the underfill phase of the process;

Figure 6 is a cross-sectional view of Figure 5 after the solder ball attachment stage of the process;

Figure 7 is a cross-sectional view of the first embodiment of the semiconductor package system of the second embodiment of the present invention after the wafer attachment stage of the process;

Figure 8 is a cross-sectional view of Figure 7 after the underfill phase of the process;

Figure 9 is a cross-sectional view of Figure 8 after the resin patterning stage of the process;

Figure 10 is a cross-sectional view of Figure 9 after the solder ball attachment stage of the process;

Figure 11 is a flow chart of a method of fabricating an integrated circuit package system in a further embodiment of the present invention.

100. . . Semiconductor package

102. . . Semiconductor wafer

104. . . Substrate

106. . . Interconnect solder bump

108. . . Die attach adhesive or underfill

110. . . Patterned resin layer

112. . . Square or rectangular

114. . . Opening

116. . . Component

118. . . Base package solder ball

Claims (10)

  1. A method of fabricating an integrated circuit package system includes: providing a substrate; placing a patterned layer over the substrate to substantially remove crying warpage from the substrate, the patterned layer being a single continuous layer, the pattern The layer exposes the central opening and other plurality of openings in the patterned layer, and the patterned layer covers the entire upper surface of the substrate from the edge of the substrate to the edge of the central opening; directly on the central opening a semiconductor wafer; and a die attach adhesive or underfill between the semiconductor wafer and the substrate, the die attaching adhesive or the underfill on the entire surface of the central opening, and the die attach The adhesive or the underfill is in direct contact with the patterned layer.
  2. The method of claim 1, wherein: placing the patterned layer comprises patterning during placement of the patterned layer or during placement of the patterned layer.
  3. The method of claim 1, further comprising: forming the patterned layer surrounding the central opening to a thickness sufficient to block the die attach adhesive or the underfill.
  4. The method of claim 1, further comprising: placing a patterned solder resist layer on the substrate; and placing the patterned layer on the patterned solder resist layer.
  5. The method of claim 1, further comprising adjusting the thickness or coverage area of the patterned layer to substantially remove the crying warp.
  6. An integrated circuit packaging system comprising: a substrate; and a patterned layer over the substrate for substantially removing crying warpage from the substrate, the patterned layer being a single continuous layer, the patterned layer Exposed to the central opening and other plurality of openings in the patterned layer, and the patterned layer covers the entire upper surface of the substrate from the edge of the substrate to the edge of the central opening; the semiconductor wafer is directly mounted in the center On the opening; the die attach adhesive or underfill is between the semiconductor wafer and the substrate, the die attaches the adhesive or the bottom is filled on the entire surface of the central opening, and the die attaches The adhesive or the underfill is in direct contact with the patterned layer.
  7. The system of claim 6 wherein: the patterned layer comprises openings formed in the patterned layer as square or rectangular.
  8. The system of claim 6 wherein the patterned layer surrounding the central opening is formed to a thickness sufficient to block the die attach adhesive or the underfill.
  9. The system of claim 6 further comprising: a patterned solder resist layer on the substrate; and the patterned layer on the patterned solder resist layer.
  10. The system of claim 6 wherein the patterned layer has a thickness or coverage area to substantially remove the weeping warp.
TW099109032A 2008-04-07 2010-03-26 Integrated circuit packaging system with warpage control system and method of manufacture thereof TWI501352B (en)

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US12/412,303 US8217514B2 (en) 2008-04-07 2009-03-26 Integrated circuit packaging system with warpage control system and method of manufacture thereof

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TWI501352B true TWI501352B (en) 2015-09-21

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090001606A1 (en) * 2007-06-27 2009-01-01 Shinko Electric Industries Co., Ltd. Semiconductor package and semiconductor device using the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090001606A1 (en) * 2007-06-27 2009-01-01 Shinko Electric Industries Co., Ltd. Semiconductor package and semiconductor device using the same

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