CN102761342B - Viterbi decoder and viterbi coding method - Google Patents
Viterbi decoder and viterbi coding method Download PDFInfo
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Abstract
The open a kind of viterbi decoder of the present invention and viterbi coding method.Described viterbi decoder includes: data to decode manager, for the data to decode of input is distributed to multiple viterbi decoder unit；Multiple viterbi decoder unit, each viterbi decoder unit for carrying out Viterbi decoding based on forward direction slide block mode independently to the data to decode distributed, to obtain the decoding data of distributed data to decode, wherein, the data to decode that each viterbi decoder unit is corresponding includes synchronization blocks in succession, decoding block and backtracking block；And decoding data output manager, for receiving corresponding decoding data from the plurality of viterbi decoder unit, and combine and output decoding data.Viterbi decoder and viterbi coding method according to the present invention can provide higher decoding rate and higher hardware resource utilization.
Description
Technical field
The present invention relates to the convolutional code decoding technique in the communications field, more specifically, relate to a kind of viterbi decoder
(Viterbi decoder) and viterbi coding method.
Background technology
Convolutional code (convolution code) is the one of channel coding technology.Relative to block code, convolutional code maintains
The memory effect of channel.K information bit is weaved into n bit by convolutional code, but k and n is the least, is particularly suitable for serial shape
Formula is transmitted, and time delay is little.Different from block code, n code element after convolution coding not only k information with present segment has
Close, also relevant with N-1 segment information above.In cataloged procedure, inter-related he number is the constraint that nN, N are referred to as convolutional code
Length.The efficient channel coding that convolutional code is a kind of function admirable, hardware complexity is low, its performance is stable, a lot of logical
Communication system is applied.
The most common Convolutional Decoder Assembly is viterbi decoder and sequential decoding device.Viterbi decoder is at volume
When long-pending code constraint length is less (N ＜ 10), have compared with sequential decoding device that design structure is relatively easy, fast, the effect that calculates speed
The advantage that rate is high, is therefore widely used.
General viterbi decoder is made up of decision process part and traceback decoding part.Decision process part main
Work is compared and the storage etc. of state measurement value for the calculating of state measurement value, the additive operation of branched measurement value, substantially by
Branch metric unit (BMU, Branch metrics unit) 110, acs unit (ACSU, Add compare select
Unit) 120 and survivor path administrative unit (SMU, Survivor management unit) 130 3 part composition, such as Fig. 1 institute
Show.The data to decode received is first fed to branch metric unit 110, to calculate corresponding branched measurement value.Add ratio
The branched measurement value that old state measurement value newly calculates with branch metric unit 110 is added, after comparing by menu unit 120
Select to arrive the branch making the state measurement value after being added minimum in the branch of same code registers state to update
State measurement value.Survivor path administrative unit 130 stores and manages the path discriminative information that acs unit 120 produces.These are three years old
Part constitutes the basic processing unit (PE, Processing Element) of single channel viterbi decoder, is entered by data to decode
Row processes, and finally gives path discriminative information, and is stored in caching.Path discriminative information is believed as the input of traceback decoding part
Breath.Fig. 2 illustrates the schematic working timing figure of the traceback decoding part of viterbi decoder.Traceback decoding part is by adding ratio
The retrospective search of the path discriminative information that menu n ary operation obtains, not only obtained decoding output information, have also obtained time
On between, (baclkword) follows the tracks of the information of selected historic state backward.When the storage of survivor path information reaches certain depth
After, traceback decoding part can be followed the tracks of the most backward, to complete decoding.
The major technology bottleneck of Viterbi decoding design, is the flowing water caused due to the feedback loop configuration of acs unit
Line structure cannot be introduced directly into, and the bottleneck of the decoder arithmetic speed caused.In order to obtain sufficiently high decoding rate, typically
Use the mode of multidiameter delay.The design of the most conventional parallel viterbi decoder has base-2nLook ahead pattern, right
Folding slide block tupe etc..Base-2nLook ahead pattern is that the stepping length often walked by raising obtains parallel processing effect
's.But, base-2nLook ahead pattern becomes evolution owing to the speed obtained by advanced progression is increased with hardware spending quantity
Relation, the limited space that therefore speed improves.Doubling slide block tupe is then data block at forward and counter to be synced up also
Row fold handling, decoding result collects the pattern of caching, parallel output the most at last.Doubling slide block tupe, it is possible to substantially
Realize decoder speed and increase linear with hardware spending quantity, but in the case of the constraint degree of depth is relatively big, owing to compiling
Code memory state point is more, and depositor in viterbi decoder consumes relatively big, and leading due to forward and reverse slide block
Enter data from identical buffer shift register group, cause routing congestion, path delay to increase sharply and then during the work of reduction system
Clock.
Summary of the invention
The brief overview about the present invention given below, in order to provide about certain aspects of the invention is basic
Understand.Should be appreciated that this general introduction is not that the exhaustive about the present invention is summarized.It is not intended to determine the pass of the present invention
Key or pith, nor is it intended to limit the scope of the present invention.Its purpose is only to provide some concept in simplified form,
In this, as the preamble in greater detail discussed after a while.
An object of the present invention is to propose a kind of parallel viterbi decoder and viterbi coding method, to provide relatively
High decoding rate and higher hardware resource utilization.
According to an aspect of the invention, it is provided a kind of viterbi decoder, including: data to decode manager, use
In the data to decode of input being distributed to multiple viterbi decoder unit；The plurality of viterbi decoder unit, each
Viterbi decoder unit is translated for the data to decode distributed is carried out based on forward direction slide block mode Viterbi independently
Code, to obtain the decoding data of distributed data to decode, wherein, corresponding to be decoded of each viterbi decoder unit
Data include synchronization blocks in succession, decoding block and backtracking block；And decoding data output manager, for from the plurality of Wei Te
Receive corresponding decoding data than translator unit, and combine and export described decoding data.
According to another aspect of the present invention, it is provided that a kind of viterbi coding method, including: data to decode is divided
For multiple data segments；Each data segment is carried out independently Viterbi decoding based on forward direction slide block mode, to obtain every number
According to the decoding data of section, wherein, each data segment includes synchronization blocks in succession, decoding block and backtracking block；And by every number
Combine according to the decoding data of section and export.
Accompanying drawing explanation
The present invention can be by with reference to being better understood, wherein in institute below in association with the description given by accompanying drawing
Have in accompanying drawing and employ same or analogous reference to represent same or like parts.Described accompanying drawing is together with following
Describe the part comprising in this manual and being formed this specification together in detail, and be used for being further illustrated by this
The preferred embodiment of invention and the principle and advantage of the explanation present invention.In the accompanying drawings:
Fig. 1 illustrates the schematic block diagram of the decision process part of conventional single channel viterbi decoder；
Fig. 2 illustrates the schematic working timing figure of the traceback decoding part of conventional single channel viterbi decoder；
Fig. 3 illustrates the schematic block diagram of viterbi decoder according to embodiments of the present invention；
Fig. 4 illustrates the indicative flowchart of viterbi coding method according to embodiments of the present invention；
Fig. 5 illustrates single channel forward direction slide block type Viterbi decoding ideograph；
Fig. 6 illustrates multidiameter delay forward direction slide block type Viterbi decoding ideograph according to embodiments of the present invention；
Fig. 7 illustrates the schematic block diagram of viterbi decoder unit according to embodiments of the present invention；
Fig. 8 illustrates the schematic block diagram of processing unit according to embodiments of the present invention；
Fig. 9 illustrates the schematic block diagram of processing unit according to another embodiment of the present invention；And
Figure 10 illustrates the schematic block diagram of viterbi decoder unit according to another embodiment of the present invention.
Detailed description of the invention
Embodiments of the invention are described below with reference to accompanying drawings.In an accompanying drawing or a kind of embodiment of the present invention
The element and the feature that describe can combine with the element shown in one or more other accompanying drawing or embodiment and feature.
It should be noted that, for purposes of clarity, accompanying drawing and explanation eliminate unrelated to the invention, those of ordinary skill in the art
The parts known and the expression of process and description.
In order to provide higher decoding rate and higher hardware resource utilization, the present invention proposes a kind of sliding based on forward direction
The parallel viterbi decoder of block mode and viterbi coding method.
Fig. 3 illustrates the schematic block diagram of viterbi decoder according to embodiments of the present invention.As it can be seen, Viterbi decoding
Device 300 includes data to decode manager 310, multiple viterbi decoder unit 320 (viterbi decoder unit 1, Viterbi
Translator unit 2 ..., viterbi decoder unit m, m are the positive integer more than 1) and decoding data output manager
330.Data to decode manager 310 for distributing to multiple viterbi decoder unit 320 by the data to decode of input.Often
Individual viterbi decoder unit 320 is for carrying out dimension based on forward direction slide block mode independently to the data to decode distributing to it
The decoding of special ratio, to obtain distributing to the decoding data of its data to decode.Owing to carry out Wei Te based on forward direction slide block mode
Than decoding, the data to decode of each viterbi decoder unit 320 correspondence includes synchronization blocks in succession, decoding block and backtracking
Block.Each of synchronization blocks, decoding block and backtracking block is also referred to as slide block.Decoding data output manager 330 is for from multiple dimensions
Spy receives corresponding decoding data respectively than translator unit 320, and combines and export described decoding data, translates as final
Code result.
Owing to using parallel organization, and each viterbi decoder unit can carry out based on forward direction slide block side independently
The Viterbi decoding of formula, viterbi decoder the most according to embodiments of the present invention can carry out independence to multiple data blocks simultaneously
Decoding, thus higher decoding rate is provided.
Here, in conjunction with Fig. 4, Viterbi decoding principle based on forward direction slide block mode is described.Fig. 4 illustrates that single channel forward direction is sliding
Block formula Viterbi decoding ideograph.A convolutional code critical nature on grid chart is: from random time, it is assumed that initial
State measurement value is unknown, through carrying out L successivelysynAfter the operation of secondary forward direction (forward) Gabi selection, survivor path still can be with just
The survivor path obtained under beginning state measurement value known case overlaps.Here LsynIt is referred to as synchronization length (synchronization
Length), 5 times of generally convolutional code constraint length N.It addition, another critical nature that convolutional code is on grid chart is: no
Opinion original position how, when backtracking arrives certain traceback length LTrcAfter, survivor path all can condense together, thus just finds
True survivor path.Traceback length LTrcIt also it is typically 5 times of convolutional code constraint length N.The present invention utilizes the above-mentioned property of convolutional code
Matter, all retained before and after data block (decoding block) to be decoded one section of sufficiently long (>=5N) data block (synchronization blocks and
Backtracking block) so that whole data block (synchronization blocks, decoding block add backtracking block) can complete to translate independent of other data sequence
Code, as shown in Figure 4.
Correspondingly, in an embodiment of the present invention, the data to decode institute of each viterbi decoder unit 320 correspondence
Including the length of synchronization blocks more than or equal to the convolutional code constraint length of 5 times of data to decode, the length of backtracking block also greater than
Or the convolutional code constraint length equal to 5 times of data to decode.So, each viterbi decoder unit 320 just can be to being divided
The data to decode joined carries out Viterbi decoding based on forward direction slide block mode independently.
It addition, process for convenience, according to one embodiment of present invention, synchronization blocks, decoding block and backtracking block can have
There is identical length.As long as it is understood, however, that meet aforementioned condition, the length of three blocks can be different.
The workflow of viterbi decoder 300 is described below in conjunction with Fig. 5 and Fig. 6.
Fig. 5 illustrates the indicative flowchart of viterbi coding method according to embodiments of the present invention.In step S510, treat
Data to decode is divided into multiple data segment by decoding data manager 310.Each data segment will be distributed to a Viterbi and translate
Code device unit.Wherein, each data segment includes synchronization blocks in succession, decoding block and backtracking block.Here it is possible to by number to be decoded
According to manager 310, directly each data segment is divided into three blocks in succession, synchronization blocks, decoding block and backtracking block, it is also possible to often
After individual viterbi decoder unit 320 receives data segment, this data segment is divided into synchronization blocks in succession, decoding block and backtracking block
It is respectively processed, as long as data to decode manager 310 ensures that dividing data segment when the length of data segment can
Meet above-described synchronization blocks and the length limitation of backtracking block.Then, in step S520, each viterbi decoder unit
320 carry out Viterbi decoding based on forward direction slide block mode independently, respectively to obtain each data segment to each data segment
Decoding data.Then, in step S530, the decoding data of each data segment is combined also by decoding data output manager 330
Output, final decodes result continuously to be formed.
Fig. 6 illustrates multidiameter delay forward direction slide block type Viterbi decoding ideograph according to embodiments of the present invention.Reality at Fig. 6
Executing in example, the data to decode after caching is translated by data to decode manager 310 according to Viterbi based on forward direction slide block mode
Code principle carries out parallelization process.Specifically, data to decode manager 310 will include successively synchronization blocks (SVEx_Syn),
The data segment of decoding block (SVEx_Dec) and backtracking block (SVEx_Trc) distributes to viterbi decoder unit 1, Viterbi decoding
Device unit 2 ..., viterbi decoder unit m, enable each viterbi decoder unit segmentation concurrently to translate
Code, wherein, x represents the numbering of viterbi decoder unit.Synchronization blocks and backtracking block length meet above-described more than or
Condition equal to the convolutional code constraint length of 5 times of data to decode.Certainly, the numbering of viterbi decoder unit is the most right here
The data segment distribution of data to decode manager 310 produces constraint.It is to say, data to decode manager 310 can also be by
According to random order, such as the viterbi decoder unit of elder generation's viterbi decoder unit of odd-numbered, rear even-numbered is suitable
Sequence, sequentially distributes data segment.Further, since utilize backtracking method to decode, the decoding number of viterbi decoder unit output
According to generally contrary with the data to decode of input order.Therefore, it can each Wei Te by decoding data output manager 330
The decoding data obtained than translator unit combines accordingly, decodes result continuously with obtain normal sequence.
According to one embodiment of present invention, the decoding block in the respective data to decode of viterbi decoder unit 1-m
The data to decode of data to decode manager 310 is continuous and not crossover, to utilize each viterbi decoder list
Unit carries out the continuous decoding to data to decode.As shown in Figure 6, such as, on the left of figure takes turns in distribution, distributes to Viterbi
The decoding block (SVE1_Dec) of translator unit 1 corresponds to data to decode section Block (n), distributes to viterbi decoder list
The decoding block (SVE2_Dec) of unit 2 is corresponding to data to decode section Block (n+1), and the rest may be inferred, distributes to viterbi decoder
The decoding block (SVEm_Dec) of unit m corresponds to data to decode section Block (n+m-1).Certainly, those skilled in the art is also
Slight variations can be carried out according to the design of the present invention, make the decoding in the viterbi decoder respective data to decode of unit 1-m
Block is part crossover in the data to decode of data to decode manager 310, carries out respective handling, also when decoding output
Can realize decoding data to decode continuously, therefore the present invention is not limited to this.
As for the synchronization blocks in the viterbi decoder respective data to decode of unit 1-m and backtracking block, as mentioned before
Its length can be different and can be different from decoding block, and they can phase between individual viterbi decoder unit
Together can also be different.But, in order to data block divide facility, Fig. 6 by all of data block at all of viterbi decoder
Length between unit is all illustrated as identical, but this is not restrictive.
After the data segment distributed is decoded by each viterbi decoder unit 320, respectively obtain and distributed
The decoding data that data segment is corresponding.As shown in Figure 6, such as, on the left of figure takes turns in distribution, viterbi decoder unit 1
After the decoding block decoding distributed, obtain the decoding result corresponding with data to decode section Block (n), Viterbi decoding
After the device unit 2 decoding block decoding to being distributed, obtain the decoding result corresponding with data to decode section Block (n+1), depend on
This analogizes, and repeats no more.
Relative to the multidiameter delay structure of viterbi decoder 300, each viterbi decoder unit 320 could be for
Carry out the unit of single channel Serial viterbi decoding based on forward direction slide block mode.As example, Fig. 7 illustrates and implements according to the present invention
The schematic block diagram of the viterbi decoder unit of example.
As it is shown in fig. 7, viterbi decoder unit 700 includes that synchronization blocks processing unit (PE_Syn) 710, decoding block process
Unit (PE_Dec) 720, backtracking block processing unit (PE_Trc) 730, trace unit (TBE) 740 and decoding unit (TDE) 750.
Wherein, synchronization blocks processing unit 710 for carrying out branch metric and Gabi selection operation successively to the code element in synchronization blocks, to obtain
The state measurement value of each possible state of code registers that in synchronization blocks, last code element is corresponding.Decoding block processing unit 720
For the state measurement value of each possible state of code registers that last code element in synchronization blocks is corresponding as original state
Metric, the code element in paginal translation code block carries out branch metric and Gabi selection operation successively, to obtain decoding last in block
The state measurement value of each possible state of code registers that code element is corresponding is deposited with coding corresponding to each code element in decoding block
The path discriminative information of each possible state of device.Backtracking block processing unit 730 is for corresponding with last code element in decoding block
The state measurement value of multiple possible code registers state as original state metric, to the code element in backtracking block successively
Carry out branch metric and Gabi selection operation, to obtain recalling each possible state of code registers corresponding to each code element in block
Path discriminative information.Trace unit 740 is for the code registers each possible state corresponding according to all code elements in backtracking block
Path discriminative information to backtracking block carry out back tracking operation, with obtain merge survivor path.Decoding unit 750 is for backtracking
The terminal of the survivor path that unit 740 obtains is as starting point, each according to code registers corresponding to all code elements in decoding block
The path discriminative information of possible state carrys out paginal translation code block and carries out traceback decoding operation, to obtain decoding the decoding data of block.Due to
Utilizing backtracking method to decode, the decoding data of decoding unit 750 output is typically the decoding data of inverted order.
According to one embodiment of present invention, viterbi decoder unit 700 can also include inputting data processing unit
760, the data to decode distributed for caching, and the code element in the synchronization blocks in the data to decode that will be distributed is the most defeated
Entering to synchronization blocks processing unit 710, the code element in decoding block in the decoding data that will be distributed is input to decode at block one by one
The code element in backtracking block in reason unit 720, and the data to decode that will be distributed is input to recall block processing unit one by one
730.Should be appreciated that the work of input data processing unit 760 can also be by viterbi decoder according to embodiments of the present invention
In data to decode manager complete.
According to another embodiment of the invention, viterbi decoder unit 700 can also include discriminative information storage tube
Reason device 770, for storing path discriminative information and the path discriminative information of backtracking block of decoding block, and sentences the path of backtracking block
Certainly information distributes to trace unit 740, and the path discriminative information of decoding block is distributed to decoding unit 750.It is to be understood that, it is possible to
The path discriminative information of backtracking block is supplied directly to trace unit 740 by backtracking block processing unit 730, decoding block process
The path discriminative information of decoding block is supplied directly to decoding unit 750, by trace unit 740 and decoding unit 750 by unit 720
Carry out the storage of path discriminative information.
As example, the synchronization blocks processing unit 710 in viterbi decoder unit 700, decoding block processing unit 720 and
Backtracking block processing unit 730 all can use the processing unit shown in Fig. 8 to realize.According to the embodiment shown in Fig. 8, process single
Unit 800 is mainly made up of branch metric unit (BMU) 810 and acs unit (ACSU) 820.Branch metric unit 810 is used for
Branch metric is carried out, to obtain dividing of the described code element each possible state of corresponding code registers for the code element being currently received
Prop up metric.Acs unit 820 is for the branched measurement value obtained according to branch metric unit 810 and previous state metric value
Carry out Gabi selection operation, to obtain the state measurement value of each possible state of code registers corresponding to the code element that is currently received
With path discriminative information.
Operating for Gabi selection next time according to this state measurement value calculated to preserve, processing unit 800 is also
State measurement value register group 830 can be included.State measurement value register group 830 includes multiple state measurement value register,
For storing the state measurement value of the code element the being currently received each possible state of corresponding code registers respectively.
It addition, as it was noted above, decoding block processing unit 720 is deposited with the coding that last code element in synchronization blocks is corresponding
The state measurement value of each possible state of device as original state metric, the code element in paginal translation code block carry out successively branch metric and
Gabi selection operates, and recalls block processing unit 730 and post with the multiple possible coding that last code element in decoding block is corresponding
The state measurement value of storage state, as original state metric, carries out branch metric and Jia Bi successively to the code element in backtracking block
Selection operation. thus, processing unit 800 can also include enumerator 840 and MUX 850.Enumerator 840 is for branch
The operation times of metric element 810 and acs unit 820 counts.MUX 850 is for according to enumerator 840
Count the original state metric selecting former coagulation unit to pass over or with the code element being previously received
The state measurement value of the corresponding each possible state of code registers (state measurement after the computing that previous code element in Fig. 8 is corresponding
Value) as the previous state metric value (state measurement value before the computing in Fig. 8) of acs unit 820.
As example, for decoding block processing unit, when the counting of enumerator is equal to handled by this grade of processing unit
Data block, i.e. when the decoding length of block handled by decoding block processing unit or its integral multiple, control MUX 850 and select
Select original state metric that previous stage processing unit passes over as the previous state metric being input to acs unit 820
Value.Otherwise, control MUX 850 and select the shape of each possible state of code registers corresponding to the code element that is previously received
Metric values is as the previous state metric value being input to acs unit 820.For synchronization blocks processing unit 710, do not have
Having previous stage processing unit, therefore the prime PE state measurement value in MUX 850 could be arranged to zero.It addition, for
For synchronization blocks processing unit 710, owing to subsequent treatment need not use the path discriminative information of synchronization blocks, therefore Gabi selection list
Unit 820 can not outside outgoing route court verdict.For backtracking block processing unit 730, there is no rear stage processing unit,
Therefore after the computing of acs unit 820 output, state measurement value can essentially be not transferred to rear class PE.
In order to save hardware resource, the work clock of raising system, according to one embodiment of present invention, synchronization blocks processes
Each in unit, decoding block processing unit and backtracking block processing unit also includes the full zero unit of highest order, is used for
In the case of the highest order of the state measurement value of each possible state of code registers that the code element that is currently received is corresponding is one entirely,
The highest order of multiple state measurement values is set to zero.
Fig. 9 illustrates the schematic block diagram of the processing unit including the full zero unit of highest order according to described embodiment.
As it is shown in figure 9, the structure of processing unit 900 is essentially identical with the structure of the processing unit 800 shown in Fig. 8, the highest except including
The full zero unit 960 in position.The full zero unit 960 of highest order can be to shape after each computing of acs unit 920 output
Metric values judges, when after each computing, the highest order of state measurement value (binary representation) is for the moment entirely, each is transported
After calculation, the highest order of state measurement value is set to zero, and after each computing after then highest order being made zero, state measurement value is saved in
In state measurement value register group 930.When after each computing, the highest order of state measurement value (binary representation) is not all for the moment,
Directly state measurement value after each computing is saved in state measurement value register group 930.
In conventional parallel schema viterbi decoder, word length L of each state measurement value registerACSUIt is set to:
Wherein, ψmaxFor maximum branch metric, t is forward direction total step number (synchronization blocks, decoding block, the backtracking block length of slide block
Sum).And in the case of using the full zero unit of highest order according to embodiments of the present invention, state measurement value register
Word length LACSUFor:
Wherein, ψmaxFor maximum branch metric, ΔmaxFor each code registers obtained by synchronization acs unit
Maximum difference between the state measurement value of each possible state.Network according to viterbi decoder can obtain, synchronization
Maximum difference Δ between the state measurement value of each possible state of code registers obtained by acs unitmaxIt is limited:
Δmax≤ψmaxlog2M (3)
Wherein, ψmaxFor maximum branch metric, M is the number of each possible state of code registers.
By formula (2) it will be seen that the application of the full zero of highest order makes length and the cunning of state measurement value register
Block forward direction total step number is unrelated, will not increase along with the increase of slide block forward direction total step number, and can remain a steady state value.With
As a example by the data to decode of input is (2,1,7) Viterbi coded data that 3 bit soft information represent, owing to slider model is unidirectional
Step number, typically no less than 128, is obtained traditional approach code distance Register Word Length L by formula 1ACSUAt least 11, formula (2) must change
Enter rear code distance Register Word Length LACSUConstant is 8, therefore state measurement value register word length LACSUAt least can reduce 27%.
Further, since the full zero of highest order so that being sized to of state measurement value is maintained in smaller range.Therefore, shape is passed through
The full zero of highest order of metric values, it is possible to effectively reduce adder, the exponent number of comparator in acs unit, both saved
Hardware resource, improves again system work clock.
It addition, in order to improve decoding rate further, viterbi decoder unit can also use at multiple decoding block
The structure of reason unit.Figure 10 illustrates the schematic block diagram of viterbi decoder unit according to another embodiment of the present invention.At figure
In the embodiment of 10, it is single that the decoding block processing unit in each viterbi decoder unit can include that multiple decoding block processes son
Unit, for processing the decoding block in the data to decode distributing to described viterbi decoder unit concurrently, to improve decoding
Speed.As shown in Figure 10, in viterbi decoder unit 1000, including a synchronization blocks processing unit 1010, a backtracking
Block processing unit 1030, and p decoding block processing unit 1020, p is the positive integer more than 1.Decoding block processing unit 1020
Structure essentially identical with the decoding block processing unit 720 shown in Fig. 7.Other modules mould corresponding with Fig. 7 in Figure 10
The structure of block is identical.Describe for convenience, also viterbi decoder unit being included, the situation of multiple decoding block processing unit claims
Decoding block processing unit for viterbi decoder unit includes that multiple decoding block processes subelement.That is, decoding block processing unit
The 1020 decoding blocks that can also be described as decoding block processing unit 720 process subelement.
In order to improve the motility of viterbi decoder according to embodiments of the present invention, another according to the present invention is implemented
Example, data to decode manager 310 can be also used for only being distributed to by the data to decode of input multiple viterbi decoder list
A part in unit 320.Owing to each viterbi decoder unit 320 can independently carry out Viterbi decoding, therefore by treating
The control of decoding data manager 310 a, generally it is convenient to select road, two-way or more multichannel viterbi decoder unit run
Pattern, coordinates punching computing, can meet the requirement of multi code Rate of Chinese character and coding gain.
It addition, after the recipient of channel communication receives signal, before decoding, according to the quantization level of demodulator not
With, signal is carried out hard decision or soft-decision.Thus, the data to decode being input to viterbi decoder can be divided into through really up to the mark
The data to decode of judgement and through the data to decode (also referred to as Soft Inform ation) of soft-decision.To be decoded for through hard decision
For data, branched measurement value is the Hamming distance between sequence of symhols.For Soft Inform ation, branched measurement value is code element sequence
Euclidean distance between row.Viterbi decoder according to embodiments of the present invention can be to through hard decision with through soft-decision
Data to decode decodes, and does not has any restriction.The use of Soft Inform ation can bring bigger coding gain and higher
Error correcting capability, therefore, when reality is applied, it is preferable that can translate using Soft Inform ation as Viterbi according to embodiments of the present invention
The data to decode of code device.
Compared with Traditional parallel Viterbi decoding scheme, viterbi decoder and Viterbi according to embodiments of the present invention are translated
Code method carries out parallel Viterbi based on forward direction slider model decoding, has higher resource utilization.Due to each Wei Te
The structural models more relatively independent than between translator unit, the routing congestion occurred when can preferably reduce system synthesis, road
The problem that footpath postpones to increase sharply.
Further, since have relatively independent structural models between each viterbi decoder unit, user can facilitate
Ground selects a road to run, two-way runs or the pattern of more multi-channel running, coordinates punching computing, can meet some high-speed communication system
Multi code Rate of Chinese character and the requirement of coding gain in system.
Additionally, by state measurement value highest order complete 1 is negated, effectively reduce the adder of acs unit, compare
The exponent number of device, had both saved hardware resource, had improve the work clock of system the most significantly.
Although combine accompanying drawing above to describe embodiments of the invention in detail, it is to be understood that reality described above
The mode of executing is only intended to the present invention is described, and is not intended that limitation of the present invention.For a person skilled in the art, may be used
So that above-mentioned embodiment is made various changes and modifications without departing from the spirit and scope of the invention.Therefore, the present invention
Scope is only limited by appended claim and equivalents thereof.
Claims (19)
1. a viterbi decoder, including:
Data to decode manager, for distributing to multiple viterbi decoder unit by the data to decode of input；
The plurality of viterbi decoder unit, each viterbi decoder unit is for independent to the data to decode distributed
Ground carries out Viterbi decoding based on forward direction slide block mode, to obtain the decoding data of distributed data to decode, wherein, often
The data to decode that one viterbi decoder unit is corresponding includes synchronization blocks in succession, decoding block and backtracking block；And
Decoding data output manager, for receiving corresponding decoding data, and group from the plurality of viterbi decoder unit
Close and export described decoding data,
Wherein, each viterbi decoder unit includes decoding block processing unit, and described decoding block processing unit includes multiple
Decoding block processes subelement, for processing the described viterbi decoder distributing to described decoding block processing unit place concurrently
Decoding block in the data to decode of unit.
Viterbi decoder the most according to claim 1, wherein, the respective number to be decoded of the plurality of viterbi decoder unit
Decoding block according to is continuous and not crossover in the data to decode of described data to decode manager.
3. according to the viterbi decoder of claim 1 or 2, wherein, the length of described synchronization blocks be more than or equal to described in wait to translate
5 times of the convolutional code constraint length of code data, the length of described backtracking block is more than or equal to the convolutional code of described data to decode
5 times of constraint length.
Viterbi decoder the most according to claim 1, wherein, it is single that each viterbi decoder unit includes that synchronization blocks processes
Unit, for carrying out branch metric and Gabi selection operation successively, to obtain in described synchronization blocks to the code element in described synchronization blocks
The state measurement value of each possible state of code registers that later code element is corresponding,
Described decoding block processing unit is used for each possible shape of code registers that last code element in described synchronization blocks is corresponding
The state measurement value of state, as original state metric, carries out branch metric and Gabi selection successively to the code element in described decoding block
Operation, with obtain each possible state of code registers corresponding to last code element in described decoding block state measurement value and
The path discriminative information of each possible state of code registers that each code element in described decoding block is corresponding, and
Wherein, each viterbi decoder unit also includes:
Backtracking block processing unit, for the multiple possible code registers corresponding with last code element in described decoding block
The state measurement value of state, as original state metric, carries out branch metric and Jia Bi successively to the code element in described backtracking block
Selection operation, to obtain the path discriminative information of each possible state of code registers corresponding to each code element in described backtracking block；
Trace unit, for the road of the described code registers each possible state corresponding according to all code elements in described backtracking block
Footpath discriminative information carries out back tracking operation to described backtracking block, to obtain the survivor path merged；And
Decoding unit, for the terminal of survivor path that obtains using described trace unit as starting point, according in described decoding block
The path discriminative information of each possible state of described code registers corresponding to all code elements described decoding block is recalled
Decoded operation, to obtain the decoding data of described decoding block.
Viterbi decoder the most according to claim 4, wherein, each viterbi decoder unit also includes:
Input data processing unit, for the data to decode that distributed of caching, and same in the data to decode that will be distributed
Code element in step block is input to described synchronization blocks processing unit one by one, the code element in decoding block in the decoding data that will be distributed
The code element being input in described decoding block processing unit, and the backtracking block in the data to decode that will be distributed one by one is the most defeated
Enter to described backtracking block processing unit.
Viterbi decoder the most according to claim 4, wherein, each viterbi decoder unit also includes:
Discriminative information storage manager, the path judgement of path discriminative information and described backtracking block for storing described decoding block
Information, and the path discriminative information of described backtracking block is distributed to described trace unit, letter is adjudicated in the path of described decoding block
Breath distributes to described decoding unit.
Viterbi decoder the most according to claim 4, wherein, described synchronization blocks processing unit, described decoding block processing unit
Include with each in described backtracking block processing unit:
Branch metric unit, for carrying out branch metric for the code element being currently received, the volume corresponding to obtain described code element
The branched measurement value of each possible state of Code memory；And
Acs unit, for carrying out Gabi selection operation according to described branched measurement value and previous state metric value, to obtain
The state measurement value of each possible state of code registers that the described code element being currently received is corresponding and path discriminative information.
Viterbi decoder the most according to claim 7, wherein, described synchronization blocks processing unit, described decoding block processing unit
Also include with each in described backtracking block processing unit:
State measurement value register group, including multiple state measurement value registers, for be currently received described in storage respectively
The state measurement value of each possible state of described code registers that code element is corresponding.
9. according to the viterbi decoder of claim 7 or 8, wherein, described synchronization blocks processing unit, described decoding block process single
Each in first and described backtracking block processing unit also includes:
The full zero unit of highest order, at each possible shape of the described code registers that the described code element being currently received is corresponding
In the case of the highest order of the state measurement value of state is one entirely, the highest order of the plurality of state measurement value is set to zero.
Viterbi decoder the most according to claim 7, wherein, described synchronization blocks processing unit, described decoding block processing unit
Also include with each in described backtracking block processing unit:
Enumerator, for counting the operation times of described branch metric unit and described acs unit；And
MUX, for selecting to connect with original state metric or with previous according to the counting of described enumerator
The state measurement value of each possible state of code registers that the code element that receives is corresponding is as described previous state metric value.
11. viterbi decoders according to claim 1, wherein, described data to decode manager is further used for only by institute
The data to decode stating input distributes to the part in the plurality of viterbi decoder unit.
12. viterbi decoders according to claim 1, wherein, the data to decode of described input is after soft-decision
Soft Inform ation.
13. 1 kinds of viterbi coding methods, including:
Data to decode is divided into multiple data segment；
Each data segment is carried out independently Viterbi decoding based on forward direction slide block mode, to obtain the decoding of each data segment
Data, wherein, each data segment includes synchronization blocks in succession, decoding block and backtracking block；And
The decoding data of each data segment is combined and exports,
Wherein, each data segment is carried out independently Viterbi decoding based on forward direction slide block mode to obtain each data segment
Decoding data includes: process the decoding block in each data segment concurrently.
14. viterbi coding methods according to claim 13, wherein, the decoding block in each data segment is at described number to be decoded
It it is continuous according to and not crossover.
15. according to the viterbi coding method of claim 13 or 14, wherein, the length of described synchronization blocks is taken as more than or etc.
In 5 times of the convolutional code constraint length of described data to decode, be taken as the length of described backtracking block being more than or equal to described in treat
5 times of the convolutional code constraint length of decoding data.
16. viterbi coding methods according to claim 13, wherein, described are carried out based on forward direction slide block side each data segment
The Viterbi decoding of formula includes:
Branch metric and Gabi selection operation is carried out successively for the code element in described synchronization blocks, last to obtain in described synchronization blocks
The state measurement value of each possible state of code registers that one code element is corresponding；
In described synchronization blocks, the state measurement value of each possible state of code registers that last code element is corresponding is as initially
State measurement value, carries out branch metric and Gabi selection operation successively, to obtain described decoding block to the code element in described decoding block
In the state measurement value of each possible state of code registers corresponding to last code element and each code in described decoding block
The path discriminative information of each possible state of code registers that unit is corresponding；
Using the state measurement value of each possible state of code registers corresponding to last code element in described decoding block as just
Beginning state measurement value, carries out branch metric and Gabi selection operation successively, to obtain described backtracking to the code element in described backtracking block
The path discriminative information of each possible state of code registers that each code element in block is corresponding；
Path discriminative information according to each possible state of code registers corresponding to all code elements in described backtracking block is to described
Backtracking block carries out back tracking operation, to obtain the survivor path merged；And
Using the terminal of obtained survivor path as starting point, deposit according to the coding that all code elements in described decoding block are corresponding
Described decoding block is recalled and decoded operation by the path discriminative information of each possible state of device, to obtain described decoding block
Decoding data.
17. viterbi coding methods according to claim 16, wherein,
The operation of described branch metric includes: carry out branch metric for current symbol, the volume corresponding to obtain described current symbol
The branched measurement value of each possible state of Code memory；And
The operation of described Gabi selection includes: carry out Gabi selection operation according to described branched measurement value and previous state metric value, with
Obtain state measurement value and the path discriminative information of the described current symbol each possible state of corresponding code registers.
18. viterbi coding methods according to claim 17, also include:
The state measurement value of each possible state of described code registers that the code element that is currently received described in storage is corresponding respectively.
19., according to the viterbi coding method of claim 17 or 18, also include:
Highest order in the state measurement value of each possible state of described code registers corresponding to the described code element being currently received
In the case of being entirely one, the highest order of the plurality of state measurement value is set to zero.
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| EP1089441A2 (en) * | 1999-10-01 | 2001-04-04 | Matsushita Electric Industrial Co., Ltd. | Viterbi decoder and Viterbi decoding method |
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| CN101764622A (en) * | 2010-01-19 | 2010-06-30 | 清华大学 | Parallel multicode-rate convolutional code decoding method and realization device thereof |
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| EP1089441A2 (en) * | 1999-10-01 | 2001-04-04 | Matsushita Electric Industrial Co., Ltd. | Viterbi decoder and Viterbi decoding method |
| CN101247380A (en) * | 2008-03-27 | 2008-08-20 | 复旦大学 | High-speed vital ratio decoder for multi-tape orthogonal frequency division multiplexing ultra-broadband system |
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