CN102761328A - Frequency generation circuit used for generating output frequency signal and related method - Google Patents
Frequency generation circuit used for generating output frequency signal and related method Download PDFInfo
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- CN102761328A CN102761328A CN2011101134283A CN201110113428A CN102761328A CN 102761328 A CN102761328 A CN 102761328A CN 2011101134283 A CN2011101134283 A CN 2011101134283A CN 201110113428 A CN201110113428 A CN 201110113428A CN 102761328 A CN102761328 A CN 102761328A
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Abstract
The invention relates to a frequency generation circuit used for generating an output frequency signal, which comprises a pulse generator, a counter, a processing unit and a frequency generator, wherein the pulse generator is used for generating a first pulse signal; the counter is coupled to the pulse generator; after the first pulse signal is generated by the pulse generator, the counter begins to count by using a reference frequency signal so as to generate a counting value; the processing unit is coupled to the counter and used for receiving the counting value, and when the counting value reaches a critical value, a second pulse signal is generated; and the frequency generator is coupled to the pulse generator and the processing unit and used for generating an output frequency signal according to the first pulse signal and the second pulse signal.
Description
Technical field
The present invention relates to a kind of frequency generating circuit, refer to a kind of frequency generating circuit and correlation technique that can produce particular duty cycle especially.
Background technology
For some circuit; For example switched capacitor circuit (switching-capacitor circuit) or double data rate (Double Data Rate, DDR) DRAM (DynamicRandom-Access Memory, DRAM); The work period of frequency signal, (duty cycle) was very important; If it is 50% too many that the work period of frequency signal departs from, may have influence on the usefulness of circuit, serious situation also may cause the malfunction of circuit.Therefore, in general, in system, need the circuit of the work period of the signal of can adjusting frequency.
In general, prior art is to utilize digital delay line to adjust frequency work period of signal for example " An all-digital 50% duty-cycle corrector; IEEE, 2004, page II-925-II-928 "; Yet; The frequency that the length of digital delay line can receive frequency signal influences, and when the frequency of frequency signal is very low, can needs very long digital delay line and causes the increase of chip area.In addition, the design of digital delay line itself also needs long length to reduce the quantization error (quantization error) of foregoing circuit.
Summary of the invention
Therefore, one of the object of the invention is to provide a kind of frequency generating circuit and correlation technique that can produce particular duty cycle, and its chip area can not receive the influence of quantization error of frequency and the circuit of frequency signal, to solve the above problems.
According to one embodiment of the invention, a kind of frequency generating circuit that is used for producing output frequency signal includes pulse generator, counter, processing unit and frequency generator.This pulse generator is used for producing first pulse signal; This counter is coupled to this pulse generator, and wherein after this pulse generator produced this first pulse signal, this counter used reference frequency signal to begin counting, to produce count value; This processing unit is coupled to this counter, is used for receiving this count value, and when this count value arrives critical value, produces second pulse signal; This frequency generator is coupled to this pulse generator and this processing unit, is used for according to this first pulse signal and this second pulse signal to produce this output frequency signal.
According to another embodiment of the present invention, a kind of method that is used for producing output frequency signal includes: produce first pulse signal; After producing this first pulse signal, use a reference frequency signal to begin counting, to produce first count value; Receive this first count value, and when this first count value arrives critical value, produce second pulse signal; And according to this first pulse signal and this second pulse signal to produce this output frequency signal.
Description of drawings
Fig. 1 is the sketch map of frequency generating circuit that is used for producing output frequency signal according to first embodiment of the invention;
Fig. 2 is the sequential chart of each signal shown in Figure 1;
Fig. 3 is the sketch map of frequency generating circuit that is used for producing output frequency signal according to second embodiment of the invention;
Fig. 4 is a kind of method that is used for producing output frequency signal according to one embodiment of the invention.
Embodiment
With reference to figure 1, Fig. 1 is the sketch map of frequency generating circuit 100 that is used for producing output frequency signal CLK_OUT according to first embodiment of the invention.As shown in Figure 1, frequency generating circuit 100 includes pulse generator 110, counter 120, processing unit 130 and frequency generator, and (in present embodiment, this frequency generator is for setting/reset (Set/Reset, SR) latch unit 140).Wherein frequency generating circuit 100 is used for receiving input frequency signal CLK_IN, and input frequency signal CLK_IN is adjusted into the have particular duty cycle output frequency signal CLK_OUT of (duty cycle).
Simultaneously with reference to figure 1 and Fig. 2, Fig. 2 is the sequential chart of each signal shown in Figure 1.In the operation of frequency generating circuit 100; At first; Pulse generator 110 receives input frequency signal CLK_IN; And by the edge-triggered of input frequency signal CLK_IN (is that positive edge triggers in present embodiment) to produce the first pulse signal PA, wherein pulse signal PA has the identical cycle with input frequency signal CLK_IN.Then; Counter 120 begins counting producing the first count value CV by the edge-triggered of the first pulse signal PA (is that positive edge triggers in present embodiment) with the reference frequency signal CLK_REF that uses oscillator 150 to be produced, and the first count value CV is sent to processing unit 130.Then, processing unit 130 receives the first count value CV, and when the first count value CV arrives critical value; Produce the second pulse signal PB; Wherein this critical value is used for representing the pairing count value of this particular duty cycle, for instance, supposes that the count value that the periodic width T of the first pulse signal PA corresponds to is 10; Suppose that then frequency generating circuit 100 is to be used for producing the output frequency signal CLK_OUT that 50%T does the cycle, then this critical value then is 5; And if frequency generating circuit 100 is the output frequency signal CLK_OUT that were used for producing 30% work period, then this critical value then is 3 ... By that analogy.In addition, this critical value can be set or by 100 generations of frequency generating circuit, is dissolved in following row again in the correlative detail and narrate by the designer.At last, the SR latch unit 140 reception first pulse signal PA and the second pulse signal PB are to produce output frequency signal CLK_OUT.
About processing unit 130 employed these critical values; In one embodiment of the invention; Begin to produce before the output frequency signal CLK_OUT with this particular duty cycle at frequency generating circuit 100; The periodic width T that counter 120 use reference frequency signal CLK_REF calculate the first pulse signal PA is to produce second count value; Afterwards, processing unit 130, and is temporary in this critical value in the processing unit 130 and uses for subsequent operation producing this critical value (concrete instance can fall said with reference to the preceding paragraph) according to this second count value and this particular duty cycle.
In frequency generating circuit 100; No matter the frequency of input frequency signal CLK_IN how; Frequency generating circuit 100 all can produce the output frequency signal CLK_OUT with ideal operation cycle really; Therefore, the chip area of frequency generating circuit 100 can not receive the influence of quantization error of frequency and the circuit of input frequency signal CLK_IN.
In addition; In frequency generating circuit 100; Processing unit 130 uses the first pulse signal PA to operate, yet, in other embodiments of the invention; Processing unit 130 can also change into and use input frequency signal CLK_IN to operate, and the variation in these designs all should be under the jurisdiction of category of the present invention.
With reference to figure 3, Fig. 3 is the sketch map of frequency generating circuit 300 that is used for producing output frequency signal CLK_OUT according to second embodiment of the invention.As shown in Figure 3, frequency generating circuit 300 includes pulse generator 310, counter 320, processing unit 330 and frequency generator (in present embodiment, this frequency generator is a SR latch unit 340).Wherein frequency generating circuit 300 is used for receiving input frequency signal CLK_IN, and input frequency signal CLK_IN is adjusted into the output frequency signal CLK_OUT with particular duty cycle.
Simultaneously with reference to the 2nd, 3 figure; In the operation of frequency generating circuit 300; At first; Pulse generator 310 receives input frequency signal CLK_IN, and to produce the first pulse signal PA, wherein pulse signal PA has the identical cycle with input frequency signal CLK_IN by the edge-triggered (is that positive edge triggers in present embodiment) of input frequency signal CLK_IN.Then; Counter 320 begins counting producing the first count value CV by the edge-triggered of input frequency signal CLK_IN (is that positive edge triggers in present embodiment) with the reference frequency signal CLK_REF that uses oscillator 350 to be produced, and the first count value CV is sent to processing unit 330.Then; Processing unit 330 receives the first count value CV; And when the first count value CV arrives critical value; Produce the second pulse signal PB, wherein this critical value is used for representing the pairing count value of this particular duty cycle, and this critical value can be by designer's setting or by 300 generations of frequency generating circuit.At last, the SR latch unit 340 reception first pulse signal PA and the second pulse signal PB are to produce output frequency signal CLK_OUT.
In addition; In frequency generating circuit 300; Processing unit 330 uses input frequency signal CLK_IN to operate, yet, in other embodiments of the invention; Processing unit 330 can also change into and use the first pulse signal PA to operate, and the variation in these designs all should be under the jurisdiction of category of the present invention.
With reference to figure 4, Fig. 4 is a kind of method that is used for producing output frequency signal according to one embodiment of the invention.With reference to the 1st～4 figure, flow process is narrated as follows:
Step 400: produce first pulse signal.
Step 402: after producing this first pulse signal, use reference frequency signal to begin counting, to produce first count value.
Step 404: receive this first count value, and when this first count value arrives critical value, produce second pulse signal.
Step 406: according to this first pulse signal and this second pulse signal to produce this output frequency signal.
Concise and to the point conclusion the present invention; A kind ofly be used for producing in the frequency generating circuit and correlation technique of output frequency signal in of the present invention; Utilize pulse generator, counter, processing unit and frequency generator to produce output frequency signal with particular duty cycle; Compared to utilizing the adjust frequency prior art of work period of signal of digital delay line; The chip area of frequency generating circuit of the present invention can not receive the influence of quantization error of frequency and the circuit of input frequency signal, therefore has preferable efficient and lower cost.
The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (11)
1. frequency generating circuit that is used for producing output frequency signal includes:
Pulse generator is used for producing first pulse signal;
Counter is coupled to said pulse generator, and wherein after said pulse generator produced said first pulse signal, said counter used reference frequency signal to begin counting, to produce first count value;
Processing unit is coupled to said counter, is used for receiving said first count value, and when said first count value arrives critical value, produces second pulse signal; And
Frequency generator is coupled to said pulse generator and said processing unit, is used for said first pulse signal of foundation and said second pulse signal to produce said output frequency signal.
2. frequency generating circuit as claimed in claim 1, wherein said counter begins counting by the edge-triggered of said first pulse signal to use said reference frequency signal.
3. frequency generating circuit as claimed in claim 1, wherein said pulse generator by the edge-triggered of input frequency signal to produce said first pulse signal.
4. frequency generating circuit as claimed in claim 3, wherein said counter begins counting by the edge-triggered of said input frequency signal to use said reference frequency signal.
5. frequency generating circuit as claimed in claim 1; Wherein said frequency generating circuit is used for producing the said output frequency signal with particular duty cycle; And said counter uses periodic width that said reference frequency signal calculates said first pulse signal producing second count value, and said processing unit according to said second count value and said particular duty cycle to produce said critical value.
6. frequency generating circuit as claimed in claim 1, wherein said frequency generator is for setting/reset latch unit.
7. method that is used for producing output frequency signal includes:
Produce first pulse signal;
After producing said first pulse signal, use reference frequency signal to begin counting, to produce first count value;
Receive said first count value, and when said first count value arrives critical value, produce second pulse signal; And
Said first pulse signal of foundation and said second pulse signal are to produce said output frequency signal.
8. method as claimed in claim 7, the step of wherein using said reference frequency signal to begin to count includes:
Edge-triggered by said first pulse signal begins counting to use said reference frequency signal.
9. method as claimed in claim 7, the step that wherein produces said first pulse signal includes:
By the edge-triggered of input frequency signal to produce said first pulse signal.
10. method as claimed in claim 9, the step of wherein using said reference frequency signal to begin to count includes:
Edge-triggered by said input frequency signal begins counting to use said reference frequency signal.
11. the method for claim 1 be used for producing the said output frequency signal with particular duty cycle, and said method includes also:
Use periodic width that said reference frequency signal calculates said first pulse signal to produce second count value; And
Said second count value of foundation and said particular duty cycle are to produce said critical value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011101134283A CN102761328A (en) | 2011-04-27 | 2011-04-27 | Frequency generation circuit used for generating output frequency signal and related method |
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| CN2011101134283A CN102761328A (en) | 2011-04-27 | 2011-04-27 | Frequency generation circuit used for generating output frequency signal and related method |
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| CN102761328A true CN102761328A (en) | 2012-10-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391422A (en) * | 2017-07-19 | 2017-11-24 | 上海航天测控通信研究所 | multi-path asynchronous serial communication data access system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611675A (en) * | 1979-07-04 | 1981-02-05 | Marantz Japan Inc | Key-touch strength changing circuit for automatic playing piano |
| CN101472370A (en) * | 2007-12-26 | 2009-07-01 | 夏普株式会社 | Pulse signal delay circuit and led drive circuit |
| US20090261877A1 (en) * | 2008-04-18 | 2009-10-22 | Hsien-Sheng Huang | Duty cycle correction circuit with wide-frequency working range |
-
2011
- 2011-04-27 CN CN2011101134283A patent/CN102761328A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611675A (en) * | 1979-07-04 | 1981-02-05 | Marantz Japan Inc | Key-touch strength changing circuit for automatic playing piano |
| CN101472370A (en) * | 2007-12-26 | 2009-07-01 | 夏普株式会社 | Pulse signal delay circuit and led drive circuit |
| US20090261877A1 (en) * | 2008-04-18 | 2009-10-22 | Hsien-Sheng Huang | Duty cycle correction circuit with wide-frequency working range |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391422A (en) * | 2017-07-19 | 2017-11-24 | 上海航天测控通信研究所 | multi-path asynchronous serial communication data access system and method |
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Application publication date: 20121031 |