CN102760684A - Metal interconnection method - Google Patents
Metal interconnection method Download PDFInfo
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- CN102760684A CN102760684A CN2011101050697A CN201110105069A CN102760684A CN 102760684 A CN102760684 A CN 102760684A CN 2011101050697 A CN2011101050697 A CN 2011101050697A CN 201110105069 A CN201110105069 A CN 201110105069A CN 102760684 A CN102760684 A CN 102760684A
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Abstract
The invention discloses a metal interconnection method which comprises the following steps of: etching a dielectric layer; forming a groove in the dielectric layer; depositing metal copper; filling the deposited copper in the groove, and covering the surface of the dielectric layer; polishing the metal copper to the surface of the dielectric layer by the CMP (chemical mechanical polishing) technology; forming an etching stop layer with compressive stress on the dielectric layer; and forming a barrier layer with tension stress on the etching stop layer with compressive stress. The method disclosed by the invention can reduce the influence of high-frequency power on the integrity of a gate oxide layer.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of metal interconnected method.
Background technology
Along with the development of semiconductor fabrication process, the area of semiconductor chip is more and more littler, and simultaneously, the quantity of the semiconductor device on a semiconductor chip is also more and more.In semiconductor circuit; Signal transmission between the semiconductor device needs highdensity interconnection line, and in traditional semiconductor technology, metallic aluminium generally is used as the metal interconnecting wires between the semiconductor device; Development along with semiconductor technology; The metallic aluminium interconnection line is substituted by the metallic copper interconnection line, and this is because metallic copper is compared with metallic aluminium and had less resistance value, adopts the metallic copper interconnection line can improve the transmission speed of signal between the semiconductor device.
Introduce based on the metal interconnected method of metallic copper in the face of in the prior art down, Fig. 1～Fig. 3 is the process generalized section of metal interconnected method in the prior art.Metal interconnected method of the prior art may further comprise the steps:
Groove shown in Figure 1 is used for the follow-up formed metallic copper interconnection line that holds.
In practical application, dielectric layer 101 can be the insulating material of low-k, also claims low K value insulating material.
Can find out that by Fig. 2 after the CMP technology, metallic copper 102 only is filled in the groove, form said metallic copper interconnection line.
Common ground; The main component of etching stop layer 103 is the fire sand (SiCN) with compression; Why has compression at practical application desired etching stop layer 103; Be to apply certain pressure to the metallic copper in the groove 102, under the effect of electric field electromigration take place outside to prevent metallic copper, and cause the interfacial diffusion of metallic copper because have the etching stop layer 103 of compression.Metal is a crystal, and the crystals metal ion is arranged according to the order of sequence, as External Electrical Field during at metallic conductor; Because effect of electric field just makes metal ion produce directed movement; Be the transport phenomena of metal ion, electromigration that Here it is can cause the interfacial diffusion of metallic copper.
In addition, when the main component of etching stop layer 103 is when having the SiCN of compression, the method that forms etching stop layer 103 is: adopt high density plasma CVD (HDP CVD) technology on dielectric layer 101, to deposit the SiCN with compression.
Fig. 4 is the structural representation of HDP CVD device in the prior art.As shown in Figure 4, on inductance coil 1002, apply high frequency power through high frequency power generator 1001, thereby around inductance coil 1002, generate an electromagnetic field; Gas is passed into the cavity 1004 from air inlet 1003 then; Ionization takes place and forms plasma in gas under the effect of electromagnetic field, wafer W is positioned on the electrostatic chuck 1005, simultaneously; On wafer W, apply low frequency power through low frequency power generator 1006; So just make there is a bigger voltage difference between wafer W and the plasma that have directivity thereby make towards the ionization base of wafer W motion, low frequency power also can be described as bias power (bias power).
Need to prove that HDP CVD device of the prior art possibly also comprise other parts, because other parts and the present invention are irrelevant, so introduce in detail no longer one by one.
So far, be that example finishes to the metal interconnected method introduction based on metallic copper with Fig. 1 to Fig. 3, need to prove that Fig. 1 to Fig. 3 only illustrates the manufacture method of layer of metal interconnection structure, the manufacture method of other layers metal structure all is similar.In addition; It will be appreciated by those skilled in the art that; Metal interconnect structure must be formed on the active area; Said active area comprises the gate oxide, grid side walls layer, drain electrode, source electrode of grid, grid below etc., because the said structure of active area is not in discussion category of the present invention, so introduction in detail no longer one by one.
When in above-mentioned steps 103, adopting HDP CVD process deposits etching stop layer 103, high frequency power, low frequency power and gas flow are main technological parameter, and the technical staff finds; No matter the size of gas flow when high frequency power is bigger, can guarantee deposition rate; Thereby guarantee output (throughput); But the integrality of the gate oxide of made semiconductor device (GOI, gateoxide integrality) always is affected.Wherein, GOI is an important indicator weighing performance of semiconductor device, and when GOI was good more, then the puncture voltage of semiconductor device was high more, that is to say, when GOI is good more, then semiconductor device be difficult for breakdown.In the prior art, the integrality of gate oxide is impacted this problem, also do not have desirable solution to high frequency power.
Summary of the invention
In view of this, the present invention provides a kind of metal interconnected method, can reduce the influence that high frequency power causes the integrality of gate oxide.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that
A kind of metal interconnected method, this method comprises:
To the dielectric layer etching, in said dielectric layer, form groove;
Plated metal copper, the metallic copper that is deposited is filled in the said groove, and covers said dielectric layer surface, adopts cmp CMP technology said metallic copper to be polished to the surface of dielectric layer then;
On said dielectric layer, form etching stop layer with compression;
On said etching stop layer with compression, form barrier layer with tensile stress.
Said etching stop layer with compression is: the fire sand SiCN with compression;
The method that then said formation has the etching stop layer of compression is: adopt high density plasma CVD HDP CVD technology on dielectric layer, to deposit the SiCN with compression.
Said barrier layer with tensile stress is: have the fire sand SiCN of tensile stress or have the silicon nitride SiN of tensile stress;
Then said formation have tensile stress the barrier layer method can for: adopt density plasma chemical vapour deposition (CVD) HDP CVD technology having the SiN that deposition on the etching stop layer of compression has the SiCN of tensile stress or has tensile stress.
Said etching stop layer with compression is 300 nanometer to 400 nanometers with the thickness sum with barrier layer of tensile stress.
Adopt CMP technology said metallic copper to be polished to after the surface of dielectric layer, this method further comprises: at the superficial growth cobalt tungsten phosphide CoWP of metallic copper.
The thickness of said CoWP is 10 nanometer to 20 nanometers.
Based on metal interconnected method provided by the present invention,, in dielectric layer, form groove at first to the dielectric layer etching; Plated metal copper then; The metallic copper that is deposited is filled in the groove, and covers the dielectric layer surface, adopts CMP technology metallic copper to be polished to the surface of dielectric layer; Secondly on dielectric layer, form etching stop layer with compression; At last form the barrier layer with tensile stress on the etching stop layer of compression having, visible, the present invention has also increased the barrier layer with tensile stress having on the etching stop layer of compression; Have tensile stress the barrier layer can with in film deposition process since the high frequency power pressure that causes accumulating in grid discharge, thereby the influence of having avoided high frequency power that the integrality of gate oxide is caused.
Further; The present invention adopts CMP technology metallic copper to be polished to after the surface of dielectric layer; Also at the superficial growth cobalt tungsten phosphide of metallic copper; Cobalt tungsten phosphide covers the surface of metallic copper, and the ion on barrier metal copper surface moves to a certain extent, thereby has avoided the interfacial diffusion of metallic copper.
Description of drawings
Fig. 1～Fig. 3 is the process generalized section of metal interconnected method in the prior art.
Fig. 4 is the structural representation of HDP CVD device in the prior art.
Fig. 5 is the flow chart of metal interconnected method provided by the present invention.
Fig. 6～Figure 10 is the process generalized section of metal interconnected method embodiment provided by the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, scheme according to the invention is done to specify further.
Record according to " 2004IEEE International Conference on Integrated Circuit Design andTechnology " 119-122 page or leaf; High frequency power can produce thermal stress; The thermal stress that is produced can act on grid, thereby gathers because the pressure that thermal stress causes at grid.Therefore; Core concept of the present invention is: according to above-mentioned document record; Bigger high frequency power can cause gathering more pressure at grid, and this might be the major reason that influences the integrality of gate oxide, and the present invention has increased the barrier layer with tensile stress; Can the pressure that cause owing to high frequency power accumulating in grid be discharged, thereby avoid the integrality of gate oxide is impacted.
Fig. 5 is the flow chart of metal interconnected method provided by the present invention, and is as shown in Figure 5, and this method comprises:
Step 1 is carried out etching to dielectric layer, in dielectric layer, forms groove.
So far, this flow process finishes.
Fig. 6～Figure 10 is the process generalized section of metal interconnected method embodiment provided by the present invention.This embodiment mainly comprises the steps:
Step 2001 referring to Fig. 6, is carried out etching to dielectric layer 101, in dielectric layer 101, forms groove.
Step 2002, referring to Fig. 7, plated metal copper 102, the metallic copper that is deposited is filled in the groove shown in Figure 6, and covers dielectric layer 101 surfaces, adopts CMP technology that metallic copper 102 is polished then, metallic copper 102 is polished to the surface of dielectric layer 101.
Above-mentioned steps 2001 is identical with prior art with 2002, will not give unnecessary details here, can be with reference to the relevant introduction of prior art.
Step 2003 is referring to Fig. 8, at the superficial growth cobalt tungsten phosphide (CoWP) 201 of metallic copper 102.
Need to prove that CoWP is a kind of alloy, it only can be grown in metallic surface, and therefore, in this step, CoWP 201 only can grow in the surface of metallic copper 102, and CoWP 201 can not grow on the surface of dielectric layer 101.
In addition, in practical application, the thickness of CoWP 201 can not be excessive, and preferably, the thickness of CoWP 201 (be between the upper surface of upper surface and dielectric layer 101 of CoWP 201 among Fig. 8 apart from d) is 10 nanometer to 20 nanometers.
Step 2004 referring to Fig. 9, forms the etching stop layer 103 with compression on dielectric layer 101.
Form etching stop layer 103 method can for: adopt HDP CVD technology on dielectric layer 101, to deposit SiCN with compression.
Step 2005 referring to Figure 10, forms the barrier layer 202 with tensile stress (tensile stress) on the etching stop layer with compression 103.
Formation have tensile stress barrier layer 202 method can for: adopt HDP CVD technology on the etching stop layer with compression 103, to deposit barrier layer 202 with tensile stress.
Have tensile stress barrier layer 202 can for: have the SiCN of tensile stress or have the silicon nitride (SiN) of tensile stress.
Wherein, Have the etching stop layer 103 of compression and have the barrier layer 202 of tensile stress the thickness sum (be have among Figure 10 tensile stress barrier layer 202 upper surface and have the distance B between the lower surface of etching stop layer 103 of compression) should with prior art in to have an etching stopping layer thickness of compression roughly the same; Preferably, the value of D is 300 nanometer to 400 nanometers.
It is thus clear that; This step is compared with prior art significantly different; This step has also increased the barrier layer 202 with tensile stress on the etching stop layer with compression 103; Can the pressure that cause owing to high frequency power accumulating in grid be discharged, thereby avoid the integrality of gate oxide is impacted.
Need to prove; The pressure that said high frequency power causes accumulating in grid not only comes from deposition-etch and stops layer 103, also comes from deposited barrier layer 202, that is to say; Every HDP CVD technology that relates to all can be owing to big high frequency power causes the build pressure at grid.
But; Analysis by to prior art can be known; Why expect that etching stop layer 103 of the prior art possesses compression; Be because the etching stop layer 103 with compression can apply certain pressure to the metallic copper in the groove 102, cause the interfacial diffusion of metallic copper to prevent metallic copper from electromigration taking place under the effect of electric field outside.And that has offset on the barrier layer 202 that has tensile stress in this step is above-mentioned to metallic copper 102 applied pressures; In order to overcome this defective; CoWP201 has grown in above-mentioned steps 2003; CoWP 201 covers the surface of metallic copper 102, and the ion on barrier metal copper 102 surfaces moves to a certain extent, thereby has avoided the interfacial diffusion of metallic copper.
So far, this flow process finishes.
To sum up, based on technical scheme provided by the present invention, at first to the dielectric layer etching; In dielectric layer, form groove, plated metal copper then, the metallic copper that is deposited is filled in the groove; And cover the dielectric layer surface; Adopt CMP technology that metallic copper is polished to the surface of dielectric layer, secondly on dielectric layer, form etching stop layer, form barrier layer on the etching stop layer of compression having at last with tensile stress with compression; It is thus clear that; The present invention has also increased the barrier layer with tensile stress having on the etching stop layer of compression, have tensile stress the barrier layer can with in film deposition process since pressure that high frequency power causes accumulating in grid discharge, thereby the influence of having avoided high frequency power that the integrality of gate oxide is caused.
Further; The present invention adopts CMP technology metallic copper to be polished to after the surface of dielectric layer; Also at the superficial growth cobalt tungsten phosphide of metallic copper; Cobalt tungsten phosphide covers the surface of metallic copper, and the ion on barrier metal copper surface moves to a certain extent, thereby has avoided the interfacial diffusion of metallic copper.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. metal interconnected method, this method comprises:
To the dielectric layer etching, in said dielectric layer, form groove;
Plated metal copper, the metallic copper that is deposited is filled in the said groove, and covers said dielectric layer surface, adopts cmp CMP technology said metallic copper to be polished to the surface of dielectric layer then;
On said dielectric layer, form etching stop layer with compression;
On said etching stop layer with compression, form barrier layer with tensile stress.
2. method according to claim 1 is characterized in that, said etching stop layer with compression is: the fire sand SiCN with compression;
The method that then said formation has the etching stop layer of compression is: adopt high density plasma CVD HDP CVD technology on dielectric layer, to deposit the SiCN with compression.
3. method according to claim 1 is characterized in that, said barrier layer with tensile stress is: have the fire sand SiCN of tensile stress or have the silicon nitride SiN of tensile stress;
Then said formation have tensile stress the barrier layer method can for: adopt density plasma chemical vapour deposition (CVD) HDP CVD technology having the SiN that deposition on the etching stop layer of compression has the SiCN of tensile stress or has tensile stress.
4. method according to claim 1 is characterized in that, said etching stop layer with compression is 300 nanometer to 400 nanometers with the thickness sum with barrier layer of tensile stress.
5. method according to claim 1 is characterized in that, adopts CMP technology said metallic copper to be polished to after the surface of dielectric layer, and this method further comprises: at the superficial growth cobalt tungsten phosphide CoWP of metallic copper.
6. method according to claim 5 is characterized in that,
The thickness of said CoWP is 10 nanometer to 20 nanometers.
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| CN2011101050697A CN102760684A (en) | 2011-04-26 | 2011-04-26 | Metal interconnection method |
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| CN2011101050697A CN102760684A (en) | 2011-04-26 | 2011-04-26 | Metal interconnection method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106463396A (en) * | 2014-02-05 | 2017-02-22 | 应用材料公司 | Dielectric/metal barrier integration to prevent copper diffusion |
| CN113539952A (en) * | 2021-06-29 | 2021-10-22 | 上海华力集成电路制造有限公司 | Process control method for copper CMP |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2003007368A2 (en) * | 2001-07-12 | 2003-01-23 | Advanced Micro Devices, Inc. | Method of forming nitride capped cu lines with reduced electromigration along the cu/nitride interface |
| CN1716589A (en) * | 2004-06-18 | 2006-01-04 | 株式会社瑞萨科技 | Semiconductor device |
| CN1819179A (en) * | 2005-02-10 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN1835206A (en) * | 2005-02-05 | 2006-09-20 | 三星电子株式会社 | Method of forming double-setting line arrange for semiconductor device using protective access cover layer |
-
2011
- 2011-04-26 CN CN2011101050697A patent/CN102760684A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007368A2 (en) * | 2001-07-12 | 2003-01-23 | Advanced Micro Devices, Inc. | Method of forming nitride capped cu lines with reduced electromigration along the cu/nitride interface |
| CN1716589A (en) * | 2004-06-18 | 2006-01-04 | 株式会社瑞萨科技 | Semiconductor device |
| CN1835206A (en) * | 2005-02-05 | 2006-09-20 | 三星电子株式会社 | Method of forming double-setting line arrange for semiconductor device using protective access cover layer |
| CN1819179A (en) * | 2005-02-10 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106463396A (en) * | 2014-02-05 | 2017-02-22 | 应用材料公司 | Dielectric/metal barrier integration to prevent copper diffusion |
| CN106463396B (en) * | 2014-02-05 | 2020-03-10 | 应用材料公司 | Dielectric/metal barrier integration to prevent copper diffusion |
| CN113539952A (en) * | 2021-06-29 | 2021-10-22 | 上海华力集成电路制造有限公司 | Process control method for copper CMP |
| CN113539952B (en) * | 2021-06-29 | 2024-04-30 | 上海华力集成电路制造有限公司 | Process control method for copper CMP |
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