CN102752223B - Method for transmitting data among parallel systems and system of method - Google Patents
Method for transmitting data among parallel systems and system of method Download PDFInfo
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- CN102752223B CN102752223B CN201210261307.8A CN201210261307A CN102752223B CN 102752223 B CN102752223 B CN 102752223B CN 201210261307 A CN201210261307 A CN 201210261307A CN 102752223 B CN102752223 B CN 102752223B
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Abstract
The invention relates to the field of computers and communications and discloses a method for transmitting data among parallel systems and a system of the method. According to the method for transmitting the data among the parallel systems, a plurality of the parallel systems are connected with one another through a peripheral component interconnect express (PCIe) bus, each of the parallel systems establishes a buffer area descriptor and a receiving buffer area for other systems, data are transmitted to the corresponding receiving buffer area in a receiving system, information in the buffer area descriptor is set and read by the receiving system, a bottom network can be established in the plurality of the parallel systems, and free data transmission among the systems can be achieved. A reading position and a writing position are correspondingly arranged in a sending descriptor of a sending system and a receiving descriptor of the receiving system, the sending system updates the writing position in the receiving system through the PCIe bus, the receiving system updates the reading position in the sending system through the PCIe bus, and the reading position and the writing position in the descriptors are not required to be updated fully by the local system. Time required for data transmission can be further shortened.
Description
Technical field
The present invention relates to computer and the communications field, particularly data transmission technology between parallel system.
Background technology
In the Chinese patent that is 02110763.7 at application number, disclose a kind ofly based on polyprocessor virtual network card system and communication means thereof, by the communicator between a network interface card, master processor, processor and a plurality of other processing mechanism, built up whole virtual network card system; External data bag passes through the communication drivers module of network interface card, network interface card driver module, master processor, and is distributed to object processor according to the destination address of packet; The network protocol stack of processor by the data transaction of upper layer application part become packet to pass through the communicator between communication drivers module, processor, communication drivers module, network interface card driver module and the network interface card of master processor sends to outside.
The present inventor's discovery, prior art is mainly deposited problem in the following areas:
1, in prior art, use pci bus to carry out the mutual of data, during pci bus transmission, use parallel bus mode, parallel transmission is vulnerable to external disturbance, and need to from end system, share bandwidth, the limited speed of Internet Transmission with other.
2,, in prior art, main side system can forward the data to from end system according to destination address after receiving data, from end system, also can transfer data to main side system.But data can only be transmitted in main side system with between end system, from cannot freely transmitting data between end system.
3, in prior art, while realizing with PERCOM peripheral communication, Network card setup need to be become to promiscuous mode, when packet is too much in network, can impact the performance of main side system, particularly in the system of resource anxiety.
4, in prior art, use main side system maintenance whole system network configuration information, can obviously find out the importance of main side system, if work as machine in the system running of main side, other cannot communicate from end system so.
5, in prior art, the MAC from end system need to be exposed to outer net by main side network interface card, may cause address conflict problem.
Summary of the invention
The object of the present invention is to provide data transmission method and system thereof between a kind of parallel system, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.
For solving the problems of the technologies described above, embodiments of the present invention disclose data transmission method between a kind of parallel system, and N parallel system, connects with PCIe bus between each system, and N is greater than 1 integer;
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system;
Method comprises the following steps:
The first system by data by PCIe bus transfer in second system corresponding to the reception buffer zone of the first system; Wherein the first system and second system are two systems arbitrarily in the parallel system of N;
The first system writes in second system the buffer descriptor corresponding to the first system by indicating newly to the information of data;
Second system is according to corresponding to the information in the buffer descriptor of the first system, reading out data from the reception buffer zone corresponding to the first system.
Embodiments of the present invention also disclose data transmission system between a kind of parallel system, comprising: N parallel system, between each system, with PCIe bus, connect, and N is greater than 1 integer;
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system; Each system comprises:
Data transmission unit, for by data by PCIe bus transfer to recipient's system the reception buffer zone corresponding to native system;
Buffering area writing unit, for indicating that the new information to data writes recipient's system corresponding to the buffer descriptor of native system;
Data-reading unit, the information for basis corresponding to the buffer description of transmit leg system, reading out data from the reception buffer zone corresponding to transmit leg system.
Compared with prior art, the main distinction and effect thereof are embodiment of the present invention:
By PCIe bus, connect a plurality of parallel systems, each system is built respectively a buffer descriptor and reception buffer zone for each other system, data are passed to corresponding reception buffer zone in receiving system, and the information in buffer descriptor is set, etc. receiving system, read, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On upper strata (as application layer), above-mentioned fabric is equal to a Microsoft Loopback Adapter, and how communicate by letter between each parallel system without considering on upper strata, as long as using a Microsoft Loopback Adapter, data are by this Microsoft Loopback Adapter sending and receiving, simply handy.
Further, in the transmission descriptor of transmitting system (the first system) and the reception descriptor of receiving system (second system), corresponding reading location and writing position are set, by transmitting system, by PCIe bus, upgrade the writing position in receiving system, by receiving system, by PCIe bus, upgrade the reading location in transmitting system, rather than the reading location in descriptor and writing position are upgraded by local system entirely, can further shorten the required time of transfer of data flow process.Because the present inventor finds in practice, writing of PCIe bus is that POST(submits to) type operation, and to read be the non-submission of NONPOST() type operation, write operation will be obviously faster than read operation comparatively speaking, so by two pairs of reading and writing positions are set, by opposite end, write local terminal and read, rather than directly go to opposite end to read, can obviously save the operating time.
Further, in each system, retain the interrupt number of N the overall situation, the corresponding N of a difference system, transmitting system is notified receiving system with interrupt mode, and receiving system is determined transmitting system with interrupt number, can realize efficiently the notice after transfer of data.
Further, use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of data transmission method between a kind of parallel system in first embodiment of the invention;
Fig. 2 is the structural representation of a kind of parallel system in first embodiment of the invention;
Fig. 3 is the structural representation of a kind of shared buffer of parallel system in first embodiment of the invention;
Fig. 4 is the schematic flow sheet of data transmission method between a kind of parallel system in second embodiment of the invention;
Fig. 5 is the schematic diagram of a kind of transmission-buffering area-reception in second embodiment of the invention;
Fig. 6 is the working method schematic diagram of a kind of buffer circle in second embodiment of the invention;
Fig. 7 is the transmitting-receiving procedure chart of two inter-system datas in a kind of parallel system in second embodiment of the invention;
Fig. 8 is the initialized schematic flow sheet of a kind of Microsoft Loopback Adapter in second embodiment of the invention;
Fig. 9 is the schematic flow sheet of a kind of data transmission procedure in second embodiment of the invention;
Figure 10 is the schematic flow sheet of a kind of DRP data reception process in second embodiment of the invention;
Figure 11 is the structural representation of data transmission system between a kind of parallel system in third embodiment of the invention.
Embodiment
In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following execution mode and modification, also can realize each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to data transmission method between a kind of parallel system.Fig. 1 is the schematic flow sheet of data transmission method between this parallel system.
Between this parallel system, data transmission method is applicable to N parallel system, between each system, with PCIe bus, connects, and N is greater than 1 integer.
Parallel system: refer to a plurality of in the running operating system of synchronization.
Fig. 2 is a kind of structural representation of parallel system.In parallel system as shown in Figure 2,4 operating systems that parallel running that coexisting, similarly more system can be expanded and be obtained by PCIe bridge, and implementation procedure is all identical.
PCIe bus: full name is PCI Express, is bus interface of new generation, is developed at first by Intel.Support point-to-point serial link, each system all has the private link of oneself, does not need to bus request bandwidth, transfer rate can be brought up to very high frequency.
When N parallel system starts, comprise the following steps:
One in N parallel system as main system, other system is done from system, and main system is completed the guiding from system is started by PCIe bus, and the PCIe mapping relations of being set up by main system in guiding start-up course remain unchanged.
As shown in Figure 2, in the system that success starts, in root complex (Root Complex is called for short " RC ") and three terminals (End Point is called for short " EP "), moving different operating system simultaneously.
During startup, main system is completed the guiding from system (this technology Zheng our company Patent Application) is started by PCIe bus, when main system is when moving completely from system, has just formed 4 operating systems that in Fig. 2, parallel running.The PCIe mapping relations of being set up by main system in guiding start-up course remain unchanged, i.e. the system of each directed startup remains unchanged in the address in PCIe bus territory.
In this application, use PCIe bus to carry out data interaction, PCIe bus has many good qualities.First, PCIe bus makes can directly mutually communicating to connect from system of whole system inside, and does not need the participation of main system, that is to say and uses PCIe bus can realize inner point-to-point communication connection.Secondly, PCIe adopts universal serial bus mode, and PCIe point to point connect is occupied bandwidth separately.Moreover the bandwidth of PCIe is higher, the speed that realizes Internet Transmission can reach 345Mbps, and now Bandwidth-Constrained is in the performance of processor.
In this application, each has the network system of oneself from system, can separate configurations, if work as machine in main system running, on other from the communication of system without impact.And, do not need the MAC from system to be exposed to outer net by main side network interface card, can not cause the address conflict problem that may cause.
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system.
After system has started, set up shared buffer sound zone system.Shared buffer sound zone system is a slice contiguous memory, comprising two parts content: first is buffer descriptor, is mainly used to data of description and receives, sends the position of buffering area and current state; Second portion is reception buffer zone, is mainly used to the network packet that storage is sent by other system.In each system, for each other system is set up respectively a buffer descriptor and a reception buffer zone with store data, in the N for a parallel running in theory operating system, need to distribute N-1 buffer descriptor and N-1 reception buffer zone.In the present embodiment, for unified programming, can distribute N buffer descriptor and N reception buffer zone, only to n system, n buffer descriptor and n reception buffer zone are not used, the n is here more than or equal to 1, and is less than or equal to the integer of N, and all system numberings and buffering area numbering are all since 1.Fig. 3 is the shared buffer structural representation of the parallel system shown in Fig. 2.
As shown in Figure 3,
Buffering area starts: refer to the position that in all systems, buffering area starts, and corresponding actual physical internal memory, and be local device internal memory.
Buffer descriptor: storing two kinds of descriptors here, receiving descriptor and send descriptor.Receive physical address and state that descriptor has indicated reception buffer zone; Send buffer descriptor and indicated physical address and the state that sends buffering area, the physical address that sends buffering area is positioned at PCIe address space, and non-local internal memory.Each system all can be assigned with a this data structure in each other system, to realize reception and the transmission of data.Suppose the system and No. 2 system communication that are numbered 1, so, in system 1 and system 2, all can be distributed a this descriptor by the other side, by this descriptor, just can realize reception and the transmission of data.
Reception buffer zone: this region is mainly used to realize the reception of data, all data are all directly sent in reception buffer zone in the present embodiment, send buffer address and are corresponding reception buffer zone; Preferably, in present embodiment, buffer circle pattern is used in the management of buffering area.A buffering area correspondence two buffer descriptors, and one is mainly used to describe accepting state in this locality, and another is positioned at long-range (PCIe space), is mainly used to describe transmission state.In buffering area, each cell size is defined as 1536Bytes, and in present embodiment, its total size of temporary transient definition is 96KB, and its total size can be determined according to actual needs.
Specifically, as shown in Figure 1, between this parallel system, data transmission method comprises the following steps:
In step 101, the first system by data by PCIe bus transfer in second system corresponding to the reception buffer zone of the first system.Wherein the first system and second system are two systems arbitrarily in the parallel system of N.
After this enter step 102, the first system writes in second system the buffer descriptor corresponding to the first system by indicating newly to the information of data.
After this enter step 103, second system is according to corresponding to the information in the buffer descriptor of the first system, reading out data from the reception buffer zone corresponding to the first system.
After this process ends.
By PCIe bus, connect a plurality of parallel systems, each system is built respectively a buffer descriptor and reception buffer zone for each other system, data are passed to corresponding reception buffer zone in receiving system, and the information in buffer descriptor is set, etc. receiving system, read, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On upper strata (as application layer), above-mentioned fabric is equal to a Microsoft Loopback Adapter, and how communicate by letter between each parallel system without considering on upper strata, as long as using a Microsoft Loopback Adapter, data are by this Microsoft Loopback Adapter sending and receiving, simply handy.
Second embodiment of the invention relates to data transmission method between a kind of parallel system.Fig. 4 is the schematic flow sheet of data transmission method between this parallel system.
The second execution mode improves on the basis of the first execution mode, and main improvements are:
Each buffer descriptor comprises reception descriptor and sends descriptor, receives in descriptor and transmission descriptor and includes writing position and reading location.
The first system will indicate that newly the step writing in second system corresponding to the buffer descriptor of the first system to the information of data comprises following sub-step:
The first system is revised the value of putting corresponding to the transmission write bit in a descriptor of second system in the first system.
The first system is revised the value of putting corresponding to the reception write bit in a descriptor of the first system in second system by PCIe bus.
Second system basis is corresponding to the information in the buffer descriptor of the first system, and from the reception buffer zone corresponding to the first system, the step of reading out data comprises following sub-step:
Second system judge in second system, corresponding to the reception write bit in a descriptor of the first system, put whether identical with reading location, if different, to reading out data in the reception buffer zone corresponding to the first system.
Second system is revised in second system the value corresponding to the reading location of the reception descriptor of the first system.
Second system is revised in the first system the value corresponding to the reading location of the transmission descriptor of second system by PCIe bus.
In addition, be appreciated that in the first system corresponding to reading location and writing position in the transmission descriptor of second system should correspondent equal in second system corresponding to reading location and writing position in the reception descriptor of the first system.
Specifically, as shown in Figure 4,
In step 401, the first system by data by PCIe bus transfer in second system corresponding to the reception buffer zone of the first system.
This step is the step 101 in the first execution mode.
After this enter step 402, the first system is revised the value of putting corresponding to the transmission write bit in a descriptor of second system in the first system.
After this enter step 403, the first system is revised the value of putting corresponding to the reception write bit in a descriptor of the first system in second system by PCIe bus.
After this enter step 404, second system judge in second system, corresponding to the reception write bit in a descriptor of the first system, put whether identical with reading location.
If so, process ends; If not, enter step 405.
In step 405, second system is to reading out data in the reception buffer zone corresponding to the first system.
After this enter step 406, second system is revised in second system the value corresponding to the reading location of the reception descriptor of the first system.
After this enter step 407, second system is revised in the first system the value corresponding to the reading location of the transmission descriptor of second system by PCIe bus.
After this again get back to step 404.
In the present embodiment, preferably, the way to manage of buffering area is buffer circle pattern, and by sender and writer, jointly managed, sender is to buffering area data writing, and revises two writing positions in buffer management, one is positioned at sender above, and one is positioned on recipient; Recipient therefrom takes out data, and revises two reading locations in buffer management, and one is positioned at recipient above, and one is positioned on sender.Fig. 5 is the schematic diagram of a kind of transmission-buffering area-reception.
Buffering area is a fifo queue.Sender writes buffering area by information; Recipient takes information away from buffering area.Sender need to carry out the coordination of information and synchronize with recipient, and this is to complete by the position that reads or writes in two buffer managements of modification above.Fig. 6 is a kind of working method schematic diagram of buffer circle.
In the transmission descriptor of transmitting system (the first system) and the reception descriptor of receiving system (second system), corresponding reading location and writing position are set, by transmitting system, by PCIe bus, upgrade the writing position in receiving system, by receiving system, by PCIe bus, upgrade the reading location in transmitting system, rather than the reading location in descriptor and writing position are upgraded by local system entirely, can further shorten the required time of transfer of data flow process.Because the present inventor finds in practice, writing of PCIe bus is that POST(submits to) type operation, and to read be the non-submission of NONPOST() type operation, write operation will be obviously faster than read operation comparatively speaking, so by two pairs of reading and writing positions are set, by opposite end, write local terminal and read, rather than directly go to opposite end to read, can obviously save the operating time.
The interrupt number that retains N the overall situation in N parallel system, respectively a corresponding N system.
The first system is further comprising the steps of by indicating newly after the information of data writes in second system the step corresponding to the buffer descriptor of the first system:
The first system triggers interrupt number corresponding to the first system to second system.
Second system is had no progeny in receiving, and determines that the system of this interruption of triggering is the first system according to the interrupt number of this interruption.
The interrupt number that retains N the overall situation in each system, the corresponding N of a difference system, the system that the system of transmission receives with interrupt mode notice, the system of reception is determined the system sending with interrupt number, can realize efficiently the notice after transfer of data.
In addition, be appreciated that in some other examples of the present invention, also can by the mode of interrupting, do not notify, for example, can use the mode of recipient's poll.Also can not be the interrupt number of each system assignment overall situation, but adopt alternate manner, for example, can be only with an interrupt number, the system that receives interruption knows it is which system triggers is interrupted by inquiring about certain sign.
In the present embodiment, preferably, interruption is that MSI interrupts.
Use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
In addition, be appreciated that in some other examples of the present invention, also can use in principle the interruption of other type, as PCI interruption, GPIO interruption etc.
After buffering area has been set up, while carrying out data transmission, need notification target to receive data.In the present embodiment, use to interrupt informing that target carries out the reception of data.For convenient management, the use of our unified interrupt number in whole parallel system.As supposed, No. 1 system is to interrupt for No. 136, and No. 2 systems are to interrupt for No. 137 ... the rest may be inferred.When No. 1 system is to No. 2 systems and No. 3 systems transmission data so, the own interrupt number distributing in whole system 136 that only need to set out is to No. 2 systems and No. 3 systems.Then No. 2 systems and No. 3 systems receive No. 136 interruptions, and then the system corresponding according to this interrupt number, processes corresponding reception buffer zone.
Fig. 7 is the transmitting-receiving procedure chart of No. 2 and No. 3 inter-system datas in the parallel system shown in Fig. 2.
As shown in Figure 7, band arrow dotted line is pointer, points to True Data position, supposes that No. 2 systems carry out the transmission of data to No. 3 systems.No. 2 system is received the packet that protocol stack is sent, and at the destination address that drives layer analysis packet, finds that destination address is No. 3 systems.Thereby from shared buffer, take out the descriptor of No. 3 systems, by sending the state of buffering area, judge whether buffering area exists remaining space.If there is available remaining space, find it to send buffer pointer and locus, data are copied to pointer assigned address.Reception write bit in a descriptor in this locality No. 2 systems of modification in No. 3 systems is put w, its value is revised as to No. 2 systems and to No. 3 systems transmission writes bit in a descriptor, puts w, and this step completes by rw_off pointer.Writing position w is a numerical value, if many bags in buffering area, just+1, writing position w is identical with reading location r, and just explanation does not have data, differently just illustrates and has data.Then the system break taking by No. 2 systems, as No. 137, sends interrupt signal to No. 3 systems.If there is not remaining space, stop the transmission of data.So far, the whole process that No. 2 systems send data to No. 3 systems finishes.Data transmission procedure between other system, all similar process therewith.
Present No. 3 systems by No. 2 system triggers interrupt for No. 137, No. 3 systems can know that now No. 2 systems have been sent data so.No. 3 system can be taken out the reception descriptor of No. 2 systems from the shared buffer descriptor of oneself, then by read and write position, be confirmed whether really have data to arrive, if confirm, there are data to arrive handle packet, according to the buffer location receiving in descriptor, receive data, and submit to the protocol stack of kernel, then in this locality, revise the reading location r of No. 3 systems transmission descriptor in No. 2 systems, its value is revised as to the reading location r of the reception descriptor of No. 2 systems of No. 3 system receptions, this step completes by rw_off pointer, if countless according to arrival, directly return.So far, the process that No. 2 systems of whole No. 3 systems reception are sent data completes.
To sum up, between whole parallel system, transfer of data comprises three processes: Microsoft Loopback Adapter initialization procedure, data transmission procedure and DRP data reception process.
Fig. 8 is the initialized schematic flow sheet of a kind of Microsoft Loopback Adapter.
Microsoft Loopback Adapter: refer to the function of carrying out analog hardware network interface card by software, thereby realize the technology communicating by network between several operating system.
By PCIe bus, connect a plurality of parallel systems, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On upper strata (as application layer), above-mentioned fabric is equal to a Microsoft Loopback Adapter, and how communicate by letter between each parallel system without considering on upper strata, as long as using a Microsoft Loopback Adapter, data are by this Microsoft Loopback Adapter sending and receiving, simply handy.
Specifically, as shown in Figure 8, the initialized process of this Microsoft Loopback Adapter comprises the following steps,
In step 801, registered network equipment and handling function collection thereof, comprise open, closing device, bag sends Han and Shuos Alto etc., registration NAPI function, obtains the numbering of local device in system.
After this enter step 802, allocation buffer descriptor, distributes reception buffer zone data.
After this enter step 803, distribution system interrupt resources number, is each operating system assigned interrupt resource in parallel system.
After this enter step 804, registration interrupts processing function.
After this process ends.
Fig. 9 is a kind of schematic flow sheet of data transmission procedure.Specifically, mainly comprise the following steps:
In step 901, protocol stack transmits transmission data.
After this enter step 902, extract destination address wherein.
After this enter step 903, judge whether this destination address can forward.
If so, enter step 904; If not, enter step 907.
In step 904, according to destination address, from buffer descriptor, extract and send buffer state.
After this enter step 905, according to sending buffer state, whether judgement sends buffering area full.
If so, enter step 908; If not, enter step 906.
In step 906, find and send buffer pointer and locus, data are copied to pointer assigned address.
After this process ends.
In step 907, directly abandon.After this process ends.
In step 908, wait to be sent or timeout treatment.After this process ends.
Figure 10 is a kind of schematic flow sheet of DRP data reception process.Specifically, mainly comprise the following steps:
In step 1001, enter interruption.
After this enter step 1002, close interruption, prevent that similar interruption from entering again, record interrupt status, wake network up and receive soft interruption.
After this enter step 1003, carry out the NAPI function of registration.
After this enter step 1004, according to interrupt status, obtain corresponding reception buffer zone descriptor, the reception buffer zone of processing its execution.
After this enter step 1005, reception buffer zone content is filled to network packet, be then committed to protocol stack.
After this enter step 1006, upgrade statistic behavior, the data of processing reception buffer zone reach certain condition backed off after random NAPI function, or complete backed off after random and remove interrupt status.
After this process ends.
Each method execution mode of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the memory of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, memory can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), read-only memory (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
Third embodiment of the invention relates to data transmission system between a kind of parallel system.Figure 11 is the structural representation of data transmission system between this parallel system.
Specifically, as shown in figure 11,
Between this parallel system, data transmission system comprises: N parallel system, between each system, with PCIe bus, connect, and N is greater than 1 integer.
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system;
Each system comprises:
Data transmission unit, for by data by PCIe bus transfer to recipient's system the reception buffer zone corresponding to native system;
Buffering area writing unit, for indicating that the new information to data writes recipient's system corresponding to the buffer descriptor of native system;
Data-reading unit, the information for basis corresponding to the buffer description of transmit leg system, reading out data from the reception buffer zone corresponding to transmit leg system.
On upper strata (as application layer), between above-mentioned parallel system, data transmission system is equal to a Microsoft Loopback Adapter, and how communicate by letter between each parallel system without considering on upper strata, as long as using a Microsoft Loopback Adapter, data are by this Microsoft Loopback Adapter sending and receiving, simply handy.
Here, it should be noted that, recipient's system refers to the transmission object of native system data, and transmit leg system refers to that system that sends the data to native system.
In addition, in described N parallel system, one is main system, and other system is from system;
Described main system for being completed the guiding from system started by PCIe bus when described N parallel system starts;
The PCIe mapping relations of being set up by main system in guiding start-up course remain unchanged.
The first execution mode is the method execution mode corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the first execution mode.The correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
Four embodiment of the invention relates to data transmission system between a kind of parallel system.
The 4th execution mode improves on the basis of the 3rd execution mode, and main improvements are:
Each buffer descriptor comprises reception descriptor and sends descriptor, receives in descriptor and transmission descriptor and includes writing position and reading location.
Described buffering area writing unit comprises following subelement:
Writing position first is revised subelement, the value of putting corresponding to the transmission write bit in a descriptor of recipient's system for revising native system;
Writing position second is revised subelement, for revising by PCIe bus the value that recipient's system is put corresponding to the reception write bit in a descriptor of native system;
Described data-reading unit comprises following subelement:
Judgment sub-unit, for judging that native system puts whether identical with reading location corresponding to the reception write bit in a descriptor of transmit leg system;
Read subelement, for putting when different from reading location corresponding to the reception write bit in a descriptor of transmit leg system at described judgment sub-unit judgement native system, to reading out data in the reception buffer zone corresponding to transmit leg system;
Reading location first is revised subelement, for revising native system corresponding to the value of the reading location of the reception descriptor of transmit leg system;
Reading location second is revised subelement, for revising transmit leg system corresponding to the value of the reading location of the transmission descriptor of native system by PCIe bus.
The interrupt number that retains N the overall situation in N parallel system, respectively a corresponding N system.
In each system, also comprise:
Trigger element, for triggering interrupt number corresponding to native system to recipient's system;
Determining unit, for having no progeny receiving, determines the transmit leg system that triggers this interruption according to the interrupt number of this interruption.
In the present embodiment, preferably, interruption is that MSI interrupts.
Use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
In addition, be appreciated that in some other examples of the present invention, also can use in principle the interruption of other type, as PCI interruption, GPIO interruption etc.
The second execution mode is the method execution mode corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the second execution mode.The correlation technique details of mentioning in the second execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second execution mode.
It should be noted that, each unit of mentioning in each System Implementation mode of the present invention is all logical block, physically, a logical block can be a physical location, also can be a part for a physical location, can also realize with the combination of a plurality of physical locations, the physics realization mode of these logical blocks itself is not most important, and the combination of the function that these logical blocks realize is only the key that solves technical problem proposed by the invention.In addition, for outstanding innovation part of the present invention, above-mentioned each System Implementation mode of the present invention is not introduced the unit not too close with solving technical problem relation proposed by the invention, and this does not show that the said equipment execution mode does not exist other unit.
It should be noted that, in the claim and specification of this patent, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element that " comprises " and limit by statement, and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and described, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (8)
1. a data transmission method between parallel system, is characterized in that, N parallel system, connects with PCIe bus between each system, and N is greater than 1 integer;
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system;
Said method comprising the steps of:
The first system by data by PCIe bus transfer in second system corresponding to the reception buffer zone of the first system; Wherein said the first system and second system are two systems arbitrarily in the parallel system of described N;
The first system writes in second system the buffer descriptor corresponding to the first system by indicating newly to the information of data;
Second system is according to corresponding to the information in the buffer descriptor of the first system, reading out data from the reception buffer zone corresponding to the first system;
Each buffer descriptor comprises reception descriptor and sends descriptor, receives in descriptor and transmission descriptor and includes writing position and reading location;
Described the first system will indicate that newly the step writing in second system corresponding to the buffer descriptor of the first system to the information of data comprises following sub-step:
The first system is revised the value of putting corresponding to the transmission write bit in a descriptor of second system in the first system;
The first system is revised the value of putting corresponding to the reception write bit in a descriptor of the first system in second system by PCIe bus;
Described second system basis is corresponding to the information in the buffer descriptor of the first system, and from the reception buffer zone corresponding to the first system, the step of reading out data comprises following sub-step:
Second system judge in second system, corresponding to the reception write bit in a descriptor of the first system, put whether identical with reading location, if different, to reading out data in the reception buffer zone corresponding to the first system;
Second system is revised in second system the value corresponding to the reading location of the reception descriptor of the first system;
Second system is revised in the first system the value corresponding to the reading location of the transmission descriptor of second system by PCIe bus.
2. data transmission method between parallel system according to claim 1, is characterized in that, retains the interrupt number of N the overall situation, respectively a corresponding N system in described N parallel system;
Described the first system is further comprising the steps of by indicating newly after the information of data writes in second system the step corresponding to the buffer descriptor of the first system:
The first system triggers interrupt number corresponding to the first system to second system;
Second system is had no progeny in receiving, and determines that the system of this interruption of triggering is the first system according to the interrupt number of this interruption.
3. data transmission method between parallel system according to claim 2, is characterized in that, described interruption is that MSI interrupts.
4. data transmission method between parallel system according to claim 1, is characterized in that, when described N parallel system starts, further comprising the steps of:
One in described N parallel system as main system, other system is done from system, and main system is completed the guiding from system is started by PCIe bus, and the PCIe mapping relations of being set up by main system in guiding start-up course remain unchanged.
5. a data transmission system between parallel system, is characterized in that, comprising: N parallel system, between each system, with PCIe bus, connect, and N is greater than 1 integer;
In each system, at least comprise N-1 buffer descriptor and N-1 reception buffer zone, respectively corresponding other N-1 system; Each system comprises:
Data transmission unit, for by data by PCIe bus transfer to recipient's system the reception buffer zone corresponding to native system;
Buffering area writing unit, for indicating that the new information to data writes recipient's system corresponding to the buffer descriptor of native system;
Data-reading unit, the information for basis corresponding to the buffer description of transmit leg system, reading out data from the reception buffer zone corresponding to transmit leg system;
Each buffer descriptor comprises reception descriptor and sends descriptor, receives in descriptor and transmission descriptor and includes writing position and reading location;
Described buffering area writing unit comprises following subelement:
Writing position first is revised subelement, the value of putting corresponding to the transmission write bit in a descriptor of recipient's system for revising native system;
Writing position second is revised subelement, for revising by PCIe bus the value that recipient's system is put corresponding to the reception write bit in a descriptor of native system;
Described data-reading unit comprises following subelement:
Judgment sub-unit, for judging that native system puts whether identical with reading location corresponding to the reception write bit in a descriptor of transmit leg system;
Read subelement, for putting when different from reading location corresponding to the reception write bit in a descriptor of transmit leg system at described judgment sub-unit judgement native system, to reading out data in the reception buffer zone corresponding to transmit leg system;
Reading location first is revised subelement, for revising native system corresponding to the value of the reading location of the reception descriptor of transmit leg system;
Reading location second is revised subelement, for revising transmit leg system corresponding to the value of the reading location of the transmission descriptor of native system by PCIe bus.
6. data transmission system between parallel system according to claim 5, is characterized in that, retains the interrupt number of N the overall situation, respectively a corresponding N system in described N parallel system;
In each system, also comprise:
Trigger element, for triggering interrupt number corresponding to native system to recipient's system;
Determining unit, for having no progeny receiving, determines the transmit leg system that triggers this interruption according to the interrupt number of this interruption.
7. data transmission system between parallel system according to claim 6, is characterized in that, described interruption is that MSI interrupts.
8. data transmission system between parallel system according to claim 5, is characterized in that,
In described N parallel system, one is main system, and other system is from system;
Described main system for being completed the guiding from system started by PCIe bus when described N parallel system starts;
The PCIe mapping relations of being set up by main system in guiding start-up course remain unchanged.
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