CN102752223A - Method for transmitting data among parallel systems and system of method - Google Patents
Method for transmitting data among parallel systems and system of method Download PDFInfo
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- CN102752223A CN102752223A CN2012102613078A CN201210261307A CN102752223A CN 102752223 A CN102752223 A CN 102752223A CN 2012102613078 A CN2012102613078 A CN 2012102613078A CN 201210261307 A CN201210261307 A CN 201210261307A CN 102752223 A CN102752223 A CN 102752223A
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Abstract
The invention relates to the field of computers and communications and discloses a method for transmitting data among parallel systems and a system of the method. According to the method for transmitting the data among the parallel systems, a plurality of the parallel systems are connected with one another through a peripheral component interconnect express (PCIe) bus, each of the parallel systems establishes a buffer area descriptor and a receiving buffer area for other systems, data are transmitted to the corresponding receiving buffer area in a receiving system, information in the buffer area descriptor is set and read by the receiving system, a bottom network can be established in the plurality of the parallel systems, and free data transmission among the systems can be achieved. A reading position and a writing position are correspondingly arranged in a sending descriptor of a sending system and a receiving descriptor of the receiving system, the sending system updates the writing position in the receiving system through the PCIe bus, the receiving system updates the reading position in the sending system through the PCIe bus, and the reading position and the writing position in the descriptors are not required to be updated fully by the local system. Time required for data transmission can be further shortened.
Description
Technical field
The present invention relates to the computer and the communications field, particularly data transmission technology between parallel system.
Background technology
In application number is 02110763.7 Chinese patent; Disclose a kind ofly, built up whole virtual network card system through the communicator between a network interface card, master processor, the processor and a plurality of other processing mechanism based on polyprocessor virtual network card system and communication means thereof; The external data bag passes through the communication drivers module of network interface card, network interface card driver module, master processor, and is distributed to the purpose processor according to the destination address of packet; The network protocol stack of each processor converts the upper layer application partial data communication drivers module, network interface card driver module and the network interface card of packet through the communicator between communication drivers module, the processor, master processor to and sends to the outside.
Inventor of the present invention finds that mainly there is the problem of following aspect in prior art:
1, in the prior art, use pci bus to carry out the mutual of data, use the parallel bus mode during pci bus transmission, parallel transmission is vulnerable to external disturbance, and need with other from the end system shared bandwidth, the limited speed of Network Transmission.
2, in the prior art, main end system can forward the data to from end system according to destination address after receiving data, also can give main end system with transfer of data from end system.But data can only be transmitted at main end system with between the end system, from can't freely transmitting data between the end system.
3, in the prior art, when realizing, need network interface card be arranged to promiscuous mode, when packet is too much in the network, can the performance of main end system be impacted, particularly in the system of resource anxiety with PERCOM peripheral communication.
4, in the prior art, use main end system safeguard whole system network configuration information, can obviously find out the importance of main end system, if work as machine in the main end system running, other can't communicate from end system so.
5, in the prior art, need and to be exposed to outer net from the MAC of end system through main end network interface card, possibly cause the address conflict problem.
Summary of the invention
The object of the present invention is to provide data transmission method and system thereof between a kind of parallel system, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.
For solving the problems of the technologies described above, execution mode of the present invention discloses data transmission method between a kind of parallel system, and N parallel system connects with the PCIe bus between each system, and N is the integer greater than 1;
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system;
Method may further comprise the steps:
First system with data through PCIe bus transfer reception buffering area corresponding to first system in second system; Wherein first system and second system are two systems arbitrarily in the parallel system of N;
First system has newly expression to the information of data and writes in second system buffer descriptor corresponding to first system;
Second system is according to corresponding to the information in the buffer descriptor of first system, from corresponding to reading of data the reception buffering area of first system.
Execution mode of the present invention also discloses data transmission system between a kind of parallel system, comprising: N parallel system, connect with the PCIe bus between each system, and N is the integer greater than 1;
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system; Comprise in each system:
Data transmission unit is used for data are passed through the PCIe bus transfer to the reception buffering area of recipient system corresponding to native system;
The buffering area writing unit is used for having new information to data to write the buffer descriptor of recipient system corresponding to native system expression;
Data-reading unit is used for according to the information corresponding to the buffer description of transmit leg system, from corresponding to reading of data the reception buffering area of transmit leg system.
Embodiment of the present invention compared with prior art, the main distinction and effect thereof are:
Connect a plurality of parallel systems through the PCIe bus; Each system builds a buffer descriptor respectively and receives buffering area for each other system; Data are passed to corresponding reception buffering area in the receiving system, and the information in the buffer descriptor is set, read etc. receiving system; Can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On the upper strata (like application layer); Above-mentioned fabric is equal to a Microsoft Loopback Adapter, and the upper strata need not to consider how to communicate by letter between each parallel system, as long as as using a Microsoft Loopback Adapter; Data are got final product through this Microsoft Loopback Adapter transmission and reception, simply handy.
Further; Corresponding reading location and writing position are set in the reception descriptor of the transmission descriptor of transmitting system (first system) and receiving system (second system); Upgrade the writing position in the receiving system by transmitting system through the PCIe bus; Upgrade the reading location in the transmitting system by receiving system through the PCIe bus, rather than reading location in the descriptor and writing position are upgraded by local system entirely, can further shorten the required time of transfer of data flow process.Because inventor of the present invention finds in practice; Writing of PCIe bus is POST (submission) type operation, and to read be the operation of NONPOST (non-submission) type, and write operation will be obviously faster than read operation comparatively speaking; So through two pairs of reading and writing positions are set; Write local terminal by the opposite end and read, rather than directly go to the opposite end to read, obviously the save operation time.
Further, in each system, keep the interrupt number of N the overall situation, distinguish a corresponding N system, transmitting system is notified receiving system with interrupt mode, and receiving system is confirmed transmitting system with interrupt number, can realize the notice after the transfer of data efficiently.
Further, use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
Description of drawings
Fig. 1 is the schematic flow sheet of data transmission method between a kind of parallel system in the first embodiment of the invention;
Fig. 2 is the structural representation of a kind of parallel system in the first embodiment of the invention;
Fig. 3 is the structural representation of a kind of shared buffer of parallel system in the first embodiment of the invention;
Fig. 4 is the schematic flow sheet of data transmission method between a kind of parallel system in the second embodiment of the invention;
Fig. 5 is the sketch map of a kind of transmission-buffering area-reception in the second embodiment of the invention;
Fig. 6 is the working method sketch map of a kind of buffer circle in the second embodiment of the invention;
Fig. 7 is the transmitting-receiving procedure chart of two inter-system datas in a kind of parallel system in the second embodiment of the invention;
Fig. 8 is the initialized schematic flow sheet of a kind of Microsoft Loopback Adapter in the second embodiment of the invention;
Fig. 9 is the schematic flow sheet of a kind of data transmission procedure in the second embodiment of the invention;
Figure 10 is the schematic flow sheet of a kind of DRP data reception process in the second embodiment of the invention;
Figure 11 is the structural representation of data transmission system between a kind of parallel system in the third embodiment of the invention.
Embodiment
In following narration, many ins and outs have been proposed in order to make the reader understand the application better.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on the many variations and the modification of following each execution mode, also can realize each claim of the application technical scheme required for protection.
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that execution mode of the present invention is done to describe in detail further below.
First embodiment of the invention relates to data transmission method between a kind of parallel system.Fig. 1 is the schematic flow sheet of data transmission method between this parallel system.
Data transmission method is applicable to N parallel system between this parallel system, connects with the PCIe bus between each system, and N is the integer greater than 1.
Parallel system: refer to a plurality of in the running operating system of synchronization.
Fig. 2 is a kind of structural representation of parallel system.In the parallel system as shown in Figure 2,4 operating systems that parallel running that coexisting, similarly more system can expand through the PCIe bridge and obtain, and implementation procedure is all identical.
The PCIe bus: full name is PCI Express, is the EBI of a new generation, is developed by Intel at first.Support point-to-point serial link, all there is the private link of oneself in each system, need can not bring up to very high frequency to transfer rate to the bus request bandwidth.
When N system start-up that walks abreast, may further comprise the steps:
One in the individual system that walks abreast of N other system does from system as main system, and main system is accomplished the guiding startup from system through the PCIe bus, and the PCIe mapping relations of in guiding start-up course, being set up by main system remain unchanged.
As shown in Figure 2, in the system that success starts, on root complex (Root Complex is called for short " RC ") and three terminals (End Point is called for short " EP "), moving different operating systems simultaneously.
During startup, main system is accomplished starting from the guiding of system (this technology is just our company's patent application examination) through the PCIe bus, when main system with when system moves fully, just formed 4 operating systems that parallel running among Fig. 2.The PCIe mapping relations of in the guiding start-up course, being set up by main system remain unchanged, and promptly each system that is directed starting remains unchanged in the address in PCIe bus territory.
In this application, use the PCIe bus to carry out data interaction, the PCIe bus has many good qualities.At first, the PCIe bus connects inner can directly the communicating by letter each other from system of whole system, and does not need the participation of main system, that is to say and uses the PCIe bus can realize that inner point-to-point communication connects.Secondly, PCIe adopts the universal serial bus mode, and the point-to-point connection of PCIe is occupied bandwidth separately.Moreover the bandwidth of PCIe is higher, realizes that the speed of Network Transmission can reach 345Mbps, and this moment, limited bandwidth was in performance of processors.
In this application, each has oneself network system from system, but separate configurations if work as machine in the main system running, does not have influence to other communication from system.And, do not need and will be exposed to outer net through main end network interface card from the MAC of system, can not cause the address conflict problem that possibly cause.
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system.
System start-up is set up the shared buffer system after accomplishing.The shared buffer system is a slice contiguous memory, and comprising two parts content: first is a buffer descriptor, mainly is used for data of description to receive, send the position of buffering area and present state; Second portion mainly is used for storing the network packet of being sent by other system for receiving buffering area.In each system, receive buffering area with store data, in N the operating system of for parallel running in theory, only need to distribute N-1 buffer descriptor and N-1 reception buffering area for each other system sets up a buffer descriptor and one respectively.In this execution mode; For unified programming, can distribute N buffer descriptor and N reception buffering area, only to n system; N buffer descriptor and n receive buffering area and do not use; The n here is more than or equal to 1, and smaller or equal to the integer of N, all systems' numberings are numbered all since 1 with buffering area.Fig. 3 is the shared buffer structural representation of parallel system shown in Figure 2.
As shown in Figure 3,
Buffering area begins: be meant the position that buffering area begins in all systems, and corresponding actual physical internal memory, and be the local device internal memory.
Buffer descriptor: storing two kinds of descriptors here, receiving descriptor and send descriptor.Receive descriptor and indicated physical address and the state that receives buffering area; Send buffer descriptor and indicated physical address and the state that sends buffering area, the physical address that sends buffering area is positioned at the PCIe address space, but not local internal memory.Each system all can be assigned with a this data structure in each other system, to realize the reception and the transmission of data.Suppose to be numbered 1 system and No. 2 system communication, so, in system 1 and system 2, all can be distributed a this descriptor, just can realize the reception and the transmission of data through this descriptor by the other side.
Receive buffering area: this zone mainly is used for realizing the reception of data, and all data all directly are sent to and receive in the buffering area in this execution mode, and sending buffer address is corresponding reception buffering area; Preferably, in this execution mode, the buffer circle pattern is used in the management of buffering area.Buffering area corresponding two buffer descriptors, one in this locality, mainly is used for describing accepting state, another is positioned at long-range (PCIe space), mainly is used for describing transmit status.Each cell size is defined as 1536Bytes in the buffering area, and its total size of temporary transient definition is 96KB in this execution mode, and its total size can be confirmed according to actual needs.
Specifically, as shown in Figure 1, data transmission method may further comprise the steps between this parallel system:
In step 101, first system with data through PCIe bus transfer reception buffering area corresponding to first system in second system.Wherein first system and second system are two systems arbitrarily in the parallel system of N.
After this get into step 102, first system has newly expression to the information of data and writes in second system buffer descriptor corresponding to first system.
After this get into step 103, second system is according to corresponding to the information in the buffer descriptor of first system, from corresponding to reading of data the reception buffering area of first system.
After this process ends.
Connect a plurality of parallel systems through the PCIe bus; Each system builds a buffer descriptor respectively and receives buffering area for each other system; Data are passed to corresponding reception buffering area in the receiving system, and the information in the buffer descriptor is set, read etc. receiving system; Can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On the upper strata (like application layer); Above-mentioned fabric is equal to a Microsoft Loopback Adapter, and the upper strata need not to consider how to communicate by letter between each parallel system, as long as as using a Microsoft Loopback Adapter; Data are got final product through this Microsoft Loopback Adapter transmission and reception, simply handy.
Second embodiment of the invention relates to data transmission method between a kind of parallel system.Fig. 4 is the schematic flow sheet of data transmission method between this parallel system.
Second execution mode improves on the basis of first execution mode, and main improvements are:
Comprise in each buffer descriptor receiving descriptor and sending descriptor, receive descriptor and include writing position and reading location with sending in the descriptor.
First system has newly the step that writes in second system corresponding to the buffer descriptor of first system to the information of data comprise following substep expression:
The value of putting corresponding to the transmission write bit in a descriptor of second system in first system is revised by first system.
The value of putting corresponding to the reception write bit in a descriptor of first system in second system is revised by first system through the PCIe bus.
Second system basis comprises following substep corresponding to the information in the buffer descriptor of first system from the step corresponding to reading of data the reception buffering area of first system:
Second system judge put corresponding to the reception write bit in a descriptor of first system in second system whether identical with reading location, if different, then to corresponding to reading of data in the reception buffering area of first system.
The value corresponding to the reading location of the reception descriptor of first system is revised in second system by second system.
The value corresponding to the reading location of the transmission descriptor of second system is revised in first system through the PCIe bus by second system.
In addition, be appreciated that in first system corresponding to reading location and writing position in the transmission descriptor of second system should correspondent equal in second system corresponding to reading location and writing position in the reception descriptor of first system.
Specifically, as shown in Figure 4,
In step 401, first system with data through PCIe bus transfer reception buffering area corresponding to first system in second system.
This step is the step 101 in first execution mode.
After this get into step 402, the value of putting corresponding to the transmission write bit in a descriptor of second system in first system is revised by first system.
After this get into step 403, the value of putting corresponding to the reception write bit in a descriptor of first system in second system is revised by first system through the PCIe bus.
After this get into step 404, second system judge put corresponding to the reception write bit in a descriptor of first system in second system whether identical with reading location.
If, process ends then; If not, then get into step 405.
In step 405, second system is to corresponding to reading of data in the reception buffering area of first system.
After this get into step 406, the value corresponding to the reading location of the reception descriptor of first system is revised in second system by second system.
After this get into step 407, the value corresponding to the reading location of the transmission descriptor of second system is revised in first system through the PCIe bus by second system.
After this get back to step 404 once more.
In this execution mode, preferably, the way to manage of buffering area is the buffer circle pattern; And by sender and the person's of writing managed together, the sender writes data to buffering area, and revises two writing positions in the buffer management; One is positioned on the sender, and one is positioned on the recipient; The recipient therefrom takes out data, and revises two reading locations in the buffer management, and one is positioned on the recipient, and one is positioned on the sender.Fig. 5 is the sketch map of a kind of transmission-buffering area-reception.
Buffering area is a fifo queue.The sender writes buffering area with information; The recipient takes information away from buffering area.Sender and recipient need carry out the coordination of information with synchronously, and this is to accomplish through the position that reads or writes in two buffer managements of top modification.Fig. 6 is a kind of working method sketch map of buffer circle.
Corresponding reading location and writing position are set in the reception descriptor of the transmission descriptor of transmitting system (first system) and receiving system (second system); Upgrade the writing position in the receiving system by transmitting system through the PCIe bus; Upgrade the reading location in the transmitting system by receiving system through the PCIe bus; Rather than the reading location in the descriptor and writing position upgraded by local system entirely, can further shorten the required time of transfer of data flow process.Because inventor of the present invention finds in practice; Writing of PCIe bus is POST (submission) type operation, and to read be the operation of NONPOST (non-submission) type, and write operation will be obviously faster than read operation comparatively speaking; So through two pairs of reading and writing positions are set; Write local terminal by the opposite end and read, rather than directly go to the opposite end to read, obviously the save operation time.
The interrupt number that in N parallel system, keeps N the overall situation, a corresponding N system respectively.
First system has newly after the information of data writes in second system step corresponding to the buffer descriptor of first system expression further comprising the steps of:
First system triggers is given second system corresponding to the interrupt number of first system.
Have no progeny during second system receives, confirm that according to the interrupt number of this interruption the system of this interruption of triggering is first system.
The interrupt number that in each system, keeps N the overall situation, a corresponding N system respectively, the system that the system of transmission receives with the interrupt mode notice, the system of reception be with the system of the definite transmission of interrupt number, can realize the notice after the transfer of data efficiently.
In addition, be appreciated that in some other instance of the present invention, also can not use the mode of interruption to notify, for example can use the mode of recipient's poll.Also can not be the interrupt number of each system assignment overall situation, but adopt alternate manner, for example, can be only with an interrupt number, the system that receives interruption knows it is that which system triggers is interrupted through inquiring about certain sign.
In this execution mode, preferably, interruption is that MSI interrupts.
Use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
In addition, be appreciated that and in some other instance of the present invention, also can use the interruption of other type in principle, interrupt like PCI interruption, GPIO etc.
After buffering area is set up and accomplished, when carrying out the data transmission, need notification target to receive data.In this execution mode, use to interrupt informing that target carries out the reception of data.Management for ease, the use of our unified interrupt number in whole parallel system.As suppose that No. 1 system is No. 136 interruptions, No. 2 systems are No. 137 interruptions ... The rest may be inferred.No. 1 system is when No. 2 systems and No. 3 systems send data so, and the own interrupt number that in whole system, distributes 136 that only need set out gets final product for No. 2 systems and No. 3 systems.Then No. 2 systems and No. 3 systems receive No. 136 interruptions, and corresponding according to this interrupt number then system handles the corresponding buffering area that receives and gets final product.
Fig. 7 is the transmitting-receiving procedure chart of No. 2 and No. 3 inter-system datas in the parallel system shown in Figure 2.
As shown in Figure 7, band arrow dotted line is pointer, points to the True Data position, supposes that No. 2 systems carry out the transmission of data to No. 3 systems.No. 2 protocol stack data sent bag is received by system, at the destination address of Drive Layer analysis packet, finds that destination address is No. 3 systems.Thereby from shared buffer, take out the descriptor of No. 3 systems, judge through the state that sends buffering area whether buffering area exists remaining space.If there is available remaining space, then find it to send buffer pointer and locus, data are copied to the pointer assigned address.Revise No. 2 systems in this locality and put w at the reception write bit in a descriptor in No. 3 systems, its value is revised as No. 2 systems sends writes bit in a descriptor to No. 3 systems and put w, this step accomplishes through the rw_off pointer.Writing position w is a numerical value, if many bags in the buffering area, just+1, writing position w is identical with reading location r, and just explanation does not have data, and different just the explanation has data.The system break that takies through No. 2 systems then as No. 137, is sent interrupt signal to No. 3 systems.If there is not remaining space, then stop the transmission of data.So far, No. 2 systems finish to the whole process of No. 3 system's transmission data.Data transmission procedure between other system, all similar process therewith.
Present No. 3 systems by No. 2 system triggers interrupt for No. 137, No. 3 systems can know that this moment, No. 2 systems sent data so.No. 3 system can take out the reception descriptor of No. 2 systems from the shared buffer descriptor of oneself, confirms whether really to have data arrives through read and write position then, if confirm to have then handle packet of data arrives; According to the buffer location that receives in the descriptor; Receive data, and submit to the protocol stack of kernel, revise the reading location r of No. 3 systems transmission descriptor in No. 2 systems then in this locality; Its value is revised as the reading location r of the reception descriptor of No. 3 No. 2 systems of reception of system; This step accomplishes through the rw_off pointer, if free of data arrives, then directly returns.So far, whole No. 3 systems receive the process that No. 2 systems send data and accomplish.
To sum up, transfer of data comprises three processes between whole parallel system: Microsoft Loopback Adapter initialization procedure, data transmission procedure and DRP data reception process.
Fig. 8 is the initialized schematic flow sheet of a kind of Microsoft Loopback Adapter.
Microsoft Loopback Adapter: be meant by software and come the analog hardware function of network card, thereby realize the technology that communicates by network between several operating systems.
Connect a plurality of parallel systems through the PCIe bus, can in a plurality of parallel systems, set up the network of a bottom, realize between each system transfer of data freely.On the upper strata (like application layer); Above-mentioned fabric is equal to a Microsoft Loopback Adapter, and the upper strata need not to consider how to communicate by letter between each parallel system, as long as as using a Microsoft Loopback Adapter; Data are got final product through this Microsoft Loopback Adapter transmission and reception, simply handy.
Specifically, as shown in Figure 8, the initialized process of this Microsoft Loopback Adapter may further comprise the steps,
In step 801, the registered network devices and their operation functions, include turning the equipment off, packet transmission function Alto, etc., registered NAPI function, access to local devices in the system number.
After this get into step 802, the allocation buffer descriptor distributes to receive buffer data.
After this get into step 803, distribution system interrupt resources number is each operating system assigned interrupt resource in parallel system.
After this get into step 804, registration Interrupt Process function.
After this process ends.
Fig. 9 is a kind of schematic flow sheet of data transmission procedure.Specifically, mainly may further comprise the steps:
In step 901, protocol stack transmits the transmission data.
After this get into step 902, extract destination address wherein.
After this get into step 903, judge whether this destination address can be transmitted.
If then get into step 904; If not, then get into step 907.
In step 904,, from buffer descriptor, extract and send buffer state according to destination address.
After this get into step 905,, judge whether the transmission buffering area is full according to sending buffer state.
If then get into step 908; If not, then get into step 906.
In step 906, find and send buffer pointer and locus, data are copied to the pointer assigned address.
After this process ends.
In step 907, directly abandon.After this process ends.
In step 908, wait to be sent or timeout treatment.After this process ends.
Figure 10 is a kind of schematic flow sheet of DRP data reception process.Specifically, mainly may further comprise the steps:
In step 1001, get into and interrupt.
After this get into step 1002, close interruption, prevent that similar interruption from getting into once more, the record interrupt status is waken network up and is received soft interruption.
After this get into step 1003, carry out the NAPI function of registration.
After this get into step 1004, obtain corresponding reception buffer descriptor, handle the reception buffering area of its execution according to interrupt status.
After this get into step 1005, will receive buffer contents and be filled to network packet, be committed to protocol stack then.
After this get into step 1006, upgrade statistic behavior, handle and withdraw from the NAPI function after the data that receive buffering area reach certain condition, or withdraw from and remove interrupt status after accomplishing.
After this process ends.
Each method execution mode of the present invention all can be realized with modes such as software, hardware, firmwares.No matter the present invention be with software, hardware, or the firmware mode realize; Instruction code can be stored in the memory of computer-accessible of any kind (for example permanent or revisable; Volatibility or non-volatile; Solid-state or non-solid-state, fixing perhaps removable medium or the like).Equally; Memory can for example be programmable logic array (Programmable Array Logic; Abbreviation " PAL "), random access memory (Random Access Memory; Abbreviation " RAM "), programmable read only memory (Programmable Read Only Memory is called for short " PROM "), read-only memory (Read-Only Memory is called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM; Abbreviation " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc is called for short " DVD ") or the like.
Third embodiment of the invention relates to data transmission system between a kind of parallel system.Figure 11 is the structural representation of data transmission system between this parallel system.
Specifically, shown in figure 11,
Data transmission system comprises between this parallel system: N parallel system, connect with the PCIe bus between each system, and N is the integer greater than 1.
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system;
Comprise in each system:
Data transmission unit is used for data are passed through the PCIe bus transfer to the reception buffering area of recipient system corresponding to native system;
The buffering area writing unit is used for having new information to data to write the buffer descriptor of recipient system corresponding to native system expression;
Data-reading unit is used for according to the information corresponding to the buffer description of transmit leg system, from corresponding to reading of data the reception buffering area of transmit leg system.
On the upper strata (like application layer); Data transmission system is equal to a Microsoft Loopback Adapter between above-mentioned parallel system, and the upper strata need not to consider how to communicate by letter between each parallel system, as long as as using a Microsoft Loopback Adapter; Data are got final product through this Microsoft Loopback Adapter transmission and reception, simply handy.
Here, need to prove that the recipient system is meant the transmission object of native system data, and the transmit leg system is meant that system that sends the data to native system.
In addition, in said N the parallel system, one is main system, and other system is from system;
Said main system is used for when said N system start-up that walks abreast, accomplishing the guiding startup from system through the PCIe bus;
The PCIe mapping relations of in the guiding start-up course, being set up by main system remain unchanged.
First execution mode is and the corresponding method execution mode of this execution mode, this execution mode can with the enforcement of working in coordination of first execution mode.The correlation technique details of mentioning in first execution mode is still effective in this execution mode, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in this execution mode also can be applicable in first execution mode.
Four embodiment of the invention relates to data transmission system between a kind of parallel system.
The 4th execution mode improves on the basis of the 3rd execution mode, and main improvements are:
Comprise in each buffer descriptor receiving descriptor and sending descriptor, receive descriptor and include writing position and reading location with sending in the descriptor.
Said buffering area writing unit comprises following subelement:
Writing position first is revised subelement, is used for revising the value that native system is put corresponding to the transmission write bit in a descriptor of recipient system;
Writing position second is revised subelement, is used for revising the value that the recipient system puts corresponding to the reception write bit in a descriptor of native system through the PCIe bus;
Said data-reading unit comprises following subelement:
Judgment sub-unit is used for judging native system is put whether identical with reading location corresponding to the reception write bit in a descriptor of transmit leg system;
Read subelement, be used for said judgment sub-unit judge native system corresponding to the reception write bit in a descriptor of transmit leg system put with reading location not simultaneously, to corresponding to reading of data in the reception buffering area of transmit leg system;
Reading location first is revised subelement, is used for revising the value of native system corresponding to the reading location of the reception descriptor of transmit leg system;
Reading location second is revised subelement, is used for revising the value of transmit leg system corresponding to the reading location of the transmission descriptor of native system through the PCIe bus.
The interrupt number that in N parallel system, keeps N the overall situation, a corresponding N system respectively.
Also comprise in each system:
Trigger element, the interrupt number that is used to trigger corresponding to native system is given the recipient system;
Confirm the unit, be used for having no progeny receiving, confirm to trigger the transmit leg system of this interruption according to the interrupt number of this interruption.
In this execution mode, preferably, interruption is that MSI interrupts.
Use MSI interrupt notification peer-to-peer system to receive data, can support the parallel system of a greater number.
In addition, be appreciated that and in some other instance of the present invention, also can use the interruption of other type in principle, interrupt like PCI interruption, GPIO etc.
Second execution mode is and the corresponding method execution mode of this execution mode, this execution mode can with the enforcement of working in coordination of second execution mode.The correlation technique details of mentioning in second execution mode is still effective in this execution mode, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in this execution mode also can be applicable in second execution mode.
Need to prove; Each unit of mentioning in each system implementation mode of the present invention all is a logical block, and physically, a logical block can be a physical location; It also can be the part of a physical location; Can also realize that the physics realization mode of these logical blocks itself is not most important with the combination of a plurality of physical locations, the combination of the function that these logical blocks realized is only the key that solves technical problem proposed by the invention.In addition, for outstanding innovation part of the present invention, above-mentioned each the system implementation mode of the present invention will not introduced with solving the not too close unit of technical problem relation proposed by the invention, and this does not show that there is not other unit in the said equipment execution mode.
Need to prove; In the claim and specification of this patent; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that " comprises " and limit statement, and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
Though through reference some preferred implementation of the present invention; The present invention is illustrated and describes; But those of ordinary skill in the art should be understood that and can do various changes to it in form with on the details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. data transmission method between a parallel system is characterized in that, N parallel system connects with the PCIe bus between each system, and N is the integer greater than 1;
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system;
Said method comprising the steps of:
First system with data through PCIe bus transfer reception buffering area corresponding to first system in second system; Wherein said first system and second system are two systems arbitrarily in the parallel system of said N;
First system has newly expression to the information of data and writes in second system buffer descriptor corresponding to first system;
Second system is according to corresponding to the information in the buffer descriptor of first system, from corresponding to reading of data the reception buffering area of first system.
2. data transmission method between parallel system according to claim 1 is characterized in that, comprises in each buffer descriptor receiving descriptor and sending descriptor, receives descriptor and includes writing position and reading location with sending in the descriptor;
Said first system has newly the step that writes in second system corresponding to the buffer descriptor of first system to the information of data comprise following substep expression:
The value of putting corresponding to the transmission write bit in a descriptor of second system in first system is revised by first system;
The value of putting corresponding to the reception write bit in a descriptor of first system in second system is revised by first system through the PCIe bus;
Said second system basis comprises following substep corresponding to the information in the buffer descriptor of first system from the step corresponding to reading of data the reception buffering area of first system:
Second system judge put corresponding to the reception write bit in a descriptor of first system in second system whether identical with reading location, if different, then to corresponding to reading of data in the reception buffering area of first system;
The value corresponding to the reading location of the reception descriptor of first system is revised in second system by second system;
The value corresponding to the reading location of the transmission descriptor of second system is revised in first system through the PCIe bus by second system.
3. data transmission method between parallel system according to claim 1 and 2 is characterized in that, in said N parallel system, keeps the interrupt number of N the overall situation, respectively a corresponding N system;
Said first system has newly after the information of data writes in second system step corresponding to the buffer descriptor of first system expression further comprising the steps of:
First system triggers is given second system corresponding to the interrupt number of first system;
Have no progeny during second system receives, confirm that according to the interrupt number of this interruption the system of this interruption of triggering is first system.
4. data transmission method between parallel system according to claim 3 is characterized in that, said interruption is that MSI interrupts.
5. data transmission method between parallel system according to claim 1 is characterized in that, and is when said N system start-up that walks abreast, further comprising the steps of:
One in the individual system that walks abreast of said N other system does from system as main system, and main system is accomplished the guiding startup from system through the PCIe bus, and the PCIe mapping relations of in guiding start-up course, being set up by main system remain unchanged.
6. data transmission system between a parallel system is characterized in that, comprising: N parallel system, connect with the PCIe bus between each system, and N is the integer greater than 1;
At least comprise in each system that N-1 buffer descriptor and N-1 receive buffering area, corresponding respectively other N-1 system; Comprise in each system:
Data transmission unit is used for data are passed through the PCIe bus transfer to the reception buffering area of recipient system corresponding to native system;
The buffering area writing unit is used for having new information to data to write the buffer descriptor of recipient system corresponding to native system expression;
Data-reading unit is used for according to the information corresponding to the buffer description of transmit leg system, from corresponding to reading of data the reception buffering area of transmit leg system.
7. data transmission system between parallel system according to claim 6 is characterized in that, comprises in each buffer descriptor receiving descriptor and sending descriptor, receives descriptor and includes writing position and reading location with sending in the descriptor;
Said buffering area writing unit comprises following subelement:
Writing position first is revised subelement, is used for revising the value that native system is put corresponding to the transmission write bit in a descriptor of recipient system;
Writing position second is revised subelement, is used for revising the value that the recipient system puts corresponding to the reception write bit in a descriptor of native system through the PCIe bus;
Said data-reading unit comprises following subelement:
Judgment sub-unit is used for judging native system is put whether identical with reading location corresponding to the reception write bit in a descriptor of transmit leg system;
Read subelement, be used for said judgment sub-unit judge native system corresponding to the reception write bit in a descriptor of transmit leg system put with reading location not simultaneously, to corresponding to reading of data in the reception buffering area of transmit leg system;
Reading location first is revised subelement, is used for revising the value of native system corresponding to the reading location of the reception descriptor of transmit leg system;
Reading location second is revised subelement, is used for revising the value of transmit leg system corresponding to the reading location of the transmission descriptor of native system through the PCIe bus.
8. according to data transmission system between claim 6 or 7 described parallel systems, it is characterized in that, in said N parallel system, keep the interrupt number of N the overall situation, respectively a corresponding N system;
Also comprise in each system:
Trigger element, the interrupt number that is used to trigger corresponding to native system is given the recipient system;
Confirm the unit, be used for having no progeny receiving, confirm to trigger the transmit leg system of this interruption according to the interrupt number of this interruption.
9. data transmission system between parallel system according to claim 8 is characterized in that, said interruption is that MSI interrupts.
10. data transmission system between parallel system according to claim 6 is characterized in that,
In said N the parallel system, one is main system, and other system is from system;
Said main system is used for when said N system start-up that walks abreast, accomplishing the guiding startup from system through the PCIe bus;
The PCIe mapping relations of in the guiding start-up course, being set up by main system remain unchanged.
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