CN102751976A - Electric leakage prevention and electric level compatible circuit based on I2C (Intel-Integrated Circuit) bus - Google Patents
Electric leakage prevention and electric level compatible circuit based on I2C (Intel-Integrated Circuit) bus Download PDFInfo
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- CN102751976A CN102751976A CN2011101011705A CN201110101170A CN102751976A CN 102751976 A CN102751976 A CN 102751976A CN 2011101011705 A CN2011101011705 A CN 2011101011705A CN 201110101170 A CN201110101170 A CN 201110101170A CN 102751976 A CN102751976 A CN 102751976A
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Abstract
The invention relates to an electric leakage prevention and electric level compatible circuit based on an I2C (Inter-Integrated Circuit) bus, which comprises a master controller, a slave unit, an I2Cbus, a first power source VCC_A and a second power source VCC_B. The I2C bus comprises a clock signal line SCL (Serial clock line) and a data line SDA (Serial Data Line); one end SCL_A of the clock signal line SCL is connected with the master controller, and the other end SCL_B of the clock signal line SCL is connected with the slave unit; one end SDA_A of the data line SDA is connected with the master controller and the other end SDA_B of the data line SDA is connected with the slave unit; the electric leakage prevention and electric level compatible circuit further comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an MOS(Metal Oxide Semiconductor)tube; and the MOS tube is connected on the I2C bus and is used for realizing electric level compatibility and electric leakage prevention. Compared with the prior art, the electric leakage prevention and electric level compatible circuit has the advantages that electric leakage prevention and electric level compatibility can be effectively realized under the occasion that the voltage difference of the power source VCC_A and the power source VCC_B is smaller than 0.6V and the like.
Description
Technical field
The present invention relates to a kind of anticreep and level compatible circuit, especially relate to a kind of based on the anticreep of I2C and level compatible circuit.
Background technology
Because the development of large scale integrated circuit technology, at the integrated CPU of single chip and form peripheral circuit such as a necessary ROM of the system that works independently, RAM, I/O port, A/D, D/A and realized single-chip microcomputer or microcontroller that Here it is often says.At present, many in the world companies produce single-chip microcomputer, and kind is a lot: comprise the CPU of various word lengths, and the ROM of various capacity and kind, RAM, and the different I/O of function or the like.But the single-chip microcomputer description is limited, so can only select for use certain single-chip microcomputer to expand again.The method of expansion has two kinds: a kind of is parallel bus, and another kind is a universal serial bus.Because the universal serial bus line is few, simple in structure,
Often need not special-purpose motherboard directly being connected each equipment with lead with socket gets final product.Therefore, adopt universal serial bus to simplify The Hardware Design greatly.PHILIPS company has just preceding released the I2C universal serial bus as far back as the more than ten years, and it is to possess the required high performance serial bus that comprises functions such as ruling and high low speed device synchronization of multi-host system.
The I2C universal serial bus has two holding wires: a two-way data wire SDA; Another root is clock cable SCL.All serial datas of receiving the equipment on the I2C bus are all received the sda line of bus, and the clock cable SCL of each equipment receives the SCL of bus.
Be illustrated in figure 1 as the I2C connection design that present design is adopted.The voltage of master controller end is VCC_A, and the subordinate end is VCC_B.If then just may there be the side electric leakage to small voltage of big voltage in the appearance not of uniform size of VCC_A and VCC_B.Perhaps the electrifying timing sequence of principal and subordinate's chip is different, the chip electric leakage of the voltage that powers on earlier to also not powering on.If VCC_A and VCC_B pressure reduction are very big, can solve through level transferring chip.If but both pressure reduction is less, like 0.1V, 0.2V, then level transferring chip is difficult to realize conversion.
Summary of the invention
The object of the invention is exactly to provide a kind of based on the anticreep of I2C and level compatible circuit for the defective that overcomes above-mentioned prior art existence.Wherein the pressure reduction of VCC_A and VCC_B can be realized level conversion through the present invention in 0.6V.
The object of the invention can be realized through following technical scheme:
A kind of based on the anticreep of I2C and level compatible circuit; Comprise master controller, slave, I2C, the first power supply VCC_A, second source VCC_B; Described I2C comprises clock cable SCL, data wire SDA; The end SCL_A of described clock cable SCL is connected with master controller, and the other end SCL_B of described clock cable SCL is connected with slave; The end SDA_A of described data wire SDA is connected with master controller, and the other end SDA_B of described data wire SDA is connected with slave, and described master controller is connected with the first power supply VCC_A, and described slave is connected with second source VCC_B;
It is characterized in that also comprise resistance R 1, resistance R 2, resistance R 3, resistance R 4, metal-oxide-semiconductor, described metal-oxide-semiconductor is connected on the I2C, it is compatible and anticreep to be used to do level; Described resistance R 1 is connected between the end SCL_A and the first power supply VCC_A of clock cable SCL; Described resistance R 2 is connected between the end SDA_A and the first power supply VCC_A of data wire SDA; Described resistance R 3 is connected between the other end SCL_B and second source VCC_B of clock cable SCL, and described R4 is connected between the other end SDA_B and second source VCC_B of data wire SDA.Wherein the pressure reduction of VCC_A and VCC_B is less than 0.6V.
The resistance of described resistance R 1, resistance R 2, resistance R 3, resistance R 4 is identical.
If the first power supply VCC_A is smaller or equal to second source VCC_B; Described metal-oxide-semiconductor is that two N link up metal-oxide-semiconductor, comprises the grid that is connected with the first power supply VCC_A, first drain electrode that is connected with the end SCL_A of clock cable SCL, second drain electrode that is connected with the end SDA_A of data wire SDA, first source electrode that is connected with the other end SCL_B of clock cable SCL, second source electrode that is connected with the other end SDA_B of data wire SDA.
If the first power supply VCC_A is greater than second source VCC_B; Described metal-oxide-semiconductor is that two N link up metal-oxide-semiconductors, comprise the grid that is connected with the first power supply VCC_B, first source electrode that is connected with the end SCL_A of clock cable SCL, second source electrode that is connected with the end SDA_A of data wire SDA, be connected with the other end SCL_B of clock cable SCL first drain, be connected with the other end SDA_B of data wire SDA second drain.
Compared with prior art, in 0.6V, it is anticreep compatible with level that the present invention has effective realization to the pressure reduction of VCC_A and VCC_B.
Description of drawings
Fig. 1 is that existing I2C connects design circuit figure;
Fig. 2 is a circuit diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is elaborated.
Embodiment
As shown in Figure 2, a kind of based on the anticreep of I2C and level compatible circuit, comprise master controller 1, slave 2, I2C, metal-oxide-semiconductor, resistance R 1, resistance R 2, resistance R 3, resistance R 4, the first power supply VCC_A, second source VCC_B;
Described I2C comprises clock cable SCL, data wire SDA, and the end SCL_A of described clock cable SCL is connected with master controller 1, and the other end SCL_B of described clock cable SCL is connected with slave 2; The end SDA_A of described data wire SDA is connected with master controller 1, and the other end SDA_B of described data wire SDA is connected with slave 2; Described resistance R 1 is connected between the end SCL_A and the first power supply VCC_A of clock cable SCL; Described resistance R 2 is connected between the end SDA_A and the first power supply VCC_A of data wire SDA; Described resistance R 3 is connected between the other end SCL_B and second source VCC_B of clock cable SCL, and described R4 is connected between the other end SDA_B and second source VCC_B of data wire SDA; Wherein the pressure reduction of VCC_A and VCC_B is less than 0.6V.
Described master controller 1 is connected with the first power supply VCC_A, and described slave 2 is connected with second source VCC_B.
Wherein, If the first power supply VCC_A is smaller or equal to second source VCC_B; Described metal-oxide-semiconductor is that two N link up metal-oxide-semiconductors, comprises the grid G that is connected with the first power supply VCC_A, first drain D 1 that is connected with the end SCL_A of clock cable SCL, second drain D 2 that is connected with the end SDA_A of data wire SDA, first source S 1 that is connected with the other end SCL_B of clock cable SCL, second source S 2 that is connected with the other end SDA_B of data wire SDA; If the first power supply VCC_A is greater than second source VCC_B, the metal-oxide-semiconductor reversal connection, and the grid G terminal voltage meets second source VCC_B.
The resistance of described resistance R 1, resistance R 2, resistance R 3, resistance R 4 is identical, is 4.7K Ω.
It is two N-MOS pipes that metal-oxide-semiconductor is selected 2N7002DW, 2N7002DW, has high switch speed, low threshold conducting voltage (VGS (th)), and low-leakage current, so 2N7002DW just can satisfy the application of I2C.
Analyze in the face of the work of this circuit down.VCC_A≤VCC_B(VCC_B-VCC_A＜0.6V)
1) master controller 1 is to slave 2 transmitting control commands
When SCL_A and SDA_A sent high level, this moment, SCL_B and SDA_B drew on the VCC_B, also were high level, Vgs≤0, and not conducting of NMOS, it also is high level that SCL_B and SDA_B keep drawing on the VCC_B.Subordinate end and master controller end state consistency.
When SCL_A and SDA_A send low level; SCL_B and SDA_B are through the inner diode current flow of NMOS, and voltage is reduced to the conducting voltage 0.6-0.7V of diode, at this moment Vgs＞VGS (th); The metal-oxide-semiconductor conducting, SCL_B and SDA_B are dragged down by SCL_A and SDA_A and are low level.Slave 2 ends and master controller 1 end state consistency.
2) slave 2 is to master controller 1 return state
When SCL_B and SDA_B sent high level, this moment, SCL_A and SDA_A drew on the VCC_A, also were high level, Vgs≤0, and not conducting of NMOS, it also is high level that SCL_A and SDA_A keep drawing on the VCC_A.Master controller end and subordinate end state consistency.
When SCL_B and SDA_B send low level, Vgs=(VCC_A-0)＞VGS (th), then NMOS pipe conducting, SCL_A and SDA_A are dragged down by SCL_B and SDA_B and are low level.Master controller 1 end and slave 2 end state consistencies.
Analysis through top finds out that the I2C level voltage of main equipment end remains VCC_A, and the I2C level voltage of slave 2 ends remains VCC_B.And aspect electrifying timing sequence, a side powers on earlier because the existence of NMOS can not leaked electricity to the other side yet.
Claims (4)
1. one kind based on the anticreep of I2C and level compatible circuit; Comprise master controller, slave, I2C, the first power supply VCC_A, second source VCC_B; Described I2C comprises clock cable SCL, data wire SDA; The end SCL_A of described clock cable SCL is connected with master controller, and the other end SCL_B of described clock cable SCL is connected with slave; The end SDA_A of described data wire SDA is connected with master controller, and the other end SDA_B of described data wire SDA is connected with slave, and described master controller is connected with the first power supply VCC_A, and described slave is connected with second source VCC_B;
It is characterized in that also comprise resistance R 1, resistance R 2, resistance R 3, resistance R 4, metal-oxide-semiconductor, described metal-oxide-semiconductor is connected on the I2C, it is compatible and anticreep to be used to do level; Described resistance R 1 is connected between the end SCL_A and the first power supply VCC_A of clock cable SCL; Described resistance R 2 is connected between the end SDA_A and the first power supply VCC_A of data wire SDA; Described resistance R 3 is connected between the other end SCL_B and second source VCC_B of clock cable SCL, and described R4 is connected between the other end SDA_B and second source VCC_B of data wire SDA.Wherein the pressure reduction of VCC_A and VCC_B is less than 0.6V.
2. according to claim 1 a kind ofly it is characterized in that based on the anticreep of I2C and level compatible circuit, the resistance of described resistance R 1, resistance R 2, resistance R 3, resistance R 4 is identical.
3. according to claim 1 a kind of based on the anticreep of I2C and level compatible circuit; It is characterized in that; If the first power supply VCC_A is smaller or equal to second source VCC_B; Described metal-oxide-semiconductor is that two N link up metal-oxide-semiconductor, comprises the grid that is connected with the first power supply VCC_A, first drain electrode that is connected with the end SCL_A of clock cable SCL, second drain electrode that is connected with the end SDA_A of data wire SDA, first source electrode that is connected with the other end SCL_B of clock cable SCL, second source electrode that is connected with the other end SDA_B of data wire SDA.
4. according to claim 1 a kind of based on the anticreep of I2C and level compatible circuit; It is characterized in that; If the first power supply VCC_A is greater than second source VCC_B; Described metal-oxide-semiconductor is that two N link up metal-oxide-semiconductors, comprise the grid that is connected with the first power supply VCC_B, first source electrode that is connected with the end SCL_A of clock cable SCL, second source electrode that is connected with the end SDA_A of data wire SDA, be connected with the other end SCL_B of clock cable SCL first drain, be connected with the other end SDA_B of data wire SDA second drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101011705A CN102751976A (en) | 2011-04-21 | 2011-04-21 | Electric leakage prevention and electric level compatible circuit based on I2C (Intel-Integrated Circuit) bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101011705A CN102751976A (en) | 2011-04-21 | 2011-04-21 | Electric leakage prevention and electric level compatible circuit based on I2C (Intel-Integrated Circuit) bus |
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| CN102751976A true CN102751976A (en) | 2012-10-24 |
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| CN2011101011705A Pending CN102751976A (en) | 2011-04-21 | 2011-04-21 | Electric leakage prevention and electric level compatible circuit based on I2C (Intel-Integrated Circuit) bus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107368444A (en) * | 2017-08-02 | 2017-11-21 | 杭州迪普科技股份有限公司 | Electronic equipment |
| CN114090492A (en) * | 2021-11-24 | 2022-02-25 | 南京众核电子科技有限公司 | I2C level conversion device and method applied to processor |
-
2011
- 2011-04-21 CN CN2011101011705A patent/CN102751976A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107368444A (en) * | 2017-08-02 | 2017-11-21 | 杭州迪普科技股份有限公司 | Electronic equipment |
| CN114090492A (en) * | 2021-11-24 | 2022-02-25 | 南京众核电子科技有限公司 | I2C level conversion device and method applied to processor |
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Application publication date: 20121024 |