CN102750175A

CN102750175A - Method for realizing FPGA (Field Programmable Gate Array) loading technology based on Nand Flash multiversion programs

Info

Publication number: CN102750175A
Application number: CN2012102430202A
Authority: CN
Inventors: 刘剑; 翟刚毅
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2012-07-10
Filing date: 2012-07-10
Publication date: 2012-10-24

Abstract

The invention relates to a method for realizing an FPGA (Field Programmable Gate Array) loading technology based on Nand Flash multiversion programs. The method is mainly applied to a signal processing architecture platform adopting an FPGA chip, a microprocessor ARM on a universal FPGA line card selects the corresponding version program intelligently to load the FPGA after being electrified, so that the specific function of the FPGA line card is realized. The method comprises the following steps of: the ARM receives the multiversion FPGA programs by a network and writing the multiversion FPGA programs into the Nand Flash; and after the line card is electrified, the ARM reads corresponding programs from the Nand Flash to load the FPGA according to the slot position number of the line card; and after the loading is successful, the FPGA with the specific slot position realizes the specific function, so that all the FPGA line cards under the universal signal processing architecture work in a cooperative manner to realize the function of the system. Under the universal signal processing architecture platform, the method enables the FPGA line cards to have more universality, flexibility and maintainability.

Description

FPGA loading technique based on the many version programs of Nand Flash

One technical field

The present invention relates to the FPGA loading technique of the many version programs of a kind of Nand Flash.The technology that it has adopted based on high capacity Nand Flash and TCP/IP network has realized that the FPGA ply-yarn drill selects to realize specific function automatically according to slot number.The FPGA ply-yarn drill has more by versatility, dirigibility, maintainability like this.

Two background technologies

Along with the develop rapidly of integrated circuit, computer technology and software engineering, the Radar Signal Processing development is tending towards digitizing, software implementation, intellectuality.Radar signal data handling system platform demonstrates dual development trend: (1) is main outdoor unit with the antenna system, and wherein the signal data processing capacity is a Signal Pretreatment, is tending towards distributed; (2) be master's indoor unit with the integrated signal data processing, be referred to as the signal master usually and handle, be tending towards comprehensive integrationization.And along with digital phase control battle array Radar Development, these two kinds of trend are obvious day by day.And high integration, versatility, the maintainable development of Radar Signal Processing card have been quickened.

At present, form Universal Signal Processor based on the general FPGA ply-yarn drill of VPX framework and be widely used in Radar Signal Processing.

The specific download device of each FPGA manufacturer release or the PROM of low capacity are all adopted in the debugging of FPGA program and loading in the past, adopt downloader not only to cost an arm and a leg, and environment for use is required height, in charged on-line debugging process, very easily damage.Need one end of download cable directly be connected with FPGA in this locality during the program of carrying; The other end is connected with PC through USB interface; In case after the packing of product is good, revise or upgrading FPGA program, its loading procedure becomes and very bothers again; Need to connect downloader behind the knocked-down packing shell, could realize the renewal of program.The extremely consuming time and inefficiency of this process is especially in development debug phase of New System phased-array radar.

Adopt PROM to load FPGA ply-yarn drill mode,,, can only insert the specified channel position of VPX Universal Signal Processor like this in case after loading, can only realize a specific function owing to only there is single program.This shows that the processor that this ply-yarn drill is formed does not meet radar versatility development trend.

Characteristics of the present invention are to utilize high capacity Nand Flash and TCP/IP technology to realize that the FPGA ply-yarn drill realizes specific function according to the groove position automatically, have realized dirigibility, versatility, the maintainability of FPGA ply-yarn drill.

Three summary of the invention

The objective of the invention is to adopt high capacity Nand Flash and TCP/IP technology to realize that the FPGA ply-yarn drill can be according to the function of groove position realization expectation realization.The FPGA ply-yarn drill has good dirigibility, versatility, maintainability like this.

The present invention is the basis with growing high capacity Nand Flash and TCP/IP network technology.Computing machine with ICP/IP protocol, sends to many version programs of FPGA the microprocessor ARM of FPGA ply-yarn drill through netting twine; ARM judges whether to giving the data of this machine according to the IP address in the packet; If the IP address meets, then receive packet, ARM is written to these a plurality of version programs among the jumbo Nand Flash then; After a plurality of version programs sent completion, the ARM chip began to select the program of respective version initiatively to load FPGA according to the slot number at FPGA ply-yarn drill place.After powering up, the microprocessor ARM of ply-yarn drill selects corresponding program to load FPGA according to slot number, realizes the versatility of FPGA ply-yarn drill with this at every turn.

The invention is characterized in, used high capacity Nand Flash and ripe TCP/IP procotol, guaranteed that a plurality of version programs store and data are transmitted reliably; With high capacity Nand Flash serves as that the basis stores a version program, and microprocessor loads according to the slot number option program, has realized the versatility of ply-yarn drill; Mode with server is worked, realized can accomplishing simultaneously program updates to a plurality of FPGA ply-yarn drills through switch; Used passive load mode, the FPGA that has guaranteed not to cause because of the routine data mistake can't be from ROM reading of data, improved the reliability of real work.The present invention efficiently solves the dirigibility of FPGA ply-yarn drill, the problem of versatility, maintainability.Realized Radar Signal Processing card versatility, promoted signal processor being widely used in field of radar based on the VPX framework.

The present invention compared with prior art, its remarkable advantage is: (1) need not to use FPGA specific download cable, economize on hardware R&D costs; (2) adopt the loading algorithm of optimizing, realize that the efficient, quick, correct of data loads; (3) use ripe TCP/IP procotol, guaranteed reliability of data transmission; (4) can realize any time, any place, to the renewal of the FPGA program of signal processing card; (5) store a plurality of version programs, realize specific function, realized the versatility of signal processing card according to the groove position.

Below in conjunction with accompanying drawing the present invention is described in further detail.

Four description of drawings

Fig. 1 is that the hardware of present technique invention is realized block diagram;

Fig. 2 is that many version programs of present technique invention write the Flash process flow diagram;

Fig. 3 is that the microprocessor of present technique invention loads the FPGA process flow diagram.

Five embodiments

The present invention specifically implements from the following aspects:

1) the microprocessor ARM on the FPGA ply-yarn drill operates in μ COS-II implementation and operation system; The network-side of ARM is set to server end, like this, can effectively avoid the no response condition in the network service; Reduce the connection request of computing machine, simplify the design of computer program.

2) adopt the TCP/IP procotol, computing machine sends to microprocessor through network with a plurality of FPGA configuration files.Microprocessor judges according to the IP address of network packet whether this packet sends to oneself.If send to oneself, then receive this packet.If not, then abandon this packet.Owing to adopted ICP/IP protocol, it has guaranteed the high reliability of transmitted data on network between the ARM on computing machine and the ply-yarn drill.

3) after microprocessor ARM receives the configuration file of FPGA, wipe among the Nand Flash content among the corresponding Page, microprocessor is written to the FPGA configuration file that is received among the Nand Flahs afterwards.

4) after perhaps ply-yarn drill powered up after configuration file write and accomplishes, microprocessor ARM read the slot number that the FPGA ply-yarn drill self is positioned general signal processing platform.According to slot number and FPGA program correspondence table, microprocessor ARM reads out corresponding FPGA configuration file from Nand Flash.

5) microprocessor ARM drags down the PROG_B pin of FPGA, starts layoutprocedure.When PROG_B drags down, FPGA begins to remove self internal RAM, and FPGA joins the INIT_B pin low in this process.After RAM removed completion, the INIT_B pin uprised.Microprocessor ARM monitoring INIT_B pin, after this pin becomes high level, microprocessor with the program file that will dispose deliver to the DIN pin of FPGA, deliver to corresponding clock CCLK to FPGA simultaneously.In this process, the DONE pin of microprocessor monitors FPGA if the DONE pin is a high level, explains that then FPGA loads successfully.If DONE is a low level, then repeating step 4), 5).Load successfully until FPGA.

This method uses the TCP/IP network technology to realize the remote update of FPGA program, uses a plurality of version FPGA programs of high capacity Nand Flash technology storage, loads according to the automatic option program of slot number, has realized the versatility of FPGA ply-yarn drill.

Claims

1. the FPGA based on the many version programs of Nand Flash loads the implementation method technology; It is characterized in that: microprocessor ARM reads corresponding configuration file according to the slot number of ply-yarn drill automatically from Nand Flahs carries out FPGA and load: at first microprocessor receives the configuration file that main frame sends through TCP/IP; And these configuration files are written among the Nand Flash, microprocessor reads corresponding configuration file according to the residing slot number of FPGA ply-yarn drill and loads FPGA from Nand Flash.

2. realize that the described FPGA based on the many version programs of Nand Flash of claim 1 loads the implementation method technology for one kind; It is characterized in that: for guaranteeing the reliability of data in the Network Transmission; Adopted the TCP/IP network transmission protocol, when the Frame that receives is staggered the time, protocol layer is the retransmits erroneous frame automatically; Guaranteed the correctness of loading procedure, and realized the remote update of configuration file through long-distance transmissions.

3. realize that the described FPGA based on the many version programs of Nand Flash of claim 1 loads the implementation method technology for one kind; It is characterized in that: adopt wiping of ARM control Nand Flash; The technology of reading and writing operation has realized the storage of the FPGA configuration file of a plurality of versions.

4. realize that the described FPGA based on the many version programs of Nand Flash of claim 1 loads the implementation method technology for one kind; It is characterized in that: ARM can read corresponding configuration file automatically according to slot number and load FPGA; Realized the dirigibility of FPGA ply-yarn drill, versatility, ease for maintenance.