CN102739346B - Readdressing decoder for quasi-cyclic low-density parity-check code and decoding method - Google Patents

Abstract

Provided in the invention is a readdressing decoder, which is used for decoding quasi-cyclic coding and comprises a memory, a controller and a plurality of parallel processors. The memory stores a quasi-cyclic coding matrix containing a plurality of submatrixes respectively having corresponding addresses. The controller readdresses all the submatrixes as a plurality of segmented matrixes and at least defines the segmented matrixes to a first address group and a second address group. The controller respectively transmits the segmented matrixes corresponding to the first address group and the segmented matrixes corresponding to the second address group to the parallel processors to carry out debugging calculation.

Description

For addressing decoders again and the coding/decoding method of quasi-cyclic low-density parity check codes

Technical field

The invention relates to a kind of for quasi-cyclic low-density parity check codes (quasi-cyclic low-densityparity-check codes, Q-C LDPC) decoder and coding/decoding method, and relate to one especially there is parallel processing framework, be applied to decoder and the coding/decoding method thereof of quasi-cyclic low-density parity check codes.

Background technology

Along with the development of wireless transmission and mechanics of communication, for the requirement also increasingly stringent of transmitting bandwidth and efficiency.Forward error correction technique (Forward Error Correction) technology has significant effect for the correctness of promoting transmission to promote efficiency of transmission, therefore day by day for people payes attention to.The method of many forward error corrections be encoded in this general mood under be suggested one by one, more known has block code (Block Code), Hamming code (Hamming Code), convolution code (Convolutional Code), and compares turbine code (Turbo Code) and the low density parity check code of attention nearly ten years.The wherein application of low density parity check code in forward error correction technique, because it close to the coding usefulness of shannon limit (Shannon Limit) in theory, can become the branch that one of them is very important.

Shannon limit may be defined as the encoding rate in a communication channel, has a specific signal to noise ratio (SNR).In other words, shannon limit refers to the limit of channel transmission ability.

Low-density parity correcting code is the one of linear block codes, and low-density refers to check that the number of in matrix 1 compares ratio shared in whole matrix element considerably less, and this also characteristic of correcting of low-density parity just.Linear block codes (Linear Block Code) is a kind of conventional bug patch code, this coding principle be by the signal that will transmit first with generator matrix (Generate matrix, G matrix) be multiplied, namely can produce the transmission code also grown than initial data.Receiving terminal receive this signal can with transposition after inspection matrix (Check matrix, H matrix) be multiplied the data that check and corrected received arrives, be returned to the state of initial data.

With low-density parity correcting code, (n, k) low-density parity correcting code, its n represents the length (Codeword) of code, and the length of k representative data bit (Information Bits), the inspection matrix H that recycling definition produces, its code check of definable R=k/n.Check that matrix H is according to every row weight (column weight) or often whether identical row weight (row weight) is, can be divided into rule, half is regular, irregular three kinds.Namely row weight is the number of in a line 1, and row weight refers to the number of in row 1.In H matrix, as row weight is fixed, and row weight is also fixed, and is defined as rule and checks matrix.Only have one to fix and be then defined as half rule, both are neither fixing is then defined as irregular inspection matrix.With regard in efficiency, the usefulness of irregular inspection matrix is best, but also because its irregular characteristic causes its hardware designs many compared with the above two complexity.

At present, various countries promote and the received terrestrial digital broadcasting specification formulated, such as China Mobile multimedia broadcasting system (China Mobile Multimedia Broadcasting, CMMB), terrestrial DTV transmission standard (DigitalTerrestrial Multimedia Broadcast, and digital video broadcasting (Digital VideoBroadcasting DTMB), DVB), or wireless transmission standards such as WiMAX, IEEE802.11n or IEEE 802.3an etc., also respective basis low-density parity correcting code added as forward error correction technique.

The low-density parity correcting code being applied to aforementioned received terrestrial digital broadcasting has the characteristic of accurate circulation (Quasi-Cyclic), is called quasi-cyclic low-density odd and even correction code (QC-LDPC).Define a QC-LDPC code, usually only need the parity matrix defining its correspondence, QC-LDPC code is made up of multiple equal-sized rarefaction cycles matrixes.

QC-LDPC code has code word circulation (Code Word Cyclic) attribute, even code word C=(c0, c1, ..., cN-1) be a legal-code (wherein N represents code word size), the code word Tsc=(cN-s, the cN-s+1 that so will obtain after code word C to the right loopy moving S (0≤s≤N-1) individual element, ..., cN-s-1) be still a legal-code.Accurate circulation is different from circulation, is only a kind of local circulation.In other words, QC-LDPC code has accurate cycle attribute, concrete soluble as follows.

Suppose code word c=(c1, c2 ..., cn) be a legal-code of QC-LDPC code, wherein code word size N=nL, vectorial cj=(cj, 0, cj, 1 ..., cj, L-1) (1≤j≤n) length is L, is still so a legal QC-LDPC code word by the code word c code word Tpc that loop obtains after moving p (0≤p≤L-1) individual element to the right.Wherein circulation code word Tpc=(~ Tpc1, ~ Tpc2 ..., ~ Tpcn) represent and circulation right shift is carried out to each vectorial cj, namely ~ Tpc=(cj, L-p, cj, L-p+1 ..., cj, L-p-1).

Conventional LDPC decoding carries out computing in natural logrithm field (substrate is the log-domain of e), and by the computing in log-domain, obtain and multiplication is converted to addition, division is converted to subtraction, and can prophylactic iedex and do not affect decoder capabilities completely.But, still need to process more difficult mathematical computations when LDPC carries out natural logrithm computing, such as following exponential sum computing:

In(e ^a+e ^b+e ^c+...)

For reducing the burden of aforementioned exponential sum computing, below utilize Jacobi equation formula (Jacobian Formula) to carry out simplified operation, the mathematical form of Jacobi equation formula is:

max ^*(a，b)＝In(e ^a+e ^b)＝max(a，b)+In(1+e ^-|a-b|)

Jacobi calculates and usually are referred to broadly as max ^*computing, when attempting to calculate longer exponential sum, the Jacobi's computing only providing two parameter a and b can replace exponential sum with additive and calculate, and therefore greatly reduces the complexity of decoding.

For realizing the method that data are entangled with QC-LDPC code, in terrestrial broadcasting specification, in transmitting terminal, the signal of transmission is first multiplied with generator matrix (Generate matrix, G matrix), namely can produces the transmission code longer than initial data.After receiving terminal receives this signal, the inspection matrix (Check matrix, Hmatrix) after transmission code and transposition can be multiplied, with the data checked and corrected received arrives, being returned to the state of initial data, is 4 bits with initial data length, and transmission data length is 7 bits is example:

In transmission end, the situation that initial data is multiplied with generator matrix, can be expressed as following mathematical expression (1):

$\left[\begin{array}{cccc}{d}_1& d_2& d_3& d_4\end{array}\right]\×\left[\begin{array}{ccccccc}1& 0& 0& 0& 1& 1& 0\\ 0& 1& 0& 0& 1& 0& 1\\ 0& 0& 1& 0& 0& 1& 1\\ 0& 0& 0& 1& 1& 1& 1\end{array}\right]=\left[\begin{array}{ccccccc}{e}_1& e_2& e_3& e_4& e_5& e_6& e_7\end{array}\right]---\left(1\right)$

In receiving terminal, order checks that matrix is for generating transpose of a matrix matrix, and utilize matrix to be multiplied with transposed matrix to be the mathematical characteristic of 0, inspection also decodes initial data in receiving terminal.Following mathematical expression (2) can be expressed as:

$\left[\begin{array}{ccccccc}{e^{\′}}_1& {e^{\′}}_2& {e^{\′}}_3& {e^{\′}}_4& {e^{\′}}_5& {e^{\′}}_6& {e^{\′}}_7\end{array}\right]\left[\begin{array}{ccc}1& 1& 0\\ 1& 0& 1\\ 0& 1& 1\\ 1& 1& 1\\ 1& 0& 0\\ 0& 1& 0\\ 0& 0& 1\end{array}\right]=\left\{\begin{array}{c}{e^{\′}}_1+{e^{\′}}_2+{e^{\′}}_4+{e^{\′}}_5=0\\ {e^{\′}}_1+{e^{\′}}_3+{e^{\′}}_4+{e^{\′}}_6=0\\ {e^{\′}}_2+{e^{\′}}_3+{e^{\′}}_4+{e^{\′}}_7=0\end{array}\right.---\left(2\right)$

If equal inerrancy in transmitting procedure, the operation result then carrying out mathematical expression (2) at receiving terminal can produce null vector, if but produce non-vanishing vector, then represent in data that receiving terminal receives wrong, now to need via inspection matrix calculus method, to locate errors position corrected as right value, to reach the ability of error correction.

Under the choice of decode usefulness and hardware complexity, the decoding of LDPC adopts part parallel (partially parallel) framework to realize mostly, and in this framework, memory (memory) is used to store the information exchanged.And the size of memory with check binary digit in matrix (parity check matrix, PCM) " 1 " and number be directly proportional.Because memory occupies sizable area in the integrated circuit realizing LDPC decoding, how to reduce memory area and become an important subject in LDPC decoder.

With the example of received terrestrial digital broadcasting, when received terrestrial digital broadcasting specification application quasi-cyclic low-density odd and even correction technology is decoded, known decoding architecture must process a large amount of data simultaneously.With DVB-T2 standard, in code check 3/4 when, in order to be used by the information decoding in a page (frame), system must have the ability to store simultaneously and high-speed computation one is up to the inspection matrix of 64800 bit sizes.Clearly, even if under the basis of parallel calculation, in order to the restriction of minimum turnover rate under meeting Dynamic Announce, also need quite at a high speed and a large amount of system resource to process the data volume of aforementioned matrix.Therefore the cost realizing received terrestrial digital broadcasting specification is a significant increase.

According to upper, the invention provides a kind of decoder and the coding/decoding method thereof that are applied to quasi-cyclic low-density parity check codes, to process foregoing problems.

Summary of the invention

Therefore, an object of the present invention is to provide a kind of decoder and the coding/decoding method thereof that are applied to quasi-cyclic low-density parity check codes, and during to solve high-speed computation quasi-cyclic low-density parity check codes, thus a large amount of consumption calculation resources increase the problem of cost.

According to embodiments of the invention, it discloses addressing decoders again and again, for accurate loop coding of decoding, comprises a memory, stores loop coding matrix surely, and this accurate loop coding matrix comprises multiple submatrix, and each submatrix has a corresponding address; One controller, the more each submatrix of addressing is multiple subdivision matrix, and at least define these subdivision matrixes to one first address group and one second address group; And multiple parallel processor, this controller by should the first address group these subdivision matrixes and to these subdivision matrixes of the second address group should being sent to these parallel processor respectively and carrying out debug calculation, to produce one first debug result and one second debug result, the sum of these parallel processor and be defined in this first address group these subdivision matrixes sum or be defined in this second address group these subdivision matrixes sum between be integer ratio relation.

Embodiments of the invention separately disclose one addressing coding/decoding method again, for accurate loop coding of decoding, it comprises according to a subdivision matrix quantity, the more each submatrix of addressing is multiple subdivision matrix, and defines in these subdivision matrixes to one first address group or one second address group; And debug calculation is carried out to these subdivision matrixes being defined in this first address group and these subdivision matrixes of being defined in this second address group.

The advantage of embodiments of the invention is to provide one addressing decoders again, the submatrix checked in matrix can be cut into subdivision matrix to process, then according to addressing index again, the subdivision matrix after process be reduced to submatrix.Therefore according to the quantity n of subdivision matrix, the quantity of parallel processor in debugger can be reduced to original 1/n, significantly reduce the hardware cost realized needed for high-speed decoding.

In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below:

Accompanying drawing explanation

Fig. 1 is the schematic diagram of a terrestrial broadcast system receiving terminal 100 of the present invention one specific embodiment.

Fig. 1 a is that LDPC encodes the schematic diagram of bilateral figure.

Fig. 2 is to a QC-LDPC, the minimum and algorithm of an application of specific embodiments of the invention checks that matrix carries out the better implementing procedure figure of computing.

Fig. 3 a is the schematic diagram of addressing method again of specific embodiments of the invention.

Fig. 3 b is the schematic diagram of addressing method again and again of a specific embodiment of the present invention.

Fig. 3 c is again and again addressing method flow chart.

Fig. 4 is the schematic diagram of the disclosed debugger of addressing again.

Fig. 5 is the schematic diagram of disclosed another addressing debugger again.

Main element symbol description

100: terrestrial broadcast system receiving terminal

102: antenna

103: tuner

104: demodulator

106 forward error correction decoders

108: page processor

106a: deinterlacer

106b:LDPC decoder

400: addressing debugger again

401: memory

402: controller

403a, 403b ~ 403n: parallel processor

404: first information passage

405: the second information channels

406: addressing passage

500: debugger

501: memory

501a, 501b ~ 501n: memory cell

502: addressing controller again

503: internal network controller

503a: tubbiness shift unit

504a, 504b ~ 504n: parallel processor

505: the first addressing passages

506: the second addressing passages

508: the second data channel

Embodiment

Some vocabulary is employed to censure specific element in the middle of specification and follow-up claim.Person with usual knowledge in their respective areas should understand, and hardware manufacturer may call same element with different nouns.This specification and follow-up claim are not used as the mode of distinguish one element from another with the difference of title, but are used as the criterion of differentiation with element difference functionally." comprising " mentioned in the middle of specification and follow-up claims is in the whole text an open term, therefore should be construed to " comprise but be not limited to ".In addition, " " word comprises directly any at this and is indirectly electrically connected means in electrical connection.Therefore, if describe a first device in literary composition to be electrically connected on one second device, then represent this first device and directly can be electrically connected in this second device, or be indirectly electrically connected to this second device through other devices or connection means.

The schematic diagram of the terrestrial broadcast system receiving terminal 100 that Fig. 1 discloses for one embodiment of the present of invention, this terrestrial broadcast system 100 comprises an antenna (antenna) 102, tuner (tuner) 103, demodulator (demodulator) 104, forward error correction decoder (FEC decoder) 106 and a page processor (framingprocessor) 108.This forward error correction decoder 106 comprises a deinterlacer (deinterleaver) 106a and LDPC decoder (LDPC decoder) 106b.This LDPC decoder 106b comprises product comparator (productcomparator) 106b1 and debugger (corrector) 106b2.This antenna 102 is electrically connected with this tuner 103, and this tuner 103 is electrically connected with this demodulator 104, and this demodulator 104 is electrically connected with this forward error correction decoder 106, and this forward error correction decoder 106 is electrically connected with this page processor 108.This deinterlacer 106a is electrically connected with this product comparator 106b1 with this demodulator 104 respectively, and this product comparator 106b1 and this debugger 106b2 is electrically connected.This LDPC decoder 106b and this page processor 108 are electrically connected.

This antenna 102 receives the RF ground broadcast singal that a terrestrial broadcast system transmitting terminal is sent, and is sent to this demodulator 104 and carries out demodulation, to produce a fundamental frequency ground broadcast signal, and exports this fundamental frequency ground broadcast signal to this deinterlacer 106a.This fundamental frequency ground broadcast signal is converted to the data matrix (information matrix) of quasi-cyclic low-density odd and even correction code form by this deinterlacer 106a, and this data matrix is sent to this product comparator 106b1.In an embodiment, this tuner 103 can perform to change (down-converting), rectification action (demodulating) and when input signal is revolution word format process during analogy form by the frequency reducing that RF ground broadcast singal becomes intermediate frequency (intermediate frequency) or fundamental frequency (base band) from radio frequency.This deinterlacer 106a can perform code-change modulation (Variable Coding and Modulation, VCM) and adaptive coding's modulation (Adaptive Coding and Modulation, ACM) computing.This data matrix and one are checked that matrix multiple is to produce one first test value by this product comparator 106b1, when this first test value is 0, data then in this data matrix are correct, and this LDPC decoder (LDPC decoder) 106b takes out the page data (frame data) in this data matrix.This page data is transferred into this page processor 108, and this page data is shown in a display screen (not shown) by this page processor 108.

When this first test value is more than or equal to 0, then start this debugger 106b2 and carry out debug, the mode of debug is for utilizing this inspection matrix of LDPC decoding algorithm correction, and send this inspection matrix revised back to this product comparator 106b1, this product comparator 106b1 by this data matrix and this inspection matrix multiple revised, to produce one second test value.When this second test value is not 0, then this debugger 106b2 utilizes LDPC algorithm again to revise this inspection matrix again, until the test value that this product comparator 106b1 produces is 0.This debugger 106b2 can utilize and the algorithm such as long-pending algorithm (sum-product algorithm), log domain and long-pending algorithm (log-domain sum-product algorithm), minimum and algorithm (min-sum algorithm) is realized.In the present embodiment, this debugger 106b2 can utilize software or hardware structure to implement, the function of this debugger 106b2 can be expanded or be changed, such as, debugger 106b2 by this hardware implementation can comprise the implementing circuit of multiple kinds of algorithms simultaneously, coordinates the Different Ground broadcast standard for implementing or customer demand and start different algorithm function.And by the debugger 106b2 of implement software, then can pass through the difference of write software, realize its function with different algorithms.

This terrestrial broadcast system receiving terminal 100 disclosed in Fig. 1, can be applicable to follow standardization department of International Telecommunication Union (The Telecommunication Standardization Sector, in the terrestrial broadcast system of the ITU-T ITU-T) defined J.83 standard, such as DVB-T2 standard is just included.In the standard of DVB-T2, this data matrix of encoding through LDPC is defined as a code pages (FERFRAME) forward, this forward code pages in DVB-T2 standard, comprise two kinds of character code forms, be 64800 and 16200 bit sizes respectively.In DVB-T2 specification, its data bit element K (information bits), code word size N (codeword length), generator matrix G (generator matrix) and check can have following relation between matrix H (Parity-check matrix):

Information bit number: K

Code word size: N

Check bit number: N-K=M

Generator matrix (K × N):

Check matrix (M × N):

Relation between its code check and each parameter can show by following table one, and wherein Q represents in the system that each parallel processing unit has x bit Data disposal ability, the number of the submatrix of required parallel processing:

Code check	K	N	Q＝(N-K)/X
				1/2	32400	64800	90
3/5	38880	64800	72
				2/3	43200	64800	60
3/4	48600	64800	45
				4/5	51840	64800	36
5/6	54000	64800	30

For simple and clear and easy-to-read is understood, describing of an embodiment in the present invention will be carried out with the specification of DVB-T2 below.It should be noted, though quote the use being defined as explanation in DVB-T2 in the present embodiment, do not represent that applicant has a mind to carry out the present invention the limit of any application standard or specification.Chat bright sincerely.

Theory introduction about the LDPC code being applied to DVB-T2 please refer to following file:

[1]R.Gallager，Low-Density Parity-Check Codes，Cambridge，MA：MIT Press，1963.

[2]M.luby，M.Mitzennmacher，A.Shokrollahi，D Spielman，and V.Stemann，“Practical Loss-resillent codes”，1997.

[3] Hau Thien Tran, " low-density parity-check decoder and its coding/decoding method " application for a patent for invention publication number CN1822509, publication date 2006/8/23.

The framework of low density parity check code can be depicted bilateral figure (Bipartite graph) as and be called that Tanner schemes.Fig. 1 .a is that LDPC encodes the schematic diagram of bilateral figure, be bit node (bit nodes) below bilateral figure, top is for checking node (check nodes), a line of a corresponding parity check matrix of bit node, namely the bit in corresponding coded word, one row of a corresponding parity check matrix of inspection node, namely represent a parity check equation.When segment length is close to infinity, each checks that node only connects the bit node of only a few, is therefore referred to as low-density.Wherein H=(hij) MxN is defined as the LDPC parity matrix that length is N.The quantity in the i-th row of parity matrix with binary values 1 is expressed as dv (i), and the quantity in the jth row of parity matrix with binary values 1 is expressed as dc (j).In this bilateral figure, the left node of parity matrix is bit variable (or being the back end (310) in adapted for decoding LDPC code signal), and right side node is then for checking equation (or checking node 320).By N number of variable node and M, this bilateral figure defined by H checks that node defines.Each variable node in N number of variable node 310 has accurate dv (i) limit (edge, such as limit 330) keyed jointing (link) back end and one or more inspection node (or back end) 310.Limit 330 connection data node vi312 shown in figure and inspection node cj322.The quantity dv on this limit (as shown in dv314) is defined as the degree (degree) of variable node i.Similar, M to check in node 320 each picks up and look into node and have the individual limit of accurate dc (j), connects this node and one or more variable node.The quantity dc on this limit is defined as the degree of this inspection node j.

The logarithm similar value ratio (log-likelihood ratio, LLR) of LDPC code is decoded in being mathematically expressed as follows:

First be LDPC code C={v/v=(V0 ..., Vn-1), vHT=0}, and the form of the reception vector of transmission signal (received vector) is

Y=(y0 ..., yn-1), then measure (metrics) of this passage may be defined as p (yi/vi=0), p (yi/vi=1), i=0 ..., N-1. then this LLR measured is defined as

$L_{\mathrm{metrics}}\left(i\right)=\mathrm{In}\frac{p\left(y_i\right|v_i=0)}{p\left(y_i\right|v_i=1)}$

Wherein in above-mentioned mathematical expression " ln " refer to that radix is the natural logrithm of e.Wherein vi is variable node, and for each variable node vi (variable node), the value of its LLR is defined as

$\mathrm{In}\frac{p(v_i=0|y_i)}{p(v_i=1|y_i)}=L_{\mathrm{metric}}\left(i\right)+\ln \frac{p(v_i=0)}{p(v_i=1)}$

Therefore, the external data (extrinsic information) about the inspection node Cj of limit (i, j) can following mathematical expression show:

$L_{\mathrm{check}}^n(i,j)=(-1)\left[\underset{e\∈E_c\left(j\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Π}}\mathrm{sign}\left(L_{\mathrm{var}}^{n-1}\left(e\right)\right)\right]\max *\left(\right\{-\left|L_{\mathrm{var}}^{n-1}\left(e\right)\right||e\∈E_c\left(j\right)\backslash \{(i,j)\left\}\right\})$

min ^*+(x，y)＝max ^*(x，y)＝max(x，y)+ln(1+exp(-|x-y|))

min ^*-(x，y)＝ln(exp(x)-exp(y))＝max(x，y)+ln(1-exp(-|x-y|))

Wherein for the external value of internal variable node, at inspection node Cj, j=0 ..., during the situation of M-1, while be defined as represent except sending (emitting) to except the limit of variable node Vi by inspection node Cj, all by checking the limit that node Cj sends.

After utilizing following Jacobi equation formula to simplify, the external data mathematical expression of abbreviation can be drawn:

$L_{\mathrm{check}}^n(i,j)\≈\left[\underset{e\∈E_c\left(j\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Π}}\mathrm{sign}\left(L_{\mathrm{var}}^{n-1}\left(e\right)\right)\right]\min \left(\right\{\left|\left(L_{\mathrm{var}}^{n-1}\left(e\right)\right||e\∈E_c\left(j\right)\backslash \{(i,j)\}\right\})$

min ^*(x ₁，…，x _N-1)＝min ^*-(min ^*+(x ₁，…，x _N)，x _N)

Through above-mentioned two formula abbreviations, can obtain external data mathematical expression is:

$L_{\mathrm{check}}^n(i,j)=(-1)\left[\underset{e\∈E_c\left(j\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Π}}\mathrm{sign}\left(L_{\mathrm{var}}^{n-1}\left(e\right)\right)\right]\max *\left(\right\{-\left|L_{\mathrm{var}}^{n-1}\left(e\right)\right||e\∈E_c\left(j\right)\backslash \{(i,j)\left\}\right\})$

Therefore, in summary, the external data value of variable node can following mathematical expression show:

$\mathrm{Compute}{L}_{\mathrm{check}}^n(e,a)={\min }^{*}({\mathrm{\α}}_{c\left(e\right),v\left(e\right)}\left(0\right)+{\mathrm{\β}}_{c\left(e\right),v\left(e\right)}\left(a\right),{\mathrm{\α}}_{c\left(e\right),v\left(e\right)}\left(1\right)+{\mathrm{\β}}_{c\left(e\right),v\left(e\right)}(a+1))$

$\mathrm{Compute}{L}_{\mathrm{var}}^n(e,a)=L_{\mathrm{metric}}^{v\left(e\right)}\left(a\right)+\underset{e^{\′}\∈E_v\left(v\left(e\right)\right)\backslash v_e)}{\mathrm{\Σ}}{L}_{\mathrm{check}}^n(e^{\′},a)$

Please as shown in Figure 2, for this debugger 106b2 application is minimum and to a QC-LDPC, algorithm checks that matrix carries out a better implementing procedure figure of computing.In step S201, this debugger 106b2 obtain with the product of this data matrix non-be 0 this inspection matrix.In step S202, this debugger 106b2 is decided by the unit-sized to the submatrix (sub-matrix) that this inspection matrix cuts in subsequent step, and the size of this submatrix can be broadcasted specification, the disposal ability of hardware parallel processor or the fitness of memory layout according to Different Ground and determine.The conformability of aforementioned memory layout, refers to the memory cell size etc. that different memory silicon intelligence wealth is planned, the layout character that can impact system effectiveness because unit access data amount is different.In S203, according to this unit-sized, this data matrix is divided into multiple submatrix, and produces the corresponding address data of each submatrix.In S204, utilize the correction algorithm meeting specific terrestrial broadcasting standard or different customer demand to carry out computing to these submatrixs, check matrix to produce a correction.In the present embodiment, this correction algorithm is realized with minimum and algorithm.Minimum and algorithm can with reference to people such as Jianguang Zhao in IEEE TRANSACTIONS ONCOMMUNICATIONS, VOL.53, NO.4, OnImplementation of Min-Sum Algorithm and Its Modifications for DecodingLow-Density Parity-Check (LDPC) Codes mono-literary composition delivered in APRIL 2005 periodical, and show with the external data value mathematical expression of variable node.

In step S205, this correction is checked that matrix is sent to this product comparator 106b1 by this debugger 106b2, compares again to carry out product with this data matrix.

In specific terrestrial broadcasting standard, the specification of the submatrix used for rectifying inspection matrix has defined.Such as in DVB-T2 standard, be 360 bits by the size definition of submatrix.But, with the inspection matrix of DVB-T2 standard, split this inspection matrix by needs 360 submatrixs.In other words, the hardware realizing this debug calculation needs at least 360 parallel arithmetic to store these submatrixs respectively.

In addition, aforesaid submatrix size may be inconsistent with the memory cell size planned in memory layout, and the speed accessing these submatrixs arbitrary is slowed down.Under this type of situation, these submatrixs of adjustment segmentation are further needed to be the mechanism of suitable size, to reduce the quantity of parallel arithmetic or to increase system effectiveness through with causing of memory layout.

Ask for an interview shown in Fig. 3 a and Fig. 3 b, for disclosed to the method schematic diagram of submatrix C addressing again.This submatrix C is the matrix of a MxM bit size, and when this inspection matrix is a QC-LDPC, then this submatrix C is a unit matrix or a rotational units matrix.Numerical value according to unit matrix exists only in the characteristic of leading diagonal, and except exceptional situation, any point on an axes of coordinates only should exist a corresponding numerical value, and its rotational units matrix is also same.Ask for an interview this submatrix C, in X-axis and Y-axis, only there is a matrix numerical value starting point respectively separately, its coordinate in X-axis is (x, 0), represents with index (index) x, the coordinate in Y-axis is set to (0, y), represent with index y.

First this method determines submatrix C to be divided into integral multiple n, to calculate the length M/n of each subdivision matrix.Afterwards by two indexes respectively compared with subdivision matrix length M/n, when index x is greater than M/n < x < 2M/n, x value is addressed in the second subdivision matrix, and x value is reset to x-(M/n).When index x is greater than 2M/n < x < 3M/n, x value is addressed in the 3rd subdivision matrix, and x value is reset to x-(2M/n).The x ' of addressing address again of index x value can represent by mathematical expression x '=x-N* (M/n), and wherein N is integer.Similar, as M/n < y < 2M/n, y value is addressed in the second subdivision matrix, and y value is reset to y-(M/n).When index y is greater than 2M/n < y < 3M/n, y value is addressed in the 3rd subdivision matrix, and y value is reset to y-(2M/n).The y ' of addressing address again of index y value can represent by mathematical expression y '=x-N* (M/n), and wherein N is integer.In the present embodiment, be that this submatrix is divided into two matrixes further, but as known in front explanation, and submatrix C can be divided into N number of subdivision matrix according to need.In the embodiment of a DVB-T2, because there is a rolling type displacement buffer (Barrel Shifter) in its standard architecture, row conversion (rowexchange) are carried out to this fundamental frequency ground broadcast signal and produces this QC-LDPC matrix, therefore aforementioned addressing method again can utilize this rolling type displacement buffer to implement, but certainly not as limit.

Asking for an interview shown in Fig. 3 c, is the flow chart of addressing method again of this submatrix.In step S301, first calculate the length M/n of a subdivision matrix, and the matrix number n that this submatrix C is split.In step S302, Comparative indices x and subdivision matrix length M/n, to produce the ratio of x and subdivision matrix length.In step S303, carry out one first addressing step again, determine x deallocation is in what subdivision matrix.In step S304, carry out one second addressing step again, then addressing index x ' can mathematical expression x '=x-N* (M/n) performance.In step S305, first carry out addressing again for this index y, determine y deallocation is in what subdivision matrix.In step S306, one second addressing step again, its addressing index y again ' can represent by mathematical expression y '=y-N* (M/n).The submatrix checked in matrix cutting can process by this debugger 400, then according to addressing index again, the subdivision matrix after process is reduced to submatrix.Therefore according to the quantity n of subdivision matrix, the quantity of parallel processor in debugger can be reduced to original 1/n, significantly reduce the hardware cost realized needed for QC-LDPC decoding.

Figure 4 shows that the embodiment schematic diagram of the disclosed debugger of addressing again and again 400.This debugger 400 comprises memory 401, controller 402 and multiple parallel processor 403a, 403b ~ 403n.This controller 402 has first information passage 404,1 second information channel 405 and an addressing passage 406.This controller 402 is electrically connected with this memory 401 through this first information passage 404 and this addressing passage 406.This controller 402 is electrically connected with these parallel processor 403a ~ 403n respectively through this second information channel 405.In time carrying out debug computing, one checks that matrix is stored in this memory 401, and for DVB-T2 form, this inspection matrix is that address format that the submatrix size that defines with DVB-T2 standard and these submatrixs are corresponding is respectively stored in this memory 401.Therefore store these submatrixs multiple in this memory 401, each submatrix at least has an axle index, and on a plane coordinates, each submatrix has an x-axis index and a y-axis index, respectively the starting point of numerical value in x-axis and y-axis in corresponding each submatrix.In carrying out except staggering the time, first this controller 402 confirms each submatrix to be divided into several subdivision matrix, validation testing is the sum comparing these submatrixs and these parallel processor, as these submatrixs be 2 to 1 with the total ratio of these parallel processor time, a submatrix should be cut into two subdivision matrixes by expression.As these submatrixs be 3 to 1 with the ratio of these parallel processor time, a submatrix should be cut into three subdivision matrixes by expression.After confirming cutting ratio, the x-axis index of these submatrixs and y-axis index, by these corresponding address of these submatrixs corresponding, are taken out through this addressing passage by this controller 402 respectively.Afterwards, utilize prior figures 3 take off Zhu and roll over addressing method again, through these x-axis indexs of these submatrixs corresponding and y-axis index by after these submatrixs again addressing, be divided into multiple subdivision matrix separately.

In the present embodiment, as these submatrixs are cut into two subdivision matrixes separately, then by these submatrixs, the addressing address again corresponding to each self-corresponding first subdivision matrix is defined as an odd address group.Similarly, by these submatrixs, the group of addressing address again corresponding to each self-corresponding second subdivision matrix is defined as an even address group.And by parallel for these first subdivision matrixes corresponding to the group of this odd address, respectively input these parallel processor 403a ~ 403n carry out debug calculation process.After these first subdivision matrixes complete process, the data of these the first subdivision matrixes corresponding after debug calculation are filled out back these corresponding address in this memory 401 by this controller 402.After this, these parallel processor of the parallel input of these the second subdivision matrixes 403a ~ 403n corresponding to this even address group is carried out debug calculation process by this controller 402, the data of these the second subdivision matrixes corresponding is filled out back these corresponding address in this memory 401 after completing debug calculation.After these first subdivision matrixes and these the second subdivision matrixes complete process separately, these these first subdivision matrixes of controller 402 merging treatment and these the second subdivision matrixes complete debug calculate after numerical value, wherein fill out back these first subdivision matrixes of this memory 401 and these the second subdivision matrixes respectively by these submatrixs having formed debug calculation in this memory of correspondence, realize calculating the debug of these submatrixs with this.More specifically, this again addressing debugger 400 in complete these first subdivision matrixes and these the second subdivision matrixes debug calculation after, the corresponding address of each submatrix in this memory 401 can be utilized, accessed each submatrix of debug process.

In the present embodiment, the debug calculation of this controller 402 implements with minimum and algorithm, and minimum and algorithm asks for the minimum value of x-axis and y-axis in these submatrixs respectively to complete debug calculation.In other words, in the example utilizing minimum and algorithm enforcement debug calculation, this controller 402 reads the first subdivision matrix and second subdivision matrix of corresponding each submatrix, ask for the minimum value of x-axis and y-axis in this first subdivision matrix of a corresponding submatrix respectively, and the minimum value of x-axis and y-axis in this second subdivision matrix of corresponding same submatrix, and the minimum value of this first subdivision matrix and this second subdivision matrix is once compared again, obtain the minimum value of x-axis and y-axis in this first subdivision matrix and this second subdivision matrix to complete merging treatment program.

The aforementioned parallel processing program to these first subdivision matrixes and these the second subdivision matrixes, in an embodiment, refers under same work clock pulse, synchronously processes these first subdivision matrixes and these the second subdivision matrixes.But from not as limit, under tolerable error condition, certain hour difference can be had to the process of these the first subdivision matrixes.Or, also these the first subdivision matrixes can be further divided into multiple matrix group and send into these parallel processor 403a ~ 403n process respectively, again can lower the hardware resource realized needed for the parallel decoding of QC-LDPC.

Figure 5 shows that the embodiment schematic diagram of disclosed another addressing decoders 500 again.This decoder 500 comprises a memory 501, again and again addressing controller 502, tubbiness shifter 503a, an internal network connection control device 503b and multiple parallel processor 504a, 504b ~ 504n.This memory 501 comprises multiple memory cell 501a, 501b ~ 501n.The size of these memory cells 501a, 501b ~ 501n, determines according to the memory cell size using different memory silicon intelligence wealth to plan.This again addressing controller 502 be electrically connected through one first addressing passage 505 and this memory 501, and to be electrically connected with this inner connection control device (interconnection network controller) 503b through one second addressing passage 506.This tubbiness shift unit (barrelshifter) 503a, is electrically connected with this memory 501 through one first data channel 507, and is electrically connected with these parallel processor 504a, 504b ~ 504n through one second data channel 508.

In time carrying out debug computing, one checks that matrix is stored in this memory 501, for DVB-T2 form, the submatrix size that this inspection matrix defines with DVB-T2 standard and the corresponding respectively address format of these submatrixs corresponding in each memory cell of this memory 501 respectively.In the present embodiment, the size of each memory cell is identical with the size of each submatrix, and each submatrix is accordingly stored in each memory cell.Therefore in each work clock pulse, at least can being intactly accessed by these memory cells of these submatrixs.Each submatrix has an x index and a y index, respectively the starting point of numerical value in x-axis and y-axis in corresponding each submatrix.

This is addressing controller 502 again, and in carrying out first confirming each submatrix to be divided into several subdivision matrix except staggering the time, validation testing is the sum comparing these submatrixs and these parallel processor.After confirming cutting ratio, this again addressing controller 502 be stored in the corresponding address of these memory cells by these submatrixs corresponding, through this first addressing passage, the x index of these submatrixs and y index are taken out respectively.Afterwards, utilize the addressing method again that prior figures 3 discloses, through these x indexs and the y index of these submatrixs corresponding, by the addressing again of the subdivision matrix of these submatrixs, to produce these addressing address again corresponding to these subdivision matrixes, and be defined as corresponding address group.In the present embodiment, be each submatrix is divided into accordingly one first address group and one second address group.

Afterwards, this again addressing controller 502 this first address group and this second address group are sent to this internal network controller 503b.These first subdivision matrixes corresponding to this first address group are inputted these parallel processor 504a, 504b ~ 504n and carry out debug calculation process to produce one first debug result by this internal network controller 503b abreast, and this first debug result is stored in this tubbiness shift unit 503a.After these first subdivision matrixes complete process, these second subdivision matrixes corresponding to this second address group are inputted these parallel processor 504a ~ 504n and carry out debug calculation process to produce one second debug result by this internal network controller 503b abreast.In the present embodiment, for realizing the QC-LDPC decoding under DVB-T2 framework, this tubbiness shift unit 503a, according to this first debug result and this second debug result, utilizes address displacement that submatrix is converted to cell matrix, to complete debug calculation.In the present embodiment, this again the debug calculation of addressing controller 502 be implement with minimum and algorithm.

Though in previous embodiment, disclose the step that when carrying out debug calculation each submatrix first must be confirmed to be divided into several subdivision matrix, but under a mounting hardware framework, this step can after designer considers the parameter such as aforementioned memory layout, parallel processor quantity, directly be set in hardware structure, or in advance to write in the software set (such as firmware) of control hardware running.Do not need the judgement performing above-mentioned confirmation dividing number again when therefore performing debug calculation, can the processing time be reduced and increase system effectiveness.

The aforementioned parallel processing program to these first subdivision matrixes and these the second subdivision matrixes, in an embodiment, refers under same work clock pulse, synchronously processes these first subdivision matrixes and these the second subdivision matrixes.But from not as limit, under tolerable error condition, to the process of these the first subdivision matrixes so that certain hour difference can be had.Or, also these the first subdivision matrixes can be further divided into multiple matrix group and send into these parallel processor 503a ~ 503n process, again can lower the hardware resource realized needed for the parallel decoding of QC-LDPC.

Separately, though aforesaid embodiment is in time carrying out addressing operation again, be take out x index and y index is decoded to realize QC-LDPC parallel processing simultaneously.But it should be understood that under other enforcement states, x index or y index also can be utilized separately to realize aforementioned parallel decoding.For example, in the enforcement of DVB-T2 standard, when standard submatrix quantity is 360, when the number as these parallel processor is 180, only need to utilize y index can realize aforementioned parallel processing decoding, the efficiency of further elevator system when reducing operand.

Though foregoing embodiments is using DVB-T2 as representing, being so familiar with the art person can apparent, use QC-LDPC code as coding the change of DVB-C2 and DVB-S2, also be intended to by the present invention announcement and the scope protected.

In sum, although the present invention with preferred embodiment disclose dew as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when being defined by claims.

Claims (20)

1. addressing decoders again and again, is applied to the decoding of quasi-cyclic low-density parity check codes, comprises:

One memory, stores loop coding matrix surely, and this accurate loop coding matrix comprises multiple submatrix, and each submatrix has a corresponding address;

One controller, the more each submatrix of addressing is multiple subdivision matrix, and define in these subdivision matrixes to one first address group or one second address group; And

Multiple parallel processor, be coupled to this controller, debug calculation is carried out to these subdivision matrixes being defined in this first address group and these subdivision matrixes of being defined in this second address group, to produce one first debug result and one second debug result, the sum of these parallel processor and be defined in this first address group these subdivision matrixes sum or be defined in this second address group these subdivision matrixes sum between be integer ratio relation.

2. addressing decoders more as claimed in claim 1, it is characterized in that, this controller determines that at least one axle index of each submatrix is to carry out addressing again to these submatrixs.

3. addressing decoders more as claimed in claim 2, is characterized in that, comprises an x-axis index and a y-axis index of corresponding each subdivision matrix in this first debug result and this second debug result respectively.

4. addressing decoders more as claimed in claim 1, it is characterized in that, ratio between each submatrix and these subdivision matrixes corresponding to each submatrix is one first ratio, ratio between the sum of the sum of these submatrixs and these parallel processor is one second ratio, is integer ratio relation between this first ratio and this second ratio.

5. addressing decoders more as claimed in claim 1, is characterized in that, these parallel processor implement debug calculation with minimum and algorithm, and the minimum value compared respectively in this first debug result and this second debug result is calculated to complete debug.

6. addressing decoders more as claimed in claim 3, it is characterized in that, the total amount of this submatrix is 360, and the total amount of these parallel processor is 180, and these parallel processor carry out debug calculation with these y-axis indexs that each subdivision matrix is corresponding.

7. addressing decoders more as claimed in claim 3, it is characterized in that, the total amount of this submatrix is 360, and the total amount of these parallel processor is 120, and these parallel processor carry out debug calculation with these x-axis indexs corresponding to each subdivision matrix and these y-axis indexs.

8. addressing decoders more as claimed in claim 1, it is characterized in that, this controller also comprises again and again addressing controller and a tubbiness shift unit, this again addressing controller produce this first debug result and this second debug result, each submatrix, according to this first debug result and this second debug result, is converted to cell matrix by address displacement by this tubbiness shift unit.

9. addressing decoders more as claimed in claim 1, it is characterized in that, this memory comprises multiple memory cell, and each submatrix is stored in one of these memory cells.

10. addressing decoders more as claimed in claim 1, it is characterized in that, when each submatrix is a M*M matrix, to should the sum of these subdivision matrixes of the first address group and the ratio of the sum of these parallel processor be n time, the length of each subdivision matrix is M/n, one axle index of each submatrix compares with the length of these subdivision matrixes by this controller, when this axle index is less than M/n, this axle index is identical with these corresponding address of these submatrixs of these subdivision matrixes corresponding, this axle index is addressed in one first subdivision matrix, when this axle index is greater than M/n and is less than 2M/n, this axle desired value is addressed in one second subdivision matrix, and x-axis index is reset to x-axis desired value deducts M/n.

11. 1 kinds of addressing coding/decoding methods again, are applied to the decoding of quasi-cyclic low-density parity check codes, comprise the following step:

Store loop coding matrix surely, this accurate loop coding matrix comprises multiple submatrix, and each submatrix has a corresponding address;

According to a subdivision matrix sum, the more each submatrix of addressing is multiple subdivision matrix, and defines in these subdivision matrixes to one first address group or one second address group; And

By multiple parallel processor, debug calculation is carried out to these subdivision matrixes being defined in this first address group and these subdivision matrixes of being defined in this second address group, to produce one first debug result and one second debug result, the sum of these parallel processor and be defined in this first address group these subdivision matrixes sum or be defined in this second address group these subdivision matrixes sum between be integer ratio relation.

12. addressing coding/decoding methods more as claimed in claim 11, it is characterized in that, the more each submatrix of addressing are in the step of multiple subdivision matrix, also comprises the following step:

Determine at least one axle index of each submatrix, and according to each axle index, addressing is again carried out to these submatrixs.

13. addressing coding/decoding methods more as claimed in claim 12, is characterized in that, comprise an x-axis index and a y-axis index of corresponding each subdivision matrix in this first debug result and this second debug result respectively.

14. addressing coding/decoding methods more as claimed in claim 11, it is characterized in that, ratio between each submatrix and these subdivision matrixes corresponding to each submatrix is one first ratio, ratio between the sum of the sum of these submatrixs and these parallel processor is one second ratio, integer ratio relation between this first ratio and this second ratio.

15. addressing coding/decoding methods more as claimed in claim 14, is characterized in that, these parallel processor implement debug calculation with minimum and algorithm, compare the minimum value of this first debug result and this second debug result to complete debug calculation.

16. addressing coding/decoding methods more as claimed in claim 14, it is characterized in that, the total amount of these submatrixs is 360, and the total amount of these parallel processor is 180, and these parallel processor carry out debug calculation with these y-axis indexs that each subdivision matrix is corresponding.

17. addressing coding/decoding methods more as claimed in claim 14, it is characterized in that, the total amount of this submatrix is 360, and the total amount of these parallel processor is 120, and these parallel processor carry out debug calculation with these x-axis indexs corresponding to each subdivision matrix and these y-axis indexs.

18. addressing coding/decoding methods more as claimed in claim 14, is characterized in that, also comprise the following step:

According to this first debug result and this second debug result, by address displacement, each submatrix is converted to cell matrix.

19. addressing coding/decoding methods more as claimed in claim 11, it is characterized in that, each submatrix correspondence is stored in one of multiple memory cell.

20. addressing coding/decoding methods more as claimed in claim 11, it is characterized in that, the each submatrix of addressing is in the step of multiple subdivision matrix again, when each submatrix is a M*M matrix, and to should the sum of these subdivision matrixes of the first address group and the ratio of the sum of these parallel processor be n time, the length of each subdivision matrix is M/n, one axle index of each submatrix is compared with the length M/n of these subdivision matrixes, when this axle index is less than M/n, this axle index is identical with these corresponding address of these submatrixs of these subdivision matrixes corresponding, this axle index is addressed in one first subdivision matrix, when this axle index is greater than M/n and is less than 2M/n, this axle desired value is addressed in one second subdivision matrix, and x-axis index is reset to x-axis desired value deducts M/n.