CN102738218A - Integrated circuit and manufacturing method thereof - Google Patents

Integrated circuit and manufacturing method thereof Download PDF

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Publication number
CN102738218A
CN102738218A CN2011104260555A CN201110426055A CN102738218A CN 102738218 A CN102738218 A CN 102738218A CN 2011104260555 A CN2011104260555 A CN 2011104260555A CN 201110426055 A CN201110426055 A CN 201110426055A CN 102738218 A CN102738218 A CN 102738218A
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metal structure
width
diffusion zone
distance
ratio
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CN102738218B (en
Inventor
阿里·凯沙瓦齐
郭大鹏
宋淑惠
曾祥仁
林学仕
鲁立忠
吴忠政
田丽钧
杨荣展
陈淑敏
曹敏
侯永清
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US13/086,186 external-priority patent/US9312260B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Abstract

The invention discloses an integrated circuit which includes a first diffusion area for a first type transistor. The first diffusion area includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second diffusion area includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Description

Integrated circuit and manufacturing approach thereof
The cross reference of related application
The application is that the U.S. Patent Application Serial Number of submitting on May 26th, 2010 that is called " INTERGRATED CIRCUITSAND MANUFACTURING METHODS THEREOF (integrated circuit and manufacturing approach thereof) " is No.12/787; 966 the part application case that continues, its content all is hereby expressly incorporated by reference.
Technical field
The present invention relates generally to field of semiconductor devices, relates in particular to integrated circuit and the method that forms integrated circuit.
Background technology
Semiconductor integrated circuit (IC) industry has experienced fast development.The technological progress of IC material and design has produced many for IC, and wherein, each generation all has than last Dai Gengxiao and complicated circuitry more.Yet these progressive complexity of handling and making IC that increased are for these progressive, as to need IC to handle and make similar development that will realize.
In the IC evolution process, functional density (that is, the quantity of the interconnect devices of every chip area) increases usually, and physical dimension (that is, using manufacturing to handle the minimal parts (or line) that can create) reduces simultaneously.This reduces to handle usually in proportion provides benefit through increasing production efficiency and reducing relevant cost.Thisly reduce also to produce high relatively power consumption value in proportion, it can use low power consumption device (such as, complementary metal oxide semiconductors (CMOS) (CMOS) device) to solve.
Summary of the invention
According to an aspect of the present invention, a kind of integrated circuit is provided, comprises: be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone; Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone; Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously; First metal structure is electrically connected with said first drain region; Second metal structure is electrically connected with said second drain region; And the 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the width of said first metal structure is equal to or greater than the width of said the 3rd metal structure basically.
Preferably, the ratio of the width of the width of said first metal structure and said the 3rd metal structure changed in about 2: 1 scope at about 1: 1.
Preferably, the ratio of the width of the width of said first metal structure and said the 3rd metal structure changed in about 1.6: 1 scope at about 1.3: 1.
Preferably, said first metal structure and said second metal structure are extended to opposite edges from the edge of said first diffusion zone and said second diffusion zone respectively on said wiring direction basically continuously.
Preferably, this integrated circuit further comprises: the 4th metal structure is electrically connected with said first source area; And five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, Said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction, and said first distance is greater than said second distance.
Preferably; Said first diffusion zone has first width; Said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1.
Preferably, the width of said the 4th metal structure and said five metals belong to structure the ratio of width at about 1: 1 in about 2: 1 scope.
Preferably, the width of said the 4th metal structure and said five metals belong to structure the ratio of width at about 1.3: 1 in about 1.6: 1 scope.
Preferably, this integrated circuit further comprises: the 6th metal structure is electrically connected with said second source area; And the 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, Said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction, and said the 3rd distance is greater than said the 4th distance.
Preferably; Said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope.
Preferably, the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 2: 1 scope at about 1: 1.
Preferably, the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
According to a further aspect in the invention, a kind of integrated circuit is provided, comprises: be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone; Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone; Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously; First metal structure is electrically connected with said first drain region; Second metal structure is electrically connected with said second drain region; The 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the ratio of the width of the width of said first metal structure and said the 3rd metal structure arrived in about 1.6: 1 scope at about 1.3: 1; The 4th metal structure is electrically connected with said first source area; And five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, Said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction, and said first distance is greater than said second distance.
Preferably; Said first diffusion zone has first width; Said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1.
Preferably, the width of said the 4th metal structure and said five metals belong to structure the ratio of width at about 1.3: 1 in about 1.6: 1 scope.
Preferably, this integrated circuit further comprises: the 6th metal structure is electrically connected with said second source area; And the 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, Said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction, and said the 3rd distance is greater than said the 4th distance.
Preferably; Said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope.
Preferably, the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
According to another aspect of the invention, a kind of integrated circuit is provided, comprises: be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone; Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone; Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously; First metal structure is electrically connected with said first drain region; Second metal structure is electrically connected with said second drain region; The 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the ratio of the width of the width of said first metal structure and said the 3rd metal structure is between about 1.3: 1 to about 1.6: 1; The 4th metal structure is electrically connected with said first source area; Five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, Said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction, and said first diffusion zone has first width; Said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1; The 6th metal structure is electrically connected with said second source area; And the 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, Said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction, said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope.
Preferably; The ratio that the width of said the 4th metal structure and said five metals belong to the width of structure arrived in about 1.6: 1 scope at about 1.3: 1, and the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
Description of drawings
When combining accompanying drawing to read, can understand the present invention better according to following detailed description.Should be emphasized that according to the standard practices in the industry, various parts are drawn in proportion and only are used for illustrative purposes.In fact, in order clearly to discuss, the quantity of various parts and size can be by any increase or minimizings.
Figure 1A is the sketch map that the representative configuration layer of typical integrated circuit is shown.
Figure 1B is the cross-sectional view along the typical integrated circuit of the hatching 1B-1B shown in Figure 1A.
Fig. 2 A is the sketch map that the representative configuration layer of another typical integrated circuit is shown.
Fig. 2 B is the cross-sectional view along the typical integrated circuit of the hatching 2B-2B shown in Fig. 2 A.
Fig. 3 is the flow chart that the typical method that forms integrated circuit is shown.
Fig. 4 A-Fig. 4 E is the schematic cross section that illustrates along another typical method of the formation integrated circuit of the hatching 2B-2B intercepting shown in Fig. 2 A.
Fig. 5 illustrates the sketch map that comprises the system that is arranged on the typical integrated circuit on the substrate.
Fig. 6 is the sketch map that the representative configuration layer of typical integrated circuit is shown.
Embodiment
For cmos device, contact plunger is generally used for the electrical connection between transistorized source/drain (S/D) district and the metal level M1.Usually, contact plunger is arranged in the contact hole, and contact hole is formed in interlayer dielectric (ILD) layer.The contact hole that is marked on the mask layer is foursquare.Square pattern on the mask layer is transferred on the ILD layer and becomes round.Thereby, from seeing that with the surperficial rectangular top view that is formed with transistorized wafer contact plunger has circular shape.Find that if the geometry of cmos device reduces in proportion, then transistorized S/D impedance increases.The S/D impedance infringement transistor that increases or the electric property of circuit, for example, operating current, speed, frequency etc.
Should be understood that following description is provided for realizing a plurality of different embodiment or the instance of the different characteristic of this disclosure.The particular instance of below describing assembly and configuration is to simplify this disclosure.Certainly, these only are instances and are not used in restriction.In addition, this disclosure can be in multiple instance repeat reference numerals and/or letter.This be recycled and reused for simplify and clearly purpose and itself do not represent various embodiments and/or the configuration discussed between relation.And; Parts in following disclosure are formed on another parts, are connected to another parts and/or are bonded to another parts and can comprise that a plurality of parts directly contact the embodiment of formation; And can comprise through inserting a plurality of parts and form optional feature, make the embodiment that parts can directly not contact.In addition; But usage space relative terms; For example; " lower ", " higher ", " level ", " vertically ", " on ", " under ", " making progress ", " downwards ", " top ", " bottom " etc., with and derivative (for example " flatly ", " downwards ", " up " etc.), with the relation of parts and another parts in easy this disclosure of description.This space relative terms is intended to cover the different orientations of the equipment that comprises a plurality of parts.
Figure 1A is the sketch map that the representative configuration layer of typical integrated circuit is shown.Typical figure shown in Figure 1A only shows the overlapping of diffusion layer, gate electrode layer and metal structure.In Figure 1A, integrated circuit 100 can comprise the P transistor npn npn 101 that is electrically connected with N transistor npn npn 105.In certain embodiments; Integrated circuit 100 can be digital circuit, analog circuit, mixed signal circuit, static RAM (SRAM) circuit, embedded SRAM circuit, dynamic random access memory (DRAM) circuit, embedded DRAM circuit, Nonvolatile memory circuit (for example, FALSH, EPROM, E 2PROME, field programmable gate circuit) or its any combination.In certain embodiments, P transistor npn npn 101 can be configured in inverter, logic gates, amplifier, charge pump circuit with N transistor npn npn 105 or have in any circuit of cmos device.
With reference to Figure 1A, integrated circuit 100 can comprise diffusion zone 110 and 120.Diffusion zone 110 can comprise the source area 111 and drain region 113 of P transistor npn npn 101.Diffusion zone 120 can comprise the source area 121 and drain region 123 of N transistor npn npn 105.Diffusion zone 110 can be isolated through isolation structure 115 and diffusion zone 120.Isolation structure 115 can comprise that shallow trench isolation leaves (STI) structure and/or local oxidation of silicon (LOCOS) structure.In certain embodiments, diffusion zone 110 and 120 width W 1And W 2Different respectively.In other embodiments, the width W of diffusion zone 110 1Width W greater than diffusion zone 120 2
With reference to Figure 1A, gate electrode 130 can stride across diffusion zone 110 and 120 and extend continuously on the wiring direction of gate electrode 130.In certain embodiments, gate electrode 130 can comprise gate electrode part 130a and the 130b that is respectively applied for P transistor npn npn 101 and N transistor npn npn 105. Gate electrode part 130a and 130b can be configured to receive respectively switching on and off of voltage, control P transistor npn npn 101 and N transistor npn npn 105.Notice that the wiring direction shown in Figure 1A only is exemplary.In other embodiments, wiring direction can be a horizontal direction or with respect to any direction of inclined.
Refer again to Figure 1A, metal structure 140 can be electrically connected with the source area 111 of P transistor npn npn 101.Metal structure 140 and diffusion zone 110 can be on wiring direction overlap distance D 1Metal structure 150 can be electrically connected with the drain region 113 and 123 of P transistor npn npn 101 and N transistor npn npn 105 respectively.Metal structure 150 and diffusion zone 110 overlap distance D on wiring direction 2Distance B 1Greater than distance B 2In certain embodiments, metal structure 140 directly contacts with source area 111.Metal structure 150 and drain region 113 directly contact with 123.
With reference to Figure 1A, metal structure 160 can be electrically connected with the source area 121 of N transistor npn npn 101.Metal structure 160 and diffusion zone 120 can be on wiring direction overlap distance D 3Metal structure 150 and diffusion zone 120 can be on wiring direction overlap distance D 4In certain embodiments, distance B 3Greater than distance B 4In other embodiments, distance B 3Greater than distance B 2In certain embodiments, metal structure 160 directly contacts with source area 121.
Notice that the structure shown in Figure 1A only is schematic.In certain embodiments, distance B 1And D 2Summation can equal width W basically 1In other embodiments, distance B 1And D 2Summation can be greater than or less than width W 1In other embodiment that also have, distance B 3And D 4Summation can equal width W basically 2In other embodiment that also have, distance B 3And D 4Summation can be greater than or less than width W 2
Notice that also term " metal structure " can mean metal wire, wire, metal cord, metal string (metallic string), metal coding, laths of metal or any metal structure of extending preset distance continuously at this.In certain embodiments, metal structure 140,150 and 160 can be called as (M0) layer of metal zero (metallic zero).
In certain embodiments, distance B 1With width W 1Ratio between about 0.75: 1 and 1: 1, and distance B 2With width W 1Ratio between about 0.1: 1 and 0.33: 1.In other embodiments, distance B 3With width W 2Ratio between about 0.75: 1 and 1: 1, and distance B 4With width W 2Ratio between about 0.1: 1 and 0.33: 1.
Note, metal structure 140,150 and 160 each all can on diffusion zone 110 and/or 120, extend continuously at least in part, be used to be electrically connected each source area and drain region.Structure through extending continuously at least in part can reduce transistorized source/drain (S/D) impedance.
Should also be noted that distance B 2And D 4In each all do not extend to opposite edges 110b continuously and extend to opposite edges 120b continuously respectively from the edge 120a of diffusion zone 120 from the edge 110a of diffusion zone 110.Metal structure 150 not exclusively covers diffusion zone 110 and 120 on wiring direction.Through this structure, parasitic capacitance between gate electrode part 130 each in metal structure 140,150 and 160 and/or the parasitic capacitance between metal structure 140,150 and 160 can reduce.Through changing impedance and/or parasitic capacitance, can realize the electrical characteristics of integrated circuit 100 ideally, for example service speed, frequency of operation etc.
Table 1 illustrates the velocity simulation that is used at least one inverter and a plurality of finger (finger).As shown in table 1, D 1/ W 1, D 2/ W 1, D 3/ W 2And D 4/ W 2Be that 1/1 structure is as the basis.In the foundation structure each all has the metal structure 140,150 and 160 that on wiring direction, covers diffusion zone 110 or 120 fully.The simulation velocity of foundation structure is assumed to be 1.
Table 1
Figure BSA00000638867900081
Compare D with foundation structure 1/ W 1, D 3/ W 2Be 1/1 and D 2/ W 1, D 4/ W 2Be that 0.33/1 exemplary configurations can be respectively 1-finger, 4-finger and 24-finger structure 9.6%, 8.8% and 8.4% speed gain is provided, shown in middle column.D 1/ W 1, D 3/ W 2Be 0.75/1 and D 2/ W 1, D 4/ W 2Be that another exemplary configurations of 0.33/1 can provide 10.4%, 8.9% and 8.1% speed gain for 1-finger, 4-finger and 24-finger structure, shown in the row of the right side.Find D 1/ W 1, D 2/ W 1, D 3/ W 2And/or D 4/ W 2Modification and/or change the unexpected speed gain can realize inverter.
Figure 1B is the sectional view along the example integrated circuit of the hatching 1B-1B intercepting shown in Figure 1A.Notice that Figure 1A only illustrates a plurality of layout layers of integrated circuit 100.Sectional view shown in Figure 1B can be described the more multi-part of integrated circuit 100.
With reference to Figure 1B, P transistor npn npn 101 can be formed on the substrate 103 with N transistor npn npn 105.Notice that P transistor npn npn 101 can be separated by isolation structure 115 with N transistor npn npn 105.In certain embodiments, substrate 103 can comprise basic semi-conducting material, compound semiconductor materials, alloy semiconductor material or any other suitable material or its combination.Basic semi-conducting material can comprise silicon or germanium crystal, many crystalline solid or impalpable structure.Compound semiconductor materials can comprise carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and indium antimonide.The alloy semiconductor material can comprise SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP.In one embodiment, the alloy semiconductor substrate can have inclination SiGe parts, and wherein, Si and Ge composition are changed into another ratio of another position from a ratio of a position.In another embodiment, alloy SiGe is formed on the silicon substrate.In another embodiment, the SiGe substrate is tightened up (strain).And semiconductor substrate can be a semiconductor-on-insulator, such as, silicon-on-insulator (SOI) or thin-film transistor (TFT).In some instances, semiconductor substrate can comprise the epitaxial loayer or the buried layer of doping.In other instances, compound semiconductor substrate can have sandwich construction, and perhaps substrate can comprise the multilayer compound semiconductor structure.
In certain embodiments, N type well region 107 and/or P type well region 109 can optionally be formed on the substrate 103 that is used for P transistor npn npn 101 and N transistor npn npn 105 respectively.N type well region 107 can have alloy, such as arsenic (As), phosphorus (P), other V group elements or its any combination.P type well region 109 can have alloy, such as boron (B) and/or other iii group elements.
With reference to figure 2B, P transistor npn npn 101 can comprise source area 111 and drain region 113.In certain embodiments, source area 111 can comprise structure 111c or 113c respectively with drain region 113, and it provides pressure can for the raceway groove (unmarked) of P transistor npn npn 101.The raceway groove of pressurized can change the mobility of charge carrier wherein, the feasible electric characteristic that changes P transistor npn npn 101, for example electric current.In certain embodiments, structure 111c in source area 111 and the drain region 113 and 113c can be called protruding source electrode and protruding drain electrode respectively.In other embodiments, each among structure 111c and the 113c can comprise single SiGe or Si xGe 1-xLayer, multilayer SiGe or Si xGe 1-xStructure, epitaxial structure, compound-material structure, can change other materials or its any combination of the mobility of carrier of P transistor npn npn 101.
In certain embodiments, source area 111 can optionally comprise P type lightly doped drain (LDD) 111a and 113a respectively with drain region 113.Among P type LDD 111a and the 113a each can have the type dopant opposite with N type well region 107.In other embodiments, source area 111 can comprise silicide area 111b and 113b respectively with drain region 113.Silicide area 111b and 113b can comprise at least a material; Such as, nickle silicide (NiSi), nickel Platinum Silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanosilicided (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), silication iridium (IrSi), silication erbium (ErSi), cobalt silicide (CoSi), other suitable materials or its any combination.
Refer again to Fig. 2 B, gate electrode part 130a can comprise interface dielectric layer 117a.Interface dielectric layer 117a can be arranged on the substrate 103.Interface dielectric layer 117a can comprise such as materials such as silica, silicon nitride, silicon oxynitride, other grid dielectric materials or other any combinations.
In certain embodiments, gate electrode part 130a can comprise sandwich construction 131, and it can comprise at least one high-k (layer of height-k) and at least one metal work function layer.At least one height-k dielectric layer can be formed on the boundary layer 117a.Height-k dielectric layer can comprise height-k dielectric material, such as, HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable height-k dielectric material or its any combination.In certain embodiments, height-k material can further be selected from nitrogen oxide, metal aluminate, zirconium silicate, zirconium aluminate, silica, silicon nitride, silicon oxynitride, zirconia, titanium oxide, aluminium oxide, hafnium oxide-aluminium oxide alloy, other suitable materials or its any combination of metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal.
In certain embodiments, at least one metal work function layer of sandwich construction 131 can comprise at least one P metal work function layer and at least one N metal work function layer.In other embodiments, at least one metal work function layer of gate electrode part 130a can comprise at least one P metal work function layer independently, and has no N metal work function layer.In certain embodiments, P type work function material can comprise the composition such as ruthenium, palladium, platinum, cobalt, nickel and conducting metal oxide and/or other suitable materials.N type metal material can comprise the composition such as hafnium, zirconium, titanium, tantalum, aluminium, metal carbides (for example, hafnium carbide, zirconium carbide, titanium carbide, aluminium carbide), aluminide and/or other suitable materials.
In certain embodiments, sandwich construction 131 can comprise at least one diffusion barrier layer.At least one diffusion barrier layer can be arranged between grid dielectric material and the workfunction metal material.Diffusion barrier layer can be configured to prevent that the metal ion of workfunction metal material is diffused in the grid dielectric material.Diffusion barrier layer can comprise at least a material, such as, aluminium oxide, aluminium, aluminium nitride, titanium, titanium nitride (TiN), tantalum, tantalum nitride, other suitable materials and/or its combination.
With reference to Figure 1B, gate electrode part 130a can comprise conductive layer 135a.Conductive layer 135a can be centered on by sandwich construction 131.Conductive layer 135a can be processed by at least a material, such as, aluminium, copper, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO 2, and/or other suitable materials.
Refer again to Figure 1B, N transistor npn npn 105 can comprise source area 121 and drain region 123.In certain embodiments, source area 121 can optionally comprise N type lightly doped drain (LDD) 121a and 123a respectively with drain region 123. N type LDD 121a and 123a can have the type dopant opposite with P type well region 108.In other embodiments, source area 121 can comprise silicide area 121b and 123b respectively with drain region 123. Silicide area 121b and 123b can have and silicide area 111b and the same or analogous metal material of 113b.
In other embodiments, source area 121 includes the pressure texture (not shown) with drain region 123.Pressure texture can change the mobility of carrier in the raceway groove of N transistor npn npn 105.In certain embodiments, each in the pressure texture can comprise single SiC or Si xC 1-xLayer, multilayer SiC or Si xC 1-xStructure, epitaxial structure, compound-material structure, can change other materials or its any combination of the mobility of carrier of N transistor npn npn 105.
Refer again to Fig. 2 B, gate electrode part 130b can comprise interface dielectric layer 117b.Interface dielectric layer 117b can be arranged on the substrate 103.Interface dielectric layer 117b can comprise the material such as silica, silicon nitride, silicon oxynitride, other grid dielectric materials and/or its combination.
In certain embodiments, gate electrode part 130b can comprise sandwich construction 133, and it can comprise at least one high-k (layer of height-k) and at least one metal work function layer.At least one height-k dielectric layer can be formed on the boundary layer 117b.What in certain embodiments, at least one height-k dielectric layer of sandwich construction 133 can be with sandwich construction 131 is same or similar.
In certain embodiments, at least one metal work function layer of gate electrode part 130b comprises at least one N type metal work function layer, and has no P type metal work function layer.In certain embodiments, N type metal material can comprise the composition such as hafnium, zirconium, titanium, tantalum, aluminium, metal carbides (for example, hafnium carbide, zirconium carbide, titanium carbide, aluminium carbide), aluminide and/or other suitable materials.
In certain embodiments, sandwich construction 133 can comprise at least one diffusion barrier layer.At least one diffusion barrier layer can be arranged between grid dielectric material and the workfunction metal material.Diffusion barrier layer can be configured to prevent that the metal ion of workfunction metal material is diffused in the grid dielectric material.Diffusion barrier layer can comprise at least a material, such as, aluminium oxide, aluminium, aluminium nitride, titanium, titanium nitride (TiN), tantalum, tantalum nitride, other suitable materials and/or its combination.
With reference to Figure 1B, gate electrode part 130b can comprise conductive layer 135b.Conductive layer 135b can be centered on by sandwich construction 133.Conductive layer 135b can be by processing with the same or analogous at least a material of conductive layer 135a.
With reference to Figure 1B, spacer 141a and 141b can optionally be arranged on the sidewall of gate electrode part 130a and 130b respectively.Spacer 141a and 141b can be processed by at least a material, such as, silica, silicon nitride, silicon oxynitride, other dielectric materials or its any combination.
With reference to Figure 1B, at least one dielectric layer 151 can be arranged on the substrate 103 and center on spacer 141a and 141b.At least one dielectric layer 151 can comprise at least a material; Such as, phosphorous doped silicon silicate glass (PSG), boron-doping silicon silicate glass (BSG), boron phosphorous doped silicon silicate glass (BPSG), undoped silicate glass (USG), silica, silica, silicon nitride, silicon oxynitride, low-k dielectric material, other dielectric materials or its combination.
In certain embodiments, at least one etching stopping layer (ESL) 153 can be arranged at least one dielectric layer 151.At least one ESL 153 can comprise at least a material, such as, silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide, other dielectric materials or its any combination.
With reference to Figure 1B, at least one dielectric layer 153 can be arranged at least one ESL 153.At least one dielectric layer 153 can comprise at least a material; Such as; Silica; For example, plasma enhanced oxidation thing (PEOX), undoped silicate glass (USG), phosphorous doped silicon silicate glass (PSG), boron-doping silicon silicate glass (BSG), boron phosphorous doped silicon silicate glass (BPSG), silica, silica, silicon nitride, silicon oxynitride, low-k dielectric material, other dielectric materials or its combination.
In Figure 1B, metal structure 140,150 and 160 can be arranged to through dielectric layer 151,155 and ESL 153.In certain embodiments, each in the metal structure 140,150 and 160 can be included at least one the barrier layer (not shown) in their bottom section.Barrier layer can comprise at least a material, such as, aluminium oxide, aluminium, aluminium nitride, titanium, titanium nitride (TiN), tantalum, tantalum nitride, other suitable materials and/or its combination.In other embodiments, each in the metal structure 140,150 and 160 can be processed by at least a material, such as, aluminium, copper, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO 2, and/or other suitable materials.
In certain embodiments, metal structure 140 and 160 can be respectively directly contacts with 121 with source area 111.Metal structure 150 can directly contact with 123 with drain region 113.In other embodiments, metal structure 140 can directly contact with 121b with silicide area 111b respectively with 160.Metal structure 150 can directly contact with 123b with silicide area 113b.
In certain embodiments, other dielectric materials, via plug, metal area and/or metal wire (not shown) can be formed on and be used for interconnection on gate electrode part 130a and the 130b.Dielectric layer can comprise the material such as silica, silicon nitride, silicon oxynitride, low-k dielectric material, ultralow-k dielectric material or its any combination.Via plug, metal area and/or metal wire can comprise the material such as tungsten, aluminium, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickle silicide, cobalt silicide, other suitable conductive material and/or its combination.Via plug, metal area and/or metal wire can form through any suitable treatments, such as, deposition, photoetching process and etch processes and/or its combine to form.
Fig. 2 A is the sketch map that the representative configuration layer of another typical integrated circuit is shown.Add 100 expressions with the item of the identical Fig. 2 A of item among Figure 1A by same reference numerals.In Fig. 2 A, integrated circuit 200 can comprise a plurality of metal structures, for example, metal structure 270a-270d, each all with source area 211,221 and drain region 213,223 in one directly contact.In certain embodiments, metal structure 270a-270d can be overlapping with each metal structure 240,250 and 260 at least in part on wiring direction.
In certain embodiments, the width of each among the metal structure 270a-270d can equal each metal structure 240,250 and 260 basically.In other embodiments, metal structure 270a-270d can be wideer or narrower than each metal structure 240,250 and 260.In certain embodiments, metal structure 270a-270d can be called the M01 metal structure, and metal structure 240,250 and 260 can be called the M02 metal structure.
In certain embodiments, each among the metal structure 270a-270d all can extend to opposite edges 210b from the edge 210a of diffusion zone 210 continuously and perhaps extend to opposite edges 220b continuously from the edge 220a of diffusion zone 220.In other embodiments, each among the metal structure 270a-270b all can be extended the width W of diffusion zone 210 1About 5% or distance still less or from the edge 210a-210b shortens the width W of diffusion zone 210 1About 5% or distance still less.In other embodiment that also have, each among the metal structure 270c-270d all can be extended the width W of diffusion zone 220 2About 5% or distance still less or from the edge 220a-220b shortens the width W of diffusion zone 220 2About 5% or distance still less.
In certain embodiments, metal structure 240 and diffusion zone 210 can be on wiring direction overlap distance D 1Metal structure 250 and diffusion zone 210 can be on wiring direction overlap distance D 2Distance B 1Greater than distance B 2Metal structure 260 and diffusion zone 220 can be on wiring direction overlap distance D 3Metal structure 250 and diffusion zone 220 can be on wiring direction overlap distance D 4In certain embodiments, distance B 3Greater than distance B 4In other embodiments, distance B 3Greater than distance B 2In other embodiment that also have, in this distance B that combines Figure 1A to describe 1, D 2, D 3, and/or D 4Respectively greater than distance B 1, D 2, D 3, and/or D 4
In certain embodiments, distance B 1And D 2Summation can equal width W basically 1In other embodiments, distance B 1And D 2Summation can be greater than or less than width W 1In other embodiment that also have, distance B 3And D 4Summation can equal width W basically 2In other embodiment that still also have, distance B 3And D 4Summation can be greater than or less than width W 2
Fig. 2 B is the cross-sectional view along the typical integrated circuit of the hatching 2B-2B intercepting shown in Fig. 2 A.In Fig. 2 B, metal structure 270a-270d can directly contact with source area 221 with source area 211, drain region 213,223 respectively.Metal structure 240,250 and 260 can be electrically connected with source area 211, drain region 213,223 and source area 221 respectively through metal structure 270a-270d.In certain embodiments, metal structure 270a-270d can be provided with through dielectric layer 251 and ESL 253, directly contacts with silicide area 211b, 213b, 221b and 223b respectively.
In certain embodiments, each among the metal structure 270a-270d all can be included at least one barrier layer (not shown) at their bottom section place.Barrier layer can comprise at least a material, such as, aluminium oxide, aluminium, aluminium nitride, titanium, titanium nitride (TiN), tantalum, tantalum nitride, other suitable materials and/or its combination.In certain embodiments, each among the metal structure 270a-270d all can be processed by at least a material, such as, aluminium, copper, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO 2, and/or other suitable materials.In other embodiments, each among the metal structure 270a-270d all can be processed by tungsten, and in metal structure 240,250 and 260 each all can all be made of copper.
In certain embodiments, the end face of metal structure 270a-270d can with the end face basic horizontal of conductive layer 235a and 235b.Term " basic horizontal " this can represent the end face of metal structure 270a-270d can be than the end face of conductive layer 235a and 235b a high distance, for example, the thickness of ESL 253.In certain embodiments; Term " basic horizontal " can be lower than the end face of ESL 253 at this end face that can represent metal structure 270a-270d, and this is because of the depression result on the end face of being handled the metal structure 270a-270d that causes by etch-back processing or chemico-mechanical polishing (CMP).In other embodiments; Term " basic horizontal " can be lower than the end face of conductive layer 235a and 235b at this end face that can represent metal structure 270a-270d, and this is owing to the depression result on the end face of being handled the metal structure 270a-270d that causes by etch-back processing or chemico-mechanical polishing (CMP).
With reference to figure 2A-Fig. 2 B, find, metal structure 270a-270d can be arranged to metal structure 240,250 and 260 with each source area 211, drain region 213,223 and source area 221 between be electrically connected.Metal structure 270a-270d can cover each diffusion zone 210 and 220 basically on wiring direction.Can reduce from metal structure 270a-270d to source electrode ideally and the impedance of drain region.In certain embodiments, be arranged to the metal structure 240,250 of electrical connection and 260 overlap distance D 1-D 4Can reduce.Also find, the end face of metal structure 270a-270d can with the end face basic horizontal of conductive layer 235a and 235b.Between metal structure 270a and the 270b and the parasitic capacitance between metal structure 270c and the 270d low.
Fig. 3 is the flow chart that the typical method that forms integrated circuit is shown.Fig. 4 A-Fig. 4 E is the schematic cross section along the hatching 2B-2B intercepting shown in Fig. 2 A that another typical method that forms integrated circuit 200 is shown.In Fig. 3, the method 300 that forms integrated circuit can be included in and form first diffusion zone and second diffusion zone (handling 310) on the substrate.
In certain embodiments, handle 310 and can on substrate 203, form diffusion zone 210 and 220, shown in Fig. 2 A and Fig. 4 A.In certain embodiments, handle 310 and can comprise the isolation structure 215 that formation makes diffusion zone 210 separate with diffusion zone 220.In certain embodiments; The formation of isolation structure 215 can comprise: etched trench is (for example through photoetching treatment patterned semiconductor substrate 203, in substrate; Through using dry ecthing, wet etching and/or plasma etch process) and with dielectric material filling groove (for example, through using chemical vapor deposition process).In certain embodiments, isolation structure 215 can have sandwich construction, such as, with silicon nitride or silica-filled thermal oxide backing layer.In certain embodiments, handle 310 and can be called STI processing or LOCOS processing.
With reference to figure 4A, in certain embodiments, N type well region 207 and/or P type well region 209 can optionally be formed in diffusion zone 201 and 205 respectively.N type well region 207 and/or P type well region 209 can for example inject to handle through photoetching treatment and ion and form.In certain embodiments, can carry out heat treatment and/or rapid thermal treatment (RTP), so that the alloy in N type well region 207 and/or the P type well region 209 is active.
With reference to figure 3, method 300 can comprise: in first diffusion zone, be formed for first kind transistor drain district and source area (handling 320).In some embodiment that form the P transistor npn npn 201 shown in Fig. 4 A, handle 320 and can form source area 211 and drain region 213.In certain embodiments, each in source area and drain region 211 and 213 can comprise and can for example inject the P type heavily doped region of handling formation through photoetching treatment and ion.
In other embodiments, handling 320 can comprise: in source area 211 and drain region 213, form structure 211c and 213c respectively.Structure 211c and 213c provide pressure can for the raceway groove of P transistor npn npn 201.In certain embodiments, structure 211c and 213c can pass through that epitaxial process, decompression CVD (RPCVD) are handled, molecular beam epitaxy (MBE) is handled, chemical vapor deposition (CVD) is handled, metal organic chemical vapor deposition (MOCVD) is handled, ald (ALD) is handled, multilayer epitaxial is handled or its any combination forms.
In certain embodiments, handle 320 and can optionally be included in formation P type LDD 211a and 213a under the spacer 241a. P type LDD 211a and 213a can for example inject to handle through the inclination angle ion and form.In certain embodiments, before the processing 340 that forms the gate electrode part, can on structure 211c and 213c, form silicide area, wherein, this processing can be called silicide and at first handle.In other embodiments, handle 320 and can comprise silicide area 211b and the 211c that formation is described below in conjunction with Fig. 4 C.In some other embodiment, heat treatment and/or rapid thermal treatment (RTP) can optionally be carried out, so that source area 211 is active with the alloy in the drain region 213.
Refer again to Fig. 3, method 300 can comprise: the drain region and the source area (handling 330) that in second diffusion zone, are formed for second type of transistor.In some embodiment that form the N transistor npn npn 205 shown in Fig. 4 A, handle 330 and can form source area 221 and drain region 223.In certain embodiments, each in the source area 211 and 223 can comprise and can for example inject the N type heavily doped region of handling formation through photoetching treatment and ion.
In other embodiments, handling 330 can comprise: form the pressure texture (not shown) in each in source area 221 and drain region 213.Pressure texture can provide the pressure with the pressure in contrast that is provided by structure 211c and 213c to the raceway groove of N transistor npn npn 205.Pressure texture can pass through that epitaxial process, decompression CVD (RCVD) are handled, molecular beam epitaxy (MBE) is handled, chemical vapor deposition (CVD) is handled, metal organic chemical vapor deposition (MOCVD) is handled, ald (ALD) is handled, multilayer epitaxial is handled or its any combination forms.
In certain embodiments, handling 330 can optionally comprise: under spacer 241b, form N type LDD 221a and 223a. N type LDD 221a and 223a can for example inject to handle through the inclination angle ion and form.In certain embodiments, before the processing 340 that forms the gate electrode part, can on source area 211 and drain region 213, form silicide area, wherein, this processing can be called silicide and at first handle.In other embodiments, handle 320 and can comprise silicide area 221b and the 221c that formation is described below in conjunction with Fig. 4 C.In some other embodiment, can optionally carry out heat treatment and/or rapid thermal treatment (RTP), so that source area 221 is active with the alloy in the drain region 223.Note, more than combine the processing 320 of Fig. 3 description and 330 order to exchange.For example, handling 330 can carry out before handling 320.It shall yet further be noted that treatment step and/or their order in each that handle in 320 and 330 can be changed and/or exchange.The application's scope is not limited thereto.
Refer again to Fig. 3, method 300 can comprise: form and stride across first diffusion zone and the continuous gate electrode that extends of second diffusion zone (handling 340).In certain embodiments, this method can comprise: form the gate electrode 230 shown in Fig. 2 A.
Gate electrode 230 can at first be handled or grid is handled formation at last through grid.In using last some embodiment that handle of grid, handling 340 can comprise: on substrate 203, form dummy gate electrode 232a and 232b, shown in Fig. 4 A.Dummy gate electrode 232a and 232b can be processed by at least a material, such as, polysilicon, amorphous silicon, silica, silicon nitride, material with rate of etch different basically with dielectric layer 251 and/or spacer 241a-241b.In certain embodiments, dummy gate electrode 232a and 232b can handle through CVD and form.
Handling 340 can comprise: for example remove dummy gate electrode 232a and 232b through wet etching process, dry etch process or its any combination.After removing dummy gate electrode 232a and 232b, handling 340 can comprise: on substrate 203, form gate electrode part 230a and 230b. Gate electrode part 230a and 230b can comprise sandwich construction 231,233 and conductive layer 235a, 235b respectively.Sandwich construction 231 and 233 can for example form through any suitable treatments, such as, ALD handles, CVD handles, physical vapor deposition (PVD) is handled, decompression CVD (RPCVD) handles, PECVD handles, MOCVD handles or its any combination.Conductive layer 235a and 235b can for example form through any suitable treatments; Such as, ALD handles, CVD handles, physical vapor deposition (PVD) is handled, reduce pressure CVD (RPCVD) processing, PECVD processing, MOCVD processing, electroplating processes, sputter process or its any combination.After forming gate electrode part 230a and 230b, ESL layer 253 can for example be handled through CVD and be formed on gate electrode part 230a and the 230b.
Refer again to Fig. 3, method 300 can comprise: form first metal structure, second metal structure and the 3rd metal structure (handling 350).First metal structure can be electrically connected with first source area, and second metal structure can be electrically connected with first drain region and second drain region, and the 3rd metal structure can be electrically connected with second source area.
Forming among some embodiment of metal structure with the mode that is similar to the cross-sectional view shown in Figure 1B, dielectric layer 155 can be formed on the ESL layer 153.Metal structure 140,150 and 160 can form through dielectric layer 151,155 and ESL layer 153, makes metal structure 140,150 can directly contact with 123 with separately source area and drain region 111,113,121 with 160.
Forming among some embodiment of metal structure with the mode that is similar to the structure shown in Fig. 2 A-Fig. 2 B, method 300 may further include: form the metal structure 270a-270d that is electrically connected with each metal structure 240,250 and 260.In certain embodiments, method 300 can comprise: form the opening 271a-271c through dielectric layer 251 and ESL 253.Opening 271a-271c can expose each source area and drain region 211,213,221 and 223 at least in part, shown in Fig. 4 C.
In certain embodiments, after forming opening 271a-271c, can in each source area and drain region 211,213,221 and 223, form silicide area 211b, 213b, 221b and 223b.Note, after the boundary layer 217a-217b and height-k dielectric layer that form sandwich construction 231 and 233, form silicide area 211b, 213b, 221b and 223b shown in Fig. 4 C.Silicide area 211b, 213b, 221b and 223b are without undergoing the boundary layer 217a-217b that forms sandwich construction 231 and 233 and the thermal cycle of height-k dielectric layer.In certain embodiments, the processing that forms silicide area 211b, 213b, 221b and 223b can be called silicide and handle at last.
With reference to figure 4D, method 300 can comprise the metal structure 270a-270d that formation and each source area and drain region 211,213,221 and 223 directly contact.Metal structure 270a-270d can for example pass through deposition, PVD processing, CVD processing, ALD processing, sputter process, electroplating processes, other appropriate method or its any combination and form.
With reference to figure 4E, handling 350 (as shown in Figure 3) can comprise: form the metal structure 240,250 and 260 that is electrically connected with each metal structure 270a-270d.In certain embodiments, handling 350 can comprise: form the opening (unmarked) through dielectric layer 255.Opening can expose each metal structure 270a-270d at least in part.Metal structure 240,250 and 260 can be formed in the opening then, and 270a-270d is electrically connected with each metal structure.In certain embodiments, metal structure 240,250 and 260 can for example be passed through deposition, PVD processing, CVD processing, ALD processing, sputter process, electroplating processes, other appropriate method and/or its combination formation.
Fig. 5 illustrates the sketch map that comprises the system that is arranged on the typical integrated circuit on the substrate.In Fig. 5, system 500 can comprise the integrated circuit 502 that is arranged on the substrate 501.In certain embodiments, substrate 501 can comprise printed circuit board (PCB) (PCB), printed wiring board and/or other carriers that can bearing integrated.Integrated circuit 502 can be similar to the integrated circuit 100 or 200 of above combination Figure 1A-Figure 1B and Fig. 2 A-Fig. 2 B description respectively.Integrated circuit 502 can be electrically connected with substrate 501.In certain embodiments, integrated circuit 502 can be electrically connected with substrate 501 through projection 505.In other embodiments, integrated circuit 502 can be electrically connected with substrate 501 through the wire-bonded (not shown).In certain embodiments, system 500 can be the part such as the electronic system of computer, Wireless Telecom Equipment, computer associated peripheral, amusement equipment etc.
In certain embodiments, comprise that the system 500 of integrated circuit 502 can provide whole system in an IC, so-called system on chip (SOC) or integrated circuit are attend system (SOIC) equipment.These SOC/SOIC equipment can provide all required circuit such as for example realizing mobile phone, PDA(Personal Digital Assistant), digital VCR, DV, digital camera, MP3 player in single integrated circuit.
Fig. 6 is the sketch map that the representative configuration layer of typical integrated circuit is shown.Add 400 expressions with the item of identical Fig. 6 of item among Fig. 2 A by same reference numerals.In Fig. 6, integrated circuit 600 comprises the diffusion zone 610 and 620 that is separated from each other and is arranged to respectively dissimilar transistors 601 and 605.For example, diffusion zone 610 is arranged to the P transistor npn npn, and diffusion zone 620 is arranged to the N transistor npn npn.Transistor 601 is included in the source area 611 and drain region 613 in the diffusion zone 610.Transistor 605 is included in the source area 621 and drain region 623 in the diffusion zone 620.
With reference to figure 6, integrated circuit 600 is included in and strides across the gate electrode 630 that diffusion zone 610 and 620 extends continuously on the wiring direction.In certain embodiments, integrated circuit 600 comprises a plurality of metal structures, for example, metal structure 670a-670d, each all with source area 611,621 and drain region 613,623 in one directly contact.Integrated circuit 600 can comprise the metal structure 640,650 and 660 that is separately positioned on metal structure 670a, 670b, 670d and the 670c and is electrically connected with it.In certain embodiments, metal structure 650 extends to metal structure 670d continuously from metal structure 670b.
In certain embodiments, the width W of metal structure 670b M1Basically be equal to or greater than the width W of metal structure 650 M2In other embodiments, width W M1With width W M2Ratio can be variation in about 2: 1 scope in about 1: 1.In other embodiment that also have, width W M1With width W M2Ratio can be variation in about 1.6: 1 scope in about 1.3: 1.
In certain embodiments, the width W of metal structure 670d M3Basically be equal to or greater than the width W of metal structure 650 M2In other embodiments, width W M3With width W M2Ratio can be variation in about 2: 1 scope in about 1: 1.In other embodiment that also have, width W M3With width W M2Ratio can be variation in about 1.6: 1 scope in about 1.3: 1.
In certain embodiments, the width W of metal structure 670a M4Basically be equal to or greater than the width W of metal structure 650 M5In other embodiments, width W M4With width W M5Ratio can be variation in about 2: 1 scope in about 1: 1.In other embodiment that also have, width W M4With width W M5Ratio can be variation in about 1.6: 1 scope in about 1.3: 1.
In certain embodiments, the width W of metal structure 670c M6Basically be equal to or greater than the width W of metal structure 660 M7In other embodiments, width W M6With width W M7Ratio can be variation in about 2: 1 scope in about 1: 1.In other embodiment that also have, width W M6With width W M7Ratio can be variation in about 1.6: 1 scope in about 1.3: 1.
Note width W M1, W M3, W M4And W M6In at least one be equal to or greater than width W respectively basically M2, W M5And W M7In certain embodiments, a broad among the metal structure 670a-670d and in integrated circuit 600, using only.In other embodiments, two or more broads among the metal structure 670a-670d and application in integrated circuit 600.In other embodiment that also have, all metal structure 670a-670d are wideer than each metal structure 640,650 and 660.
Note, regulate metal structure 640,650,660 and/or the width of 670a-670d and/or contact resistance and/or the parasitic capacitance that length can change integrated circuit 600.The change of contact resistance and/or parasitic capacitance can influence the service speed of integrated circuit 600.For example, among the sample I-V each, the width of each in the metal structure 640, the 650 and 660 all value of being fixed on is about 20 nanometers (nm).The width of each among the metal structure 670a-670d of sample I-V is about 26nm, 30nm, 32nm, 34nm and 38nm respectively.Thereby for sample I-V, metal structure 670a-670d was respectively 1.3: 1,1.5: 1,1.6: 1,1.7: 1 and 1.9: 1 with the width ratio of each metal structure 640,650 and 660.Notice that the size of above-mentioned metal structure 670a-670d only is schematic.In certain embodiments, the size of metal structure 670a-670d can scale up or reduces according to applied technology node.The application's scope is not limited thereto.
Table 2 illustrates the analog result that comprises in response to parasitic capacitance, contact resistance and the service speed of the integrated circuit of the change of above-mentioned width ratio.
Table 2
Sample I Sample II Sample III Sample IV Sample V
Width ratio 1.3∶1 1.5∶1 1.6∶1 1.7∶1 1.9∶1
Parasitic capacitance 1 1 1 1 1
Contact resistance 1 0.98 0.97 0.96 0.95
Service speed 1 1.014 1.02 1.028 1.037
The applicant finds that the change of the width ratio between metal structure 640,650,660 and/or the 670a-670d can unexpectedly realize the improvement to the service speed of integrated circuit.As shown in table 2, the integrated circuit that will have the sample I of 1.3: 1 width ratios is used as the basis.Find that because the same widths of metal structure 640,650 and 660, sample I-V has identical parasitic capacitance.Also find, because the increase of the width of the metal structure 670a-670d among the sample I-V causes contact resistance to reduce gradually.Along with reducing of contact resistance, the service speed of integrated circuit increases in response to the increase of the width of metal structure 670a-670d.
Notice that integrated circuit 600 can be through forming with the method 300 of above combination Fig. 3 description and/or the processing stage identical or basic similarly method of above combination Fig. 4 A-Fig. 4 E description.The detailed description of method no longer repeats.Notice that also integrated circuit 600 can be applied in the system 500 of above combination Fig. 5 description.
In the application's embodiment, integrated circuit comprises and is used for transistorized first diffusion zone of the first kind.First kind transistor comprises first drain region and first source area.Second diffusion zone that is used for second type of transistor separates with first diffusion zone.Second type of transistor comprises second drain region and second source area.Gate electrode on wiring direction, strides across first diffusion zone and second diffusion zone extends continuously.First metal structure is electrically connected with first source area.Second metal structure is electrically connected with second drain region.The 3rd metal structure is arranged on first and second metal structures and with it and is electrically connected.The width of first metal structure is equal to or greater than the width of the 3rd metal structure basically.
More than describe the characteristic of a plurality of embodiment, made those skilled in the art can understand the many aspects of this disclosure better.Those skilled in the art should expect that they can easily use this disclosure as the basis that is used to design or revise other processing and structure, the same advantage that is used to realize identical purpose and/or is implemented in the embodiment of this introduction.Those of skill in the art also will appreciate that this equivalent construction does not break away from the spirit and scope of the present invention, and they can make multiple change, replacement and change at this under the situation that does not break away from the spirit and scope of the present invention.

Claims (10)

1. integrated circuit comprises:
Be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone;
Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone;
Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously;
First metal structure is electrically connected with said first drain region;
Second metal structure is electrically connected with said second drain region; And
The 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the width of said first metal structure is equal to or greater than the width of said the 3rd metal structure basically.
2. integrated circuit according to claim 1, wherein, the ratio of the width of the width of said first metal structure and said the 3rd metal structure changed in about 2: 1 scope at about 1: 1, perhaps
The ratio of the width of the width of said first metal structure and said the 3rd metal structure changed in about 1.6: 1 scope at about 1.3: 1; Wherein, said first metal structure and said second metal structure are extended to opposite edges from the edge of said first diffusion zone and said second diffusion zone respectively on said wiring direction basically continuously.
3. integrated circuit according to claim 1 further comprises:
The 4th metal structure is electrically connected with said first source area; And
Five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction; And said first distance is greater than said second distance
Wherein, Said first diffusion zone has first width; Said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1
Wherein, the width of said the 4th metal structure and said five metals belong to structure the ratio of width at about 1: 1 in about 2: 1 scope, perhaps
The ratio that the width of said the 4th metal structure and said five metals belong to the width of structure arrived in about 1.6: 1 scope at about 1.3: 1.
4. integrated circuit according to claim 3 further comprises:
The 6th metal structure is electrically connected with said second source area; And
The 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction; And said the 3rd distance is greater than said the 4th distance
Wherein, Said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope
Wherein, the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 2: 1 scope, perhaps at about 1: 1
The ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
5. integrated circuit comprises:
Be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone;
Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone;
Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously;
First metal structure is electrically connected with said first drain region;
Second metal structure is electrically connected with said second drain region;
The 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the ratio of the width of the width of said first metal structure and said the 3rd metal structure arrived in about 1.6: 1 scope at about 1.3: 1;
The 4th metal structure is electrically connected with said first source area; And
Five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, Said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction, and said first distance is greater than said second distance.
6. integrated circuit according to claim 5; Wherein, Said first diffusion zone has first width, and said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1; Wherein, the width of said the 4th metal structure and said five metals belong to structure the ratio of width at about 1.3: 1 in about 1.6: 1 scope.
7. integrated circuit according to claim 5 further comprises:
The 6th metal structure is electrically connected with said second source area; And
The 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction; And said the 3rd distance is greater than said the 4th distance
Wherein, Said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope.
8. integrated circuit according to claim 7, wherein, the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
9. integrated circuit comprises:
Be used for transistorized first diffusion zone of the first kind, said first kind transistor is included in first drain region and first source area in said first diffusion zone;
Second diffusion zone that is used for second type of transistor, said second diffusion zone separates with said first diffusion zone, and said second type of transistor is included in second drain region and second source area in said second diffusion zone;
Gate electrode strides across said first diffusion zone on wiring direction and said second diffusion zone extends continuously;
First metal structure is electrically connected with said first drain region;
Second metal structure is electrically connected with said second drain region;
The 3rd metal structure; Be arranged on said first metal structure and said second metal structure and and be electrically connected with said first metal structure and said second metal structure; Wherein, the ratio of the width of the width of said first metal structure and said the 3rd metal structure is between about 1.3: 1 to about 1.6: 1;
The 4th metal structure is electrically connected with said first source area;
Five metals belongs to structure; Be arranged on said the 4th metal structure and and be electrically connected with it; Wherein, Said five metals belongs to structure and said first diffusion zone overlapping first distance on said wiring direction, said the 3rd metal structure and said first diffusion zone overlapping second distance on said wiring direction, and said first diffusion zone has first width; Said first distance arrives in about 1: 1 scope at about 0.75: 1 with the ratio of said first width, and the ratio of said second distance and said first width arrived in about 0.33: 1 scope at about 0.1: 1;
The 6th metal structure is electrically connected with said second source area; And
The 7th metal structure; Be arranged on said the 6th metal structure and and be electrically connected with it; Wherein, Said the 7th metal structure and said second diffusion zone overlapping the 3rd distance on said wiring direction, said the 3rd metal structure and said second diffusion zone overlapping the 4th distance on said wiring direction, said second diffusion zone has second width; The ratio of said the 3rd distance and said second width about 0.75: 1 in about 1: 1 scope, and the ratio of said the 4th distance and said second width at about 0.1: 1 in about 0.33: 1 scope.
10. integrated circuit according to claim 9; Wherein, The ratio that the width of said the 4th metal structure and said five metals belong to the width of structure arrived in about 1.6: 1 scope at about 1.3: 1, and the ratio of the width of the width of said the 6th metal structure and said the 7th metal structure arrived in about 1.6: 1 scope at about 1.3: 1.
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