CN102736338B - Liquid crystal disply device and its preparation method - Google Patents
Liquid crystal disply device and its preparation method Download PDFInfo
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- CN102736338B CN102736338B CN201110437013.1A CN201110437013A CN102736338B CN 102736338 B CN102736338 B CN 102736338B CN 201110437013 A CN201110437013 A CN 201110437013A CN 102736338 B CN102736338 B CN 102736338B
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Abstract
The present invention relates to a kind of liquid crystal indicator, it is characterized in that: comprise: a first substrate, comprises: a base material; At least one first wire, is arranged on this base material; One insulation course, covers this first wire; At least one second wire, is arranged on this insulation course, wherein this first wire and this second wire orthogonal; And a protective seam, cover this second wire, wherein this protective seam has at least one recess, is positioned at above this first wire, above this second wire or the top of an intervening portion of this first wire and this second wire; One second substrate, this first substrate parallel, this second substrate comprises at least one sept, and abuts this recess bottom one of this sept; And a liquid crystal layer, be arranged between this first substrate and this second substrate; This device has simple, the novel advantage of structure, and the cost manufacturing this device is low.
Description
Technical field
The invention relates to a kind of Liquid crystal disply device and its preparation method.
Background technology
Liquid crystal display is mainly made up of plurality of groups of substrates of thin-film transistor, colored filter substrate and the layer of liquid crystal molecule be arranged between two substrates.Because the thickness of layer of liquid crystal molecule and homogeneity can affect the characteristic of display, as display speed, visual angle, lightness and contrast etc., between two substrates, therefore need sept to maintain certain spacing.
Generally speaking, sept can be arranged on plurality of groups of substrates of thin-film transistor or on colored filter substrate.Such as can be the spherical spacers of distribution.But if when two substrates assembling slightly offsets, or when panel is subject to external force extruding, sept easily slides, and makes panel generation area light leak, contrast reduction or color is caused to show the phenomenons such as abnormal.
Therefore, the problems referred to above need a kind of Liquid crystal disply device and its preparation method of novelty, to can be improved.
Summary of the invention
The object of the present invention is to provide the manufacture method of the liquid crystal indicator of liquid crystal indicator that a kind of structure is simple, novel and a kind of low cost of manufacture.
Of the present invention one is characterised in that: a kind of liquid crystal indicator, is characterized in that: comprise:
One first substrate, comprises:
One base material;
At least one first wire, is arranged on this base material;
One insulation course, covers this first wire;
At least one second wire, is arranged on this insulation course, wherein this first wire and this second wire orthogonal; And
One protective seam, cover this second wire, wherein this protective seam has at least one recess, is positioned at above this first wire, above this second wire or the top of an intervening portion of this first wire and this second wire;
One second substrate, this first substrate parallel, this second substrate comprises at least one sept, and abuts this recess bottom one of this sept; And
One liquid crystal layer, is arranged between this first substrate and this second substrate.
Further, wherein the breadth extreme of this recess is less than or equal to the breadth extreme of this sept.
Further, wherein the breadth extreme of this recess is less than a width of this first wire or this second wire.
Further, wherein this recess runs through this protective seam.
Further, wherein this first substrate more comprises semi-conductor layer and is located between this insulation course and this second wire, and is positioned at this intervening portion, and wherein this recess is positioned at directly over semiconductor layer.
Further, wherein this first substrate more comprise a thin film transistor (TFT) be electrically connected this first and this second wire.
Further, wherein this protective seam has a contact hole, to expose a drain of this thin film transistor (TFT).
Further, wherein this first substrate more comprises a pixel electrode and is positioned on this protective seam, and this pixel electrode is electrically connected this thin film transistor (TFT) via this contact hole.
Another feature of the present invention is: a kind of manufacture method of liquid crystal indicator, is characterized in that: comprise:
Form one first wire and a gate on a base material;
Form an insulation course and cover this first wire and this gate;
Formed on a protruding semiconductor layers this insulation course above this gate;
Form one second wire, one source pole and a drain on this insulation course, wherein this source electrode and this drain cover a part for this protruding semiconductor layers, and this first wire and this second wire orthogonal;
Form a protective seam on this second wire, this protruding semiconductor layers, this source electrode and drain, this protective seam has a recess and a contact hole, this recess is positioned at above this first wire, above this second wire or the top of an intervening portion of this first wire and this second wire, and this contact hole exposes this drain;
Form a pixel electrode on this protective seam, to form a first substrate, wherein this pixel electrode is electrically connected this drain via this contact hole;
Engage this first substrate and there is a second substrate of a sept, bottom making one of this sept, abut this recess; And
Form a liquid crystal layer between this first substrate and this second substrate.
Further, the step wherein forming this protective seam comprises use one dry ecthing procedure, to form this recess and this contact hole.
Advantage of the present invention: structure is simple, novel, the sept of second substrate can abut the recess of first substrate; Recess has the function of firm sept, slides to avoid sept.In addition, this manufacture method does not need to use extra equipment or micro-photographing process to form recess, therefore can not increase manufacturing cost.
Accompanying drawing explanation
Fig. 1-3 figure is the schematic top plan view of the plurality of groups of substrates of thin-film transistor of an embodiment of the present invention.
Fig. 4-5 figure is the diagrammatic cross-section of the liquid crystal indicator of an embodiment of the present invention.
In figure: 100: first substrate; 110: base material; 120: the first wires; 122: gate; 124: shared electrode; 130: insulation course; 140: semiconductor layer; 142: protruding semiconductor layers; 150: the second wires; 152: source electrode; 154: drain; 160: protective seam; 160a: recess; 160b: contact hole; 170: thin film transistor (TFT); 180: pixel electrode; 200: second substrate; 210: sept; 300: liquid crystal layer; W1: the breadth extreme of recess; W2: the breadth extreme of sept; The width of the W3: the first wire; The width of the W4: the second wire.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
1st figure is the schematic top plan view of the plurality of groups of substrates of thin-film transistor of an embodiment of the present invention.4-5 figure is the diagrammatic cross-section of the liquid crystal indicator of A-A ' section line segment along the 1st figure.
The invention provides a kind of liquid crystal indicator, comprise first substrate 100, second substrate 200 and liquid crystal layer 300, as shown in Figure 4.First substrate 100 includes base material 110, first wire 120, insulation course 130, second wire 150 and has the protective seam 160 of recess 160a.Second substrate 200 is parallel to first substrate 100.Second substrate 200 includes sept 210, and the bottom of sept 210 abuts recess 160a.Liquid crystal layer 300 is arranged between first substrate 100 and second substrate 200.
First wire 120 is arranged on base material 110, as shown in the 1st figure and the 4th figure.The first wire 120 in 1st figure is illustrated as sweep trace.In addition, gate 122 also can be set and connect the first wire 120.
Insulation course 130 is covered on the first wire 120, as shown in Figure 4.Insulation course 130 can be silicon nitride or monox.Insulation course 130 is in order to make to be electrically insulated between the first wire 120 and the second wire 150.
Second wire 150 is arranged on insulation course 130, and the first wire 120 and the second wire 150 orthogonal, as shown in Figure 1.Illustrative second wire 150 of 1st figure is data line.First wire 120 and the second wire 150 can be metal material.In addition, source electrode 152 also can be set with drain 154 on insulation course 130.Source electrode 152 can connect the second wire 150.
In one embodiment, first substrate 100 more can comprise semiconductor layer 140, and it is located between insulation course 130 and the second wire 150, as shown in Figure 5.Semiconductor layer 140 can be positioned at the intervening portion of the first wire 120 and the second wire 150.The area of semiconductor layer 140 can be greater than the area for the recess 160a arranged.Recess 160a can be arranged at directly over semiconductor layer 140.In addition, can arrange on the insulation course 130 of protruding semiconductor layers 142 above gate 122.
Protective seam 160 covers the second wire 150, and protective seam 160 has at least one recess 160a, as shown in 4-5 figure.The material of protective seam 160 can be silicon nitride or monox.The recess 160a of protective seam 160 can be positioned at the top of the first wire 120 or the second wire 150; Or the recess 160a of protective seam 160 can be positioned at the top of the intervening portion of the first wire 120 and the second wire 150.That is, recess 160a need be arranged at the region not affecting light penetration.1st figure illustrates recess 160a and is positioned at directly over the intervening portion of the first wire 120 and the second wire 150.2nd figure illustrates the top that recess 160a is positioned at the second wire 150.3rd figure illustrates the top that recess 160a is positioned at the first wire 120.The other structure of layer below the recess 160a of diverse location is decided by the design of each layer.For example, base material 110, first wire 120, insulation course 130 and the second wire 150 is had below the recess 160a of the 4th figure.Base material 110, first wire 120, insulation course 130, semiconductor layer 140 and the second wire 150 is had below the recess 160a of the 5th figure.It can thus be appreciated that be arranged at the recess 160a of diverse location, the gross thickness of the other structure of the layer below it may be different.Therefore, the height of sept 210 can be designed according to the distance at interval required between the gross thickness of the other structure of the layer below recess 160a and two substrates.
In one embodiment, recess 160a can run through protective seam 160.As shown in 4-5 figure, recess 160a runs through protective seam 160 and exposes the upper surface of the second wire 150.Or recess 160a can be the groove with a degree of depth, and does not run through protective seam 160 (not shown).
In one embodiment, first substrate 100 can more comprise thin film transistor (TFT) 170, and it is electrically connected the first wire 120 and the second wire 150, as shown in Figure 1.Thin film transistor (TFT) 170 can include gate 122, above-mentioned protruding semiconductor layers 142, source electrode 152 and drain 154.
In one embodiment, protective seam 160 can have contact hole 160b, to expose drain 154.In one embodiment, first substrate 100 more can comprise pixel electrode 180 and is positioned on protective seam 160.Pixel electrode 180 can be electrically connected thin film transistor (TFT) 170 via contact hole 160b.
Second substrate 200 is parallel to first substrate 100 and arranges.Second substrate 200 can include sept 210, and the bottom of sept 210 abuts recess 160a, as shown in 4-5 figure.Second substrate 200 can be colored filter substrate, and first substrate 100 can be plurality of groups of substrates of thin-film transistor.Colored filter substrate can comprise colored filter and light shield layer.Sept 210 can be arranged on light shield layer, so can not affect light penetration.Sept 210 can be has flexible resin.Sept 210 is in order to make to keep a determining deviation between first substrate 100 and second substrate 200.
In one embodiment, the breadth extreme W1 of recess 160a can be less than or equal to the breadth extreme W2 of sept 210.Such as, two substrates is when assembling, and flexible sept 210 contacts recess 160a and elastic deformation, makes the bottom of sept 210 can contact recess 160a completely.The shape of the floorage of recess 160a can be roughly the same with the shape of the floorage of sept 210.As shown in Figure 1, recess 160a is circular opening, and the sept 210 corresponding to it can be cylinder.
In one embodiment, the breadth extreme W1 of recess 160a is less than the width W 3 of the first wire 120 or is less than the width W 4 of the second wire 150.For example, the recess 160a breadth extreme W1 in the 1st figure is less than the width W 4 of the second wire 150.The breadth extreme W1 of the recess 160a in the 2nd figure is less than the width W 4 of the second wire 150.Recess 160a in 3rd figure is less than the width W 3 of the first wire 120 to breadth extreme W1.The bottom of recess 160a can be smooth surface, makes can contact completely between the bottom of sept 210 with recess 160a.In addition, the bottom of sept 210 is after contact recess 160a, and the inner surface of recess 160a can stop that sept 210 slides.When second substrate 200 and first substrate 100 combine slightly offset time, sept 210 can be led in recess 160a.Therefore, recess 160a has the function of guiding and firm sept 210.
Liquid crystal layer 300 is arranged between first substrate 100 and second substrate 200, as shown in 4-5 figure.Liquid crystal layer 300 can in order to control the light quantity of transmission.
It can thus be appreciated that the recess 160a in protective seam 160 can be positioned at the top of the intervening portion of the first wire 120, second wire 150 or the first wire 120 and the second wire 150.The bottom of sept 210 can abut recess 160a and not easily slide.Therefore, can when not affecting light penetration, firm sept 210 is in recess 160a.So recess 160a can in order to avoid producing because sept 210 slides region light leak, contrast reduces or Show Color changes problem.
The invention provides a kind of manufacture method of liquid crystal indicator.First the first wire 120 is formed with gate 122 on base material 110, as shown in the 1st figure and the 4th figure.First wire 120 can be sweep trace.When formation first wire 120 is with gate 122, shared electrode 124 can be formed, as shown in Figure 1 simultaneously.Layer of metal layer can be formed on base material 110 by metal sputtering mode, then form the first wire 120, gate 122 and shared electrode 124 through micro image etching procedure.
After formation first wire 120 with gate 122, form insulation course 130 and cover the first wire 120 and gate 122, as shown in Figure 4.Chemical vapor deposition process can be utilized to form a layer insulating 130.
Then, formed on the insulation course 130 of protruding semiconductor layers 142 above gate 122.Protruding semiconductor layers 142 can in order to as the channel layer (not illustrating) in thin film transistor (TFT) 170 and ohmic contact layer (not illustrating).PECVD can be utilized to form channel layer and ohmic contact layer.In addition, semiconductor layer 140 can be formed in the first wire 120 and the intervening portion of the second wire 150 for being formed, as shown in Figure 5 simultaneously.
Then, the second wire 150, source electrode 152 and drain 154 is formed on insulation course 130, as shown in the 1st figure and 4-5 figure.Source electrode 152 and drain 154 cover a part for protruding semiconductor layers 142.Can be arranged perpendicular between the second wire 150 and the first wire 120.Second wire 150 can be data line.Layer of metal layer can be formed on insulation course 130 by metal sputtering mode, then form the second wire 150, source electrode 152 and drain 154 through micro image etching procedure.Above-mentioned gate 122, protruding semiconductor layers 142, source electrode 152 can form thin film transistor (TFT) 170 with drain 154.This thin film transistor (TFT) 170 can be electrically connected the first wire 120 and the second wire 150.
Form a protective seam 160 on the second wire 150, protruding semiconductor layers 142, source electrode 152 and drain 154, as shown in the 1st figure and 4-5 figure.Protective seam 160 has recess 160a and contact hole 160b.Recess 160a is arranged at the top of the intervening portion of the first wire 120 and the second wire 150.In one embodiment, recess 160a can be arranged at the top of the second wire 150, as shown in Figure 2.Or recess 160a can be arranged at the top of the first wire 120, as shown in Figure 3.Contact hole 160b can expose the drain 154 of a part, as shown in Figure 1.In one embodiment, dry ecthing procedure can be used to form recess 160a and contact hole 160b.Specifically, can first deposit layer protective layer 160, then form recess 160a and contact hole 160b with micro image etching procedure.
Then, pixel electrode 180 is formed on protective seam 160, to form first substrate 100.Pixel electrode 180 can be electrically connected drain 154 via contact hole 160b.Shared electrode 124 can form storage capacitors with insulation course 130, protective seam 160 and the pixel electrode 180 above it.
Engage first substrate 100 and there is the second substrate 200 of sept 210, abutting recess 160a, as shown in 4-5 figure to make the bottom of sept 210.The position that recess 160a is arranged needs the position of the sept 210 of corresponding second substrate 200.Recess 160a can help firm sept 210, makes it not easily to slide.In addition, if slightly offset in the process of combination two substrates, recess 160a also bootable sept 210 gets back to correct position.Therefore, recess 160a has the function of guiding and firm sept 210.
Then, liquid crystal layer 300 is formed between first substrate 100 and second substrate 200, as shown in 4-5 figure.By filling mode, Liquid crystal pour can be formed liquid crystal layer 300 between first substrate and second substrate 200.
This manufacture method does not need to use extra equipment or micro-photographing process to form recess, therefore can not increase manufacturing cost.In addition, general light shield or gray-level mask and micro image etching procedure can be used to form above-mentioned first substrate.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention, anyly have the knack of this those skilled in the art, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (3)
1. a liquid crystal indicator, is characterized in that: comprise:
One first substrate, comprises: a base material; At least one first wire, is arranged on this base material; One insulation course, covers this first wire; At least one second wire, is arranged on this insulation course, wherein this first wire and this second wire orthogonal; And a protective seam, cover this second wire, wherein this protective seam has at least one recess, is positioned at above this first wire, above this second wire or the top of an intervening portion of this first wire and this second wire; One second substrate, this first substrate parallel, this second substrate comprises at least one sept, and abuts this recess bottom one of this sept; And a liquid crystal layer, be arranged between this first substrate and this second substrate;
Wherein the breadth extreme of this recess is less than or equal to the breadth extreme of this sept; Wherein this recess runs through this protective seam; Wherein this first substrate more comprises semi-conductor layer and is located between this insulation course and this second wire, and is positioned at this intervening portion, and wherein this recess is positioned at directly over semiconductor layer; Wherein this first substrate more comprise a thin film transistor (TFT) be electrically connected this first and this second wire; Wherein this protective seam has a contact hole, to expose a drain of this thin film transistor (TFT); Wherein this first substrate more comprises a pixel electrode and is positioned on this protective seam, and this pixel electrode is electrically connected this thin film transistor (TFT) via this contact hole.
2. liquid crystal indicator according to claim 1, is characterized in that: wherein the breadth extreme of this recess is less than a width of this first wire or this second wire.
3. a manufacture method for liquid crystal indicator, is characterized in that: comprise:
Form one first wire and a gate on a base material; Form an insulation course and cover this first wire and this gate; Formed on a protruding semiconductor layers this insulation course above this gate; Form one second wire, one source pole and a drain on this insulation course, wherein this source electrode and this drain cover a part for this protruding semiconductor layers, and this first wire and this second wire orthogonal; Form a protective seam on this second wire, this protruding semiconductor layers, this source electrode and drain, this protective seam has a recess and a contact hole, this recess is positioned at above this first wire, above this second wire or the top of an intervening portion of this first wire and this second wire, and this contact hole exposes this drain; Form a pixel electrode on this protective seam, to form a first substrate, wherein this pixel electrode is electrically connected this drain via this contact hole; Engage this first substrate and have a second substrate of a sept, bottom making one of this sept, abut this recess, sept is arranged on the light shield layer of second substrate, and sept is for having flexible resin; And form a liquid crystal layer between this first substrate and this second substrate; The step wherein forming this protective seam comprises use one dry ecthing procedure, to form this recess and this contact hole.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110437013.1A CN102736338B (en) | 2011-12-23 | 2011-12-23 | Liquid crystal disply device and its preparation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110437013.1A CN102736338B (en) | 2011-12-23 | 2011-12-23 | Liquid crystal disply device and its preparation method |
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| CN102736338A CN102736338A (en) | 2012-10-17 |
| CN102736338B true CN102736338B (en) | 2015-11-18 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103700671B (en) * | 2013-12-24 | 2017-01-11 | 华映视讯（吴江）有限公司 | pixel array substrate and display panel |
| TWI608599B (en) * | 2016-03-02 | 2017-12-11 | Innolux Corp | Display panel |
| CN112017534B (en) * | 2019-05-31 | 2022-06-10 | 瀚宇彩晶股份有限公司 | Flexible display device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071220A (en) * | 2006-05-12 | 2007-11-14 | 瀚宇彩晶股份有限公司 | Liquid crystal display device |
| CN101398580A (en) * | 2007-09-26 | 2009-04-01 | 北京京东方光电科技有限公司 | LCD device and method for manufacturing same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071220A (en) * | 2006-05-12 | 2007-11-14 | 瀚宇彩晶股份有限公司 | Liquid crystal display device |
| CN101398580A (en) * | 2007-09-26 | 2009-04-01 | 北京京东方光电科技有限公司 | LCD device and method for manufacturing same |
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Effective date of registration: 20170810 Address after: 1#, building third, fourth, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: 350015, Xingye Road, Mawei Science Park, Fujian, Fuzhou 1, China Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
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Granted publication date: 20151118 Termination date: 20201223 |