CN102723939B - Low-delay output interface circuit used in time calibrating device - Google Patents
Low-delay output interface circuit used in time calibrating device Download PDFInfo
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- CN102723939B CN102723939B CN201210087345.6A CN201210087345A CN102723939B CN 102723939 B CN102723939 B CN 102723939B CN 201210087345 A CN201210087345 A CN 201210087345A CN 102723939 B CN102723939 B CN 102723939B
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Abstract
The invention discloses a low-delay output interface circuit used in a time calibrating device. The circuit comprises an empty node output interface channel and a TTL level output interface channel. The maximum delay of the empty node output interface channel is less than 0.5 microsecond. The maximum delay of the TTL level output interface channel is less than 0.2 microsecond. Two standard time interval signals from the time calibrating device are simultaneously used as the input signals of the empty node output interface channel and the TTL level output interface channel. The empty node output interface channel and the TTL level output interface channel are respectively provided with three output terminals. The low-delay output interface circuit of the invention can not only be directly used in the newly designed time calibrating device, but also be made into an independent circuit board or module for carrying out transformation and upgrade on the time calibrating devices produced before. The output interface circuit has short time delay and strong adaptability, and therefore the time calibrating device can satisfy all calibration operation on a pointer type electric second meter, a digital electric second meter and a digital millisecond instrument. Perfect output protection can greatly improve the reliability and the durability of the time calibrating device.
Description
Technical field
the present invention relates to a kind of time calibrator low delay output interface circuit, belong to and improve time interval generator precision and reliability engineering field.
Background technology
time is one of the most basic in physics, most important physical quantity.In athletic competition, scientific experiment and production application, often relate to the time course of generation and the end of one or more events, these time relationships are established a capital really needs accurate time interval measurement.Conventional time interval measuring instrucment mainly contains stopwatch and millisecond instrument.Wherein stopwatch comprises mechanical stopwatch, electronic stopclock and electrical secondmeter.Electrical secondmeter is divided into again pointer electrical secondmeter and electronic type electrical secondmeter.
time interval measuring instrucment whether accurately, whether reach regulation requirement, need to determine by time interval generator.Time calibrator is as middle precision time interval metrological standard unit, for examining and determine mechanical stopwatch, electronic stopclock, pointer electrical secondmeter, digital electric stopwatch and digital millisecond instrument.Its basic function is that the quartz oscillator frequency division of inner high accuracy high stability is obtained to various standard time blank signal, by electronic control circuit and output interface circuit output, above-mentioned several time interval measuring instrucments are directly examined and determine.(the calibrating clock source of pointer electrical secondmeter is civil power 50Hz signal)
according to the relevant vertification regulation of country, to the calibrating of stopwatch and millisecond instrument, need the time interval signal under time calibrator output multiple-working mode.Current existing time calibrator because of the design of its output interface circuit perfect not, when to pointer electrical secondmeter, digital electric stopwatch and digital millisecond instrument calibrating, there is output time delay defect larger, poor for applicability, be difficult to meet whole calibration operations of these time interval measuring instrucments simultaneously.Meanwhile, because output interface lacks effective protective circuit, in calibration operation, may damage because mis-wired causes time calibrator.
Summary of the invention
the object of the invention is to; a kind of time calibrator low delay output interface circuit is provided; for the calibrating requirement of pointer electrical secondmeter, digital electric stopwatch and digital millisecond instrument, a kind of low delay is provided, has and improve defencive function and the good time calibrator output interface circuit of adaptability.To overcome the deficiencies in the prior art.
technical scheme of the present invention
a kind of time calibrator low delay output interface circuit, this circuit comprises the Transistor-Transistor Logic level output interface passage that is mainly used in the empty node output interface passage of pointer electrical secondmeter calibrating and examines and determine for digital electric stopwatch or digital millisecond instrument; The maximum delay of empty node output interface passage is less than 0.5 μ s; Transistor-Transistor Logic level output interface passage maximum delay is less than 0.2 μ s; From two-way standard time of time calibrator every the input signal end IN1 of signal and input signal end IN2 simultaneously as the input signal end of empty node output interface passage and Transistor-Transistor Logic level output interface passage; Empty node output interface passage and Transistor-Transistor Logic level output interface passage are respectively equipped with three outputs.
the electric insulation of realizing time calibrator low delay output interface circuit and time calibrator in low delay output interface circuit by high speed optoelectronic coupling circuit and DC/DC buffer circuit for aforementioned time calibrator, eliminates influencing each other and disturbing between empty node output interface passage and Transistor-Transistor Logic level output interface passage and time calibrator.
aforementioned time calibrator is with in low delay output interface circuit, and described time calibrator is provided with three DC/DC buffer circuits with low delay output interface circuit; DC/DC buffer circuit comprises that model is the high insulating power supply module U4 of H0505S-1W, and the 2nd pin of power module U4 is connected with the earth terminal GND of time calibrator, and the 5th pin of power module U4 is connected with isolation earth point GND1, GND2 or GND3; From time calibrator inside+5V power supply is connected with the 1st pin of power module U4 through polymeric switch P1, the 1st foot meridian capacitor C1 of power module U4 is connected with the earth terminal GND of time calibrator, output+V1 ,+V2 that the 7th pin of power module U4 is insulating power supply or+V3; The 7th foot meridian capacitor C2 of power module U4 is connected with isolation earth point GND1, GND2 or GND3.
aforementioned time calibrator is with in low delay output interface circuit, and described empty node output interface passage comprises the identical empty node subchannel of two-way; Empty node subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, empty node output circuit and the output protection circuit that are connected in series successively; Buffering and the optocoupler drive circuit input of the empty node subchannel of two-way are connected with input signal end IN1 and input signal end IN2 respectively; The output signal common port of receiving after output protection circuit of the empty node subchannel of two-way is connected with lead-out terminal I respectively; The output signal end of receiving after output protection circuit of the empty node subchannel in one tunnel is connected with lead-out terminal II, and the output signal end of receiving after output protection circuit of the empty node subchannel in another road is connected with lead-out terminal III; The buffering of the empty node subchannel of two-way and optocoupler drive circuit power supply directly with from time calibrator inside+5V DC power supply is connected; The high speed optoelectronic coupling circuit of the empty node subchannel of two-way and empty node output circuit power supply respectively with the output+V1 of two DC/DC buffer circuits and+V2 is connected.
aforementioned time calibrator is with in low delay output interface circuit, and described Transistor-Transistor Logic level output interface passage comprises the identical Transistor-Transistor Logic level subchannel of two-way; Transistor-Transistor Logic level subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, Transistor-Transistor Logic level output circuit and the output protection circuit that are connected in series successively; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler drive circuit input are connected with input signal end IN1 and input signal end IN2 respectively; The isolation earth point GND3 of two-way Transistor-Transistor Logic level subchannel is connected with lead-out terminal ⊥; The output signal end of receiving after output protection circuit of one road Transistor-Transistor Logic level subchannel is connected with lead-out terminal A, and the output signal end of receiving after output protection circuit of another road Transistor-Transistor Logic level subchannel is connected with lead-out terminal B; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler drive circuit power supply all directly with from time calibrator inside+5V DC power supply is connected; The high speed optoelectronic coupling circuit of two-way Transistor-Transistor Logic level subchannel is connected with the output+V3 of DC/DC buffer circuit with Transistor-Transistor Logic level output circuit power supply.
aforementioned time calibrator is with in low delay output interface circuit, and described empty node output circuit adopts high speed, the high withstand voltage N-MOS triode Q1 that model is BSP89, and Q1 connects into open-drain form; The source electrode of triode Q1 is connected ground connection with isolation earth point GND1 or GND2, and drain electrode is connected with accelerating circuit and bridge rectifier, and grid is signal input part, is parallel with resistance R 4 between grid and source electrode; Accelerating circuit is in series by diode D1 and resistance R 3, the output+V1 of the positive pole of diode D1 and DC/DC buffer circuit or+V2 is connected; Resistance R 3 is connected with the drain electrode of triode Q1; Accelerating circuit makes to shorten approximately 50% the deadline of triode Q1; Bridge rectifier is in order to eliminate the polarity effect of checked object, and the positive pole of bridge rectifier is connected with the drain electrode of triode Q1, and the negative pole of bridge rectifier is connected with isolation earth point GND1 or GND2; Two ac output ends of bridge rectifier are the signal output part being connected with output protection circuit.
aforementioned time calibrator is with in low delay output interface circuit, and described Transistor-Transistor Logic level output circuit comprises that model is the integrated circuit U3 of NC7SZ04, and the 3rd pin of integrated circuit U3 is connected with isolation earth point GND3, and the 5th pin is connected with insulating power supply+V3; Insulating power supply+V3 is ground connection after resistance R 5 and resistance R 6 series connection, and resistance R 5 is connected with the tie point of resistance R 6 and the 2nd pin of integrated circuit U3; The 4th pin of integrated circuit U3 is output, is connected with output protection circuit through resistance R 7.
aforementioned time calibrator is with in low delay output interface circuit, and the output protection circuit of described empty node subchannel and Transistor-Transistor Logic level subchannel comprises TBU protection device F1, fusing type insurance F2 and gas discharge tube D7; One end of TBU protection device F1, fusing type insurance F2 and gas discharge tube D7 links together, the fusing type insurance other end of F2 and lead-out terminal II or the lead-out terminal III of empty node output interface passage are connected, or fusing type insures the other end of F2 and lead-out terminal A or the lead-out terminal B of Transistor-Transistor Logic level output interface passage are connected; The other end of gas discharge tube D7 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage; The other end of TBU protection device F1 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage through Transient Suppression Diode D6; The two ends of Transient Suppression Diode D6 are the input point being connected with empty node output circuit or Transistor-Transistor Logic level output circuit, and the Transient Suppression Diode D6 model of empty node subchannel is SMAJ90CA; The Transient Suppression Diode D6 model of Transistor-Transistor Logic level subchannel is CDSOD323-T05C.
aforementioned time calibrator is with in low delay output interface circuit, the buffering of described empty node subchannel and Transistor-Transistor Logic level subchannel and optocoupler drive circuit comprise that model is the integrated circuit U1 of NC7SZ04, the 3rd pin of integrated circuit U1 is connected with the earth terminal GND of time calibrator, and the 5th pin is connected with the power input+V in DC/DC buffer circuit; The 2nd pin is that signal input part is connected with input signal IN1 or input signal IN2, and the 4th pin is output, is connected with an input of high-speed photoelectric coupler, and the 5th pin is connected with another input of high speed optoelectronic coupling circuit through resistance R 1.
aforementioned time calibrator is with in low delay output interface circuit, the high speed optoelectronic coupling circuit of described empty node subchannel and Transistor-Transistor Logic level subchannel comprises that model is the integrated circuit U2 of 6N137, the 5th pin of integrated circuit U2 is connected with isolation earth terminal GND1, GND2 or GND3, the 8th pin connect insulating power supply+V1 ,+V2 or+V3; The 2nd pin and the 3rd pin of integrated circuit U2 are signal input part, between the 8th pin of integrated circuit U2 and the 6th pin, are parallel with resistance R 2, and resistance R 2 two ends are that signal output part is connected with empty node output circuit or Transistor-Transistor Logic level output circuit.
compared with prior art, time calibrator output interface circuit provided by the invention not only can be in newly-designed time calibrator directly adopts, and also can make independently circuit board or module the time calibrator of former production is carried out to transformation and upgrade.Output interface circuit time delay of the present invention is little, strong adaptability, makes time calibrator can meet whole calibration operations of pointer electrical secondmeter, digital electric stopwatch and digital millisecond instrument simultaneously.The present invention has perfect output protection measure and can greatly improve reliability and the durability of time calibrator.
Brief description of the drawings
fig. 1 is structural representation of the present invention;
fig. 2 is the structured flowchart of sky node output interface passage;
fig. 3 is the electrical schematic diagram of sky node output interface passage;
fig. 4 is sky node output circuit schematic diagram;
fig. 5 is the structured flowchart of Transistor-Transistor Logic level output interface passage;
fig. 6 is the electrical schematic diagram of Transistor-Transistor Logic level output interface passage;
fig. 7 is DC/DC buffer circuit schematic diagram;
fig. 8 is Transistor-Transistor Logic level output circuit schematic diagram.
fig. 9 is output protection circuit schematic diagram;
figure 10 is buffering and optocoupler driving circuit principle figure;
figure 11 is high speed optoelectronic coupling circuit schematic diagram.
Embodiment
below in conjunction with drawings and Examples, the present invention is further illustrated, but not as the foundation to the present invention's restriction.
embodiment.
a kind of time calibrator low delay output interface circuit, as shown in Figure 1.This circuit comprises and is mainly used in the empty node output interface passage of pointer electrical secondmeter calibrating and the Transistor-Transistor Logic level output interface passage for digital electric stopwatch or the calibrating of digital millisecond instrument; The maximum delay of empty node output interface passage is less than 0.5 μ s; Transistor-Transistor Logic level output interface passage maximum delay is less than 0.2 μ s; From two-way standard time of time calibrator every the input signal end IN1 of signal and input signal end IN2 simultaneously as the input signal end of empty node output interface passage and Transistor-Transistor Logic level output interface passage; Empty node output interface passage and Transistor-Transistor Logic level output interface passage are respectively equipped with three outputs.This circuit is realized the electric insulation of time calibrator low delay output interface circuit and time calibrator by high speed optoelectronic coupling circuit and DC/DC buffer circuit, eliminate influencing each other and disturbing between empty node output interface passage and Transistor-Transistor Logic level output interface passage and time calibrator.
this circuit is made up of empty node output interface passage and Transistor-Transistor Logic level output interface passage two parts.Empty node output interface passage is mainly used in the calibrating of pointer electrical secondmeter, also can be as required for the calibrating of digital electric stopwatch and digital millisecond instrument.Transistor-Transistor Logic level output interface passage is for the calibrating of digital electric stopwatch and digital millisecond instrument.Input signal is that two-way standard time of producing from time calibrator internal microprocessor or inner other digital circuit is every signal IN1 and IN2.
in order to improve accuracy of detection, the standard time should be as far as possible little every total time delay of each passage of signal IN1 and IN2 process, to composition transmission channel each unit and components and parts model is well-designed and select.According to national verification code, to the related request of time calibrator accuracy be: be better than while examining and determine pointer electrical secondmeter ± 0.6ms(internal frequency oscillator is synchronizeed with civil power); When calibrating digital electric stopwatch, be better than ± (5 × 10
-7
× output time interval+0.01ms); While examining and determine digital millisecond instrument, be better than ± (5 × 10
-7
× output time interval+3 μ s).The highest to the requirement of time calibrator accuracy while examining and determine as can be seen here digital millisecond instrument.3 μ s are requirements of the maximum intrinsic error to time calibrator.This intrinsic error is caused by microprocessor or other digital circuit of output interface circuit and time calibrator rise time blank signal.For making the maximum intrinsic error of time calibrator be less than 3 μ s, maximum delay index request of the present invention is as follows: empty node output interface passage is less than 0.5 μ s; Transistor-Transistor Logic level output interface passage is less than 0.2 μ s.
as shown in Figures 2 and 3, aforementioned empty node output interface passage comprises the identical empty node subchannel of two-way; Empty node subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, empty node output circuit and the output protection circuit that are connected in series successively; Buffering and the optocoupler drive circuit input of the empty node subchannel of two-way are connected with input signal end IN1 and input signal end IN2 respectively; The output signal common port of receiving after output protection circuit of the empty node subchannel of two-way is connected with lead-out terminal I; The output signal end of receiving after output protection circuit of the empty node subchannel in one tunnel is connected with lead-out terminal II, and the output signal end of receiving after output protection circuit of the empty node subchannel in another road is connected with lead-out terminal III; The buffering of the empty node subchannel of two-way and optocoupler drive circuit power supply directly with from time calibrator inside+5V DC power supply is connected; The high speed optoelectronic coupling circuit of the empty node subchannel of two-way and empty node output circuit power supply respectively with the output+V1 of two DC/DC buffer circuits and+V2 is connected.
empty node output interface passage comprises the identical empty node subchannel of two-way; One tunnel is the passage of standard time every signal IN1, and another road is the passage of standard time every signal IN2.The two-way standard time of input has 4 kinds of different compound modes every signal, is respectively the signal of single channel negative pulse normal width, signal, the signal of two-way positive pulse normal space and the signal of two-way negative pulse normal space of single channel positive pulse normal width.Empty node subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, empty node output circuit and the output protection circuit that are connected in series successively; Buffering and the optocoupler drive circuit input of the empty node subchannel of two-way are connected with input signal end IN1 and IN2 respectively; The output signal common port of receiving after output protection circuit of the empty node subchannel of two-way is connected with lead-out terminal I; The output signal end of receiving after output protection circuit of the empty node subchannel in one tunnel is connected with lead-out terminal II, and the output signal end that the output protection circuit after sky node subchannel is received on another road is connected with lead-out terminal III; Corresponding to the input signal of four kinds of various combination modes, be respectively from the aspect of empty node output interface passage I, II, the output of III end: the time interval when time interval of closed duration of a pair of empty node, a pair of empty node disconnection duration, two pairs of empty node disconnections and two pairs of empty nodes priority moments are closed; The buffering of the empty node subchannel of two-way and optocoupler drive circuit power supply are directly connected with+5V DC power supply; The high speed optoelectronic coupling circuit of the empty node subchannel of two-way and empty node output circuit power supply are connected with+5V DC power supply through DC/DC buffer circuit respectively.The benefit of bringing is thus: the one, realize the electric insulation of output circuit and time calibrator and other circuit.Eliminate by influencing each other between other circuit of calibrating instrument between the test examination instrument while, prevent the interference to time calibrator microprocessor portion by test examination instrument.Particularly in the time of the pointer electrical secondmeter of calibrating, due to naked between the input of some pointer electrical secondmeter and 220V civil power, the output of slightly not noting time calibrator is likely charged, if naked between other circuit of time calibrator output and time calibrator, likely makes time calibrator complete machine add dangerous voltage.This safety to testing person and time calibrator self is one and threatens greatly.Use high speed optoelectronic coupling circuit and DC/DC isolating converter to realize electric insulation, this threat is eliminated.The 2nd, make being removed publicly between two subchannels of sky node output channel, just in addition interconnected while in the end output, thus can be from the time interval signal of I, II, the more than 4 kinds compound mode of three outputs outputs of III.Need to adopt relay that time delay is very large to switch the drawback of output signal compound mode with regard to having overcome empty node output channel circuit in the past like this.
as shown in Figure 5 and Figure 6, aforementioned Transistor-Transistor Logic level output interface passage comprises the identical Transistor-Transistor Logic level subchannel of two-way; One tunnel is the passage of standard time every signal IN1, and another road is the passage of standard time every signal IN2.The two-way standard time of input has 4 kinds of different compound modes every signal, is respectively the signal of single channel negative pulse normal width, signal, the signal of two-way positive pulse normal space and the signal of two-way negative pulse normal space of single channel positive pulse normal width.Transistor-Transistor Logic level subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, Transistor-Transistor Logic level output circuit and the output protection circuit that are connected in series successively; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler drive circuit input are connected with input signal end IN1 and input signal end IN2 respectively; Corresponding to the input signal of four kinds of various combination modes, hold the aspect of output to be respectively from Transistor-Transistor Logic level output interface passage ⊥, A, B: the time interval when time interval of closed duration of a pair of Transistor-Transistor Logic level, a pair of Transistor-Transistor Logic level disconnection duration, two pairs of Transistor-Transistor Logic level disconnections and two pairs of Transistor-Transistor Logic levels priority moments are closed; The earth point of two-way Transistor-Transistor Logic level subchannel is connected with lead-out terminal ⊥ respectively; The output signal of the output protection circuit of one road Transistor-Transistor Logic level subchannel is connected with lead-out terminal A, and the output signal of the output protection circuit of another road Transistor-Transistor Logic level subchannel is connected with lead-out terminal B; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler driving power are directly connected with+5V DC power supply; The high speed optoelectronic coupling circuit of two-way Transistor-Transistor Logic level subchannel and Transistor-Transistor Logic level output circuit power supply are connected with+5V DC power supply through DC/DC buffer circuit.The benefit of bringing is thus as empty node subchannel.The one, realize the electric insulation of output circuit and time calibrator and other circuit.Eliminate by influencing each other between other circuit of calibrating instrument between the test examination instrument while, prevent the interference to time calibrator microprocessor portion by test examination instrument.Use high speed optoelectronic coupling circuit and DC/DC isolating converter to realize electric insulation, this threat is eliminated.The 2nd, make being removed publicly between two subchannels of Transistor-Transistor Logic level output channel, just in addition interconnected while in the end output, thus can be from the time interval signal of ⊥, A, the more than 4 kinds compound mode of tri-outputs outputs of B.Need to adopt relay that time delay is very large to switch the drawback of output signal compound mode with regard to having overcome Transistor-Transistor Logic level output channel circuit in the past like this.
as shown in Figure 4, aforementioned empty node output circuit adopts the N-MOS triode Q1 that model is BSP89 to connect into open-drain form; The feature that uses N-MOS triode to make open-drain circuit is that input resistance height can directly drive, time delay is little.By analysis and the experiment of the bipolar transistor to Multiple Type and MOS triode, the form of open-circuit and the concrete model of MOS triode in empty node output circuit of the present invention are finally selected.Its operating current, withstand voltage and time delay can meet the requirement of different checked objects completely.The source ground of triode Q1, drain electrode is connected with accelerating circuit and bridge rectifier, and grid is signal input part, is parallel with resistance R 4 between grid and source electrode; Accelerating circuit is in series by a Schottky diode D1 and a resistance R 3, and accelerating circuit makes to shorten approximately 50% the deadline of triode Q1; Bridge rectifier is in order to eliminate the polarity effect of checked object.Bridge rectifier is received the output of N-MOS triode open-drain circuit, realizes the nonpolarity empty node analog interface of checked object.Bridge rectifier is made up of Schottky diode.The Schottky diode of selected model has withstand voltage height, speed is fast and pressure drop is low feature.
as shown in Figure 8, aforementioned Transistor-Transistor Logic level output circuit comprises that model is the integrated circuit U3 of NC7SZ04, and the 3rd pin of integrated circuit U3 is connected with isolation earth point GND3, and the 5th pin is connected with insulating power supply+V3; Insulating power supply+V3 is ground connection after resistance R 5 and resistance R 6 series connection, and resistance R 5 is connected with the tie point of resistance R 6 and the 2nd pin of integrated circuit U3; The 4th pin of integrated circuit U3 is output, is connected with output protection circuit through resistance R 7.It is the CMOS ultrahigh speed inverse gate of NC7SZ04 that this circuit is selected model, and the propagation delay time is minimum, and output driving force is large, can easily drive follow-up various digital electric stopwatches and digital millisecond instrument.
as shown in Figure 9, the output protection circuit of aforementioned empty node subchannel and Transistor-Transistor Logic level subchannel comprises TBU protection device F1, fusing type insurance F2 and gas discharge tube D7; One end of TBU protection device F1, fusing type insurance F2 and gas discharge tube D7 links together, the fusing type insurance other end of F2 and lead-out terminal II or the lead-out terminal III of empty node output interface passage are connected, or fusing type insures the other end of F2 and lead-out terminal A or the lead-out terminal B of Transistor-Transistor Logic level output interface passage are connected; The other end of gas discharge tube D7 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage; The other end of TBU protection device F1 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage through Transient Suppression Diode D6; The two ends of Transient Suppression Diode D6 are the input point being connected with empty node output circuit or Transistor-Transistor Logic level output circuit, and the Transient Suppression Diode D6 model of empty node subchannel is SMAJ90CA; The Transient Suppression Diode D6 model of Transistor-Transistor Logic level subchannel is CDSOD323-T05C.This circuit uses advanced circuit protection technology, the output interface of time calibrator is carried out to the quick protection of overcurrent-overvoltage, prevents from causing because of line wrong the damage of output circuit in the time of calibrating.As with forward part calibration authority in the use procedure of time calibrator, because kind and the model of tested instrument are various, sometimes by by the 220V power supply misconnection of test examination instrument to the output of time calibrator, thereby cause time calibrator damage.
as shown in figure 10, the buffering of aforementioned empty node subchannel and Transistor-Transistor Logic level subchannel and optocoupler drive circuit comprise that model is the integrated circuit U1 of NC7SZ04, the 3rd pin of integrated circuit U1 is connected with the earth terminal GND of time calibrator, and the 5th pin is connected with the power input+V in DC/DC buffer circuit; The 2nd pin is that signal input part is connected with input signal IN1 or input signal IN2, and the 4th pin is output, is connected with an input of high speed optoelectronic coupling circuit, and the 5th pin is connected with another input of high speed optoelectronic coupling circuit through resistance R 1.
as shown in figure 11, the high speed optoelectronic coupling circuit of aforementioned empty node subchannel and Transistor-Transistor Logic level subchannel comprises that model is the CMOS ultrahigh speed inverse gate integrated circuit U2 of 6N137, and its maximum traffic delay time is 75ns, isolation voltage 2500V.Meet the requirement of transmission low delay and seperating safety.The 5th pin of integrated circuit U2 is connected with isolation earth terminal GND1, GND2 or GND3, the 8th pin connect insulating power supply+V1 ,+V2 or+V3; The 2nd pin and the 3rd pin of integrated circuit U2 are signal input part, between the 8th pin of integrated circuit U2 and the 6th pin, are parallel with resistance R 2, and the 8th pin of integrated circuit U2 is that signal output part is connected with empty node output circuit or Transistor-Transistor Logic level output circuit with the 6th pin.This circuit is selected the CMOS ultrahigh speed inverse gate identical with buffering and optocoupler drive circuit, and the propagation delay time is minimum, and output driving force is large, can easily drive follow-up various digital electric stopwatches and digital millisecond instrument.
as shown in Figure 7, aforementioned time calibrator is provided with three DC/DC buffer circuits with low delay output interface circuit; DC/DC buffer circuit comprises that model is the high insulating power supply module U4 of H0505S-1W, and the 2nd pin of power module U4 is connected with the earth terminal GND of time calibrator, and the 5th pin of power module U4 is connected with isolation earth point GND1, GND2 or GND3; From time calibrator inside+5V power supply is connected with the 1st pin of power module U4 through polymeric switch P1, the 1st foot meridian capacitor C1 of power module U4 is connected with the earth terminal GND of time calibrator, output+V1 ,+V2 that the 7th pin of power module U4 is insulating power supply or+V3; The 7th foot meridian capacitor C2 of power module U4 is connected with isolation earth point GND1, GND2 or GND3.Empty node output interface passage uses two DC/DC isolating converters, and the high speed optoelectronic coupling circuit of the empty node subchannel of two-way and empty node output circuit are connected with+5V DC power supply through DC/DC buffer circuit respectively.Transistor-Transistor Logic level output interface passage uses 1 DC/DC isolating converter, be added to of the present invention+5V power supply after DC/DC isolating converter, export isolate+5V power supply, simultaneously for photoelectrical coupler primary side and the Transistor-Transistor Logic level output circuit of two-way subchannel.
supplementary notes of the present invention:
in empty node output circuit (see figure 4), the model of N-MOS triode Q2 is BSP89, is connected into open-drain circuit, its source ground GND, and drain electrode is received on accelerating circuit and bridge rectifier.Diode D1 and resistance R 3 are composed in series charging accelerating circuit.Diode D1 model is STPS1150A.The positive pole of D1 is received insulating power supply+V1 ,+V2.The other end of R3 is received the drain electrode of triode Q2.Diode D2, D3, D4 and D5 are model STPS1150A, are connected into full-wave bridge rectifier circuit.The output cathode of this full-wave bridge rectifier circuit is connected with the drain electrode of Q2, and output negative pole is received GND1, GND2 isolator, and two of full-wave bridge rectifier circuit exchange node and are connected with output protection circuit.
the model of CMOS ultrahigh speed inverse gate integrated circuit U3 in Transistor-Transistor Logic level output circuit (see figure 8) is NC7SZ04.Integrated circuit U3 the 2nd pin input was connected every signal with the standard time, and the 1st pin is unsettled; The 5th pin is received insulating power supply+V3; The 3rd pin meets GND3 isolator; The 4th pin is that reversed-phase output drives current-limiting resistance R7 to be connected with output protection circuit through optocoupler.
in output protection circuit (see figure 9), the model of TBU protection device F1 is TBU-CA085-100-WH; its one end is connected with the output of empty node output circuit or TTL circuit output circuit, and the other end is connected with the tie point of fusing type insurance F2 and gas discharge tube D7.The model of fusing type insurance F2 is 0461.500ER, the fusing type insurance other end of F2 and lead-out terminal II or the lead-out terminal III of empty node output interface passage are connected, or fusing type insures the other end of F2 and lead-out terminal A or the lead-out terminal B of Transistor-Transistor Logic level output interface passage are connected; The model of gas discharge tube D7 is 2027-47-BLF, and its other end is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage.The operation principle of output protection circuit is: if too high transient voltage or continuous voltage enter sky node passage, the first action of TVS pipe, is restricted to dangerous voltage in safe range.If now exceed protective current by the electric current of TBU current protection device, TBU current protection device moves rapidly, and electric current is turn-offed, and the node passage that makes to have leisure is protected.Withstand voltage not high due to TBU current protection device, is generally 850V, and higher voltage will damage TBU, and therefore circuit uses again gas discharge tube to carry out voltage protection to TBU.The operation voltage of gas discharge tube is chosen and is less than on TBU withstand voltage.And the larger impact of energy may cause the damage of gas discharge tube, therefore add the insurance of fusing type as protection at the afterbody of output.This combined protection mode node passage that makes to have leisure is thoroughly protected.
buffering in empty node subchannel and Transistor-Transistor Logic level subchannel and optocoupler drive circuit (see figure 10), high speed optoelectronic coupling circuit (seeing Figure 11), output protection circuit (see figure 9) are all identical with DC/DC buffer circuit (see figure 7), output protection circuit in its hollow node subchannel is different with the Transient Suppression Diode D6 model in the output protection circuit in Transistor-Transistor Logic level subchannel, and the model of the Transient Suppression Diode D6 of empty node subchannel is SMAJ90CA; The model of the Transient Suppression Diode D6 of Transistor-Transistor Logic level subchannel is CDSOD323-T05C.
Claims (8)
1. a time calibrator low delay output interface circuit, is characterized in that: this circuit comprises and is mainly used in the empty node output interface passage of pointer electrical secondmeter calibrating and the Transistor-Transistor Logic level output interface passage for digital electric stopwatch or the calibrating of digital millisecond instrument; The maximum delay of empty node output interface passage is less than 0.5 μ s; Transistor-Transistor Logic level output interface passage maximum delay is less than 0.2 μ s; From two-way standard time of time calibrator every the input signal end IN1 of signal and input signal end IN2 simultaneously as the input signal end of empty node output interface passage and Transistor-Transistor Logic level output interface passage; Empty node output interface passage and Transistor-Transistor Logic level output interface passage are respectively equipped with three outputs; Empty node output interface passage comprises the identical empty node subchannel of two-way; Empty node subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, empty node output circuit and the output protection circuit that are connected in series successively; Buffering and the optocoupler drive circuit input of the empty node subchannel of two-way are connected with input signal end IN1 and input signal end IN2 respectively; The output signal common port of receiving after output protection circuit of the empty node subchannel of two-way is connected with lead-out terminal I; The output signal end of receiving after output protection circuit of the empty node subchannel in one tunnel is connected with lead-out terminal II, and the output signal end of receiving after output protection circuit of the empty node subchannel in another road is connected with lead-out terminal III; The buffering of the empty node subchannel of two-way and optocoupler drive circuit power supply directly with from time calibrator inside+5V DC power supply is connected; The high speed optoelectronic coupling circuit of the empty node subchannel of two-way and empty node output circuit power supply respectively with the output+V1 of two DC/DC buffer circuits and+V2 is connected; Transistor-Transistor Logic level output interface passage comprises the identical Transistor-Transistor Logic level subchannel of two-way; Transistor-Transistor Logic level subchannel comprises the buffering and optocoupler drive circuit, high speed optoelectronic coupling circuit, Transistor-Transistor Logic level output circuit and the output protection circuit that are connected in series successively; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler drive circuit input are connected with input signal end IN1 and input signal end IN2 respectively; The isolation earth point GND3 of two-way Transistor-Transistor Logic level subchannel is connected with lead-out terminal ⊥; The output signal end of receiving after output protection circuit of one road Transistor-Transistor Logic level subchannel is connected with lead-out terminal A, and the output signal end of receiving after output protection circuit of another road Transistor-Transistor Logic level subchannel is connected with lead-out terminal B; The buffering of two-way Transistor-Transistor Logic level subchannel and optocoupler drive circuit power supply all directly with from time calibrator inside+5V DC power supply is connected; The high speed optoelectronic coupling circuit of two-way Transistor-Transistor Logic level subchannel is connected with the output+V3 of DC/DC buffer circuit with Transistor-Transistor Logic level output circuit power supply.
2. time calibrator low delay output interface circuit according to claim 1, it is characterized in that: this circuit is realized the electric insulation of time calibrator low delay output interface circuit and time calibrator by high speed optoelectronic coupling circuit and DC/DC buffer circuit, eliminate influencing each other and disturbing between empty node output interface passage and Transistor-Transistor Logic level output interface passage and time calibrator.
3. time calibrator low delay output interface circuit according to claim 1, is characterized in that: described time calibrator low delay output interface circuit is provided with three DC/DC buffer circuits; DC/DC buffer circuit comprises that model is the high insulating power supply module U4 of H0505S-1W, and the 2nd pin of power module U4 is connected with the earth terminal GND of time calibrator, and the 5th pin of power module U4 is connected with isolation earth point GND1, GND2 or GND3; From time calibrator inside+5V power supply is connected with the 1st pin of power module U4 through polymeric switch P1, the 1st foot meridian capacitor C1 of power module U4 is connected with the earth terminal GND of time calibrator, output+V1 ,+V2 that the 7th pin of power module U4 is insulating power supply or+V3; The 7th foot meridian capacitor C2 of power module U4 is connected with isolation earth point GND1, GND2 or GND3.
4. time calibrator low delay output interface circuit according to claim 1, is characterized in that: described empty node output circuit adopts high speed, the high withstand voltage N-MOS triode Q1 that model is BSP89, and Q1 connects into open-drain form; The source electrode of triode Q1 is connected with isolation earth point GND1 or GND2, and drain electrode is connected with accelerating circuit and bridge rectifier, and grid is signal input part, is parallel with resistance R 4 between grid and source electrode; Accelerating circuit is in series by diode D1 and resistance R 3, the output+V1 of the positive pole of diode D1 and DC/DC buffer circuit or+V2 is connected; Resistance R 3 is connected with the drain electrode of triode Q1; Accelerating circuit makes to shorten approximately 50% the deadline of triode Q1; Bridge rectifier is in order to eliminate the polarity effect of checked object, and the positive pole of bridge rectifier is connected with the drain electrode of triode Q1, and the negative pole of bridge rectifier is connected with isolation earth point GND1 or GND2; Two ac output ends of bridge rectifier are the signal output part being connected with output protection circuit.
5. time calibrator low delay output interface circuit according to claim 1, it is characterized in that: described Transistor-Transistor Logic level output circuit comprises that model is the integrated circuit U3 of NC7SZ04, the 3rd pin of integrated circuit U3 is connected with isolation earth point GND3, and the 5th pin is connected with insulating power supply+V3; Insulating power supply+V3 is ground connection after resistance R 5 and resistance R 6 series connection, and resistance R 5 is connected with the tie point of resistance R 6 and the 2nd pin of integrated circuit U3; The 4th pin of integrated circuit U3 is output, is connected with output protection circuit through resistance R 7.
6. time calibrator low delay output interface circuit according to claim 1, is characterized in that: the output protection circuit of described empty node subchannel and Transistor-Transistor Logic level subchannel comprises TBU protection device F1, fusing type insurance F2 and gas discharge tube D7; One end of TBU protection device F1, fusing type insurance F2 and gas discharge tube D7 links together, the fusing type insurance other end of F2 and lead-out terminal II or the lead-out terminal III of empty node output interface passage are connected, or fusing type insures the other end of F2 and lead-out terminal A or the lead-out terminal B of Transistor-Transistor Logic level output interface passage are connected; The other end of gas discharge tube D7 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage; The other end of TBU protection device F1 is connected with the lead-out terminal I of empty node output interface passage or the lead-out terminal ⊥ of Transistor-Transistor Logic level output interface passage through Transient Suppression Diode D6; The two ends of Transient Suppression Diode D6 are the input point being connected with empty node output circuit or Transistor-Transistor Logic level output circuit, and the Transient Suppression Diode D6 model of empty node subchannel is SMAJ90CA; The Transient Suppression Diode D6 model of Transistor-Transistor Logic level subchannel is CDSOD323-T05C.
7. time calibrator low delay output interface circuit according to claim 1, it is characterized in that: the buffering of described empty node subchannel and Transistor-Transistor Logic level subchannel and optocoupler drive circuit comprise that model is the integrated circuit U1 of NC7SZ04, the 3rd pin of integrated circuit U1 is connected with the earth terminal GND of time calibrator, and the 5th pin is connected with the power input+V in DC/DC buffer circuit; The 2nd pin is that signal input part is connected with input signal IN1 or input signal IN2, and the 4th pin is output, is connected with an input of high speed optoelectronic coupling circuit, and the 5th pin is connected with another input of high speed optoelectronic coupling circuit through resistance R 1.
8. time calibrator low delay output interface circuit according to claim 1, it is characterized in that: the high speed optoelectronic coupling circuit of described empty node subchannel and Transistor-Transistor Logic level subchannel comprises that model is the integrated circuit U2 of 6N137, the 5th pin of integrated circuit U2 is connected with isolation earth terminal GND1, GND2 or GND3, the 8th pin connect insulating power supply+V1 ,+V2 or+V3; The 2nd pin and the 3rd pin of integrated circuit U2 are signal input part, between the 8th pin of integrated circuit U2 and the 6th pin, are parallel with resistance R 2, and resistance R 2 two ends are that signal output part is connected with empty node output circuit or Transistor-Transistor Logic level output circuit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2833664Y (en) * | 2005-05-18 | 2006-11-01 | 成都飞机工业（集团）有限责任公司 | Digital multifunctional time calibrator |
| EP1954104A1 (en) * | 2007-01-31 | 2008-08-06 | TridonicAtco Schweiz AG | Interface for switch signals and digital signals with protective circuit |
| CN202513905U (en) * | 2012-03-29 | 2012-10-31 | 贵州省计量测试院 | Low-delay output interface circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2833664Y (en) * | 2005-05-18 | 2006-11-01 | 成都飞机工业（集团）有限责任公司 | Digital multifunctional time calibrator |
| EP1954104A1 (en) * | 2007-01-31 | 2008-08-06 | TridonicAtco Schweiz AG | Interface for switch signals and digital signals with protective circuit |
| CN202513905U (en) * | 2012-03-29 | 2012-10-31 | 贵州省计量测试院 | Low-delay output interface circuit |
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| 基于单片机89C51的时间继电器现场检定仪;罗均等;《仪器仪表学报》;20040831;第25卷(第4期);第161-164页 * |
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