CN102710237A - First-order digital low-pass filtering method, filter and electronic equipment - Google Patents
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- CN102710237A CN102710237A CN2012101969282A CN201210196928A CN102710237A CN 102710237 A CN102710237 A CN 102710237A CN 2012101969282 A CN2012101969282 A CN 2012101969282A CN 201210196928 A CN201210196928 A CN 201210196928A CN 102710237 A CN102710237 A CN 102710237A
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Abstract
The invention provides a first-order digital low-pass filtering method, a filter and electronic equipment and belongs to the technical field of digital signal processing. The first-order digital low-pass filtering method comprises the following steps of shifting a first sampling value leftwards for a first integer bit by a first shift register; carrying out shifting operation with corresponding digit on the left shifting result of the first shift register by second shift registers; adding data subjected to shifting by each second shift register by a first adding device; determining the number of the first adding devices and the number of the second shift registers according to a first filtering coefficient; determining the shifting digit of each second shift register; shifting the addition result of the first adding device rightwards for a first integer bit by each third shift register; and obtaining the filtered sampling value according to the right shifting result of the third shift register by the second adding device. The multiply operation is converted into shift operation, so that the implementation penalty can be reduced.
Description
Technical field
The present invention relates to digital signal processing technique field, particularly a kind of single order digital low-pass filtering method, filter and electronic equipment.
Background technology
In many embedded systems (like sub-district safety-protection system, Internet of Things node etc.), a large amount of on-the-spot physical signalling (pyroelectricity, smog, coal gas etc.) needs measured, and this mainly accomplishes by transducer.Transducer becomes the variation of the signal of telecommunication to the change transitions of physical quantity (pyroelectricity, smog, coal gas etc.), and passes to microprocessor processes through specific circuit; This type systematic all is to operate in some open environment, some noise signals so the output of signal usually can superpose, and the variation that is exactly these signals in addition all is very faint, all is usually in the scope of millivolt or milliampere level, to change; Therefore will carry out filtering to the analog signal of transducer output, and the frequency that these signals change is all lower, so traditional filtering method all adopts single order digital low-pass filtering method, shown in formula one:
Y(n)=(1-a)*X(n)+a*Y(n-1)
In the formula: Y (n)-----filtered the n time sampled value;
The n time sampled value of X (n)-----non-filtered;
Y (n-1)-----filtered the n-1 time sampled value;
The a-----filter factor is in [1,0] interval value;
Filter factor a in the formula one, the expression time constant filter and the ratio in sampling period are formula two:
In the formula: the Tf-----time constant filter;
The T-----sampling period;
As sampling period T the time much smaller than time constant filter Tf, this algorithm of equal value with single order RC analog filter, PERIODIC INTERFERENCE is had good inhibition effect, be applicable to the occasion that vibration frequency is higher.Its weak point is that the microprocessor in the system is required height, because the processing multiplying is very expensive source and time, microprocessor can take much time and resource is handled filtering algorithm; Particularly in the system that has FPGA and CPLD to participate in, if realize multiplying with hardware, that cost is expensive.
This shows in the prior art and exist: the single order wave digital lowpass filter is realized the arm and a leg problem of multiplying.
Summary of the invention
In order to address the above problem; The purpose of the embodiment of the invention provides a kind of single order digital low-pass filtering method, filter and electronic equipment; Exist in the solution prior art, the single order wave digital lowpass filter is realized the arm and a leg problem of multiplying, and this method comprises:
First shift register to first sampled value to first integer-bit that moves to left, first sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before one of sampled value;
The result that second shift register moves to left first shift register carries out the shifting function of corresponding figure place;
First adder is wherein confirmed the number of first adder and the number of second shift register according to first filter factor through the data addition after each second shift register displacement, and the displacement figure place of confirming each second shift register;
The 3rd shift register is with the addition result of first adder, and first integer-bit moves to right;
Second adder obtains this filtered sampled value according to the result that the 3rd shift register moves to right.
Further, also comprise:
The 4th shift register to second sampled value to second integer-bit that moves to left, second sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before in sampled value another;
The result that the 5th shift register moves to left the 4th shift register carries out the shifting function of corresponding figure place;
Data addition the 3rd adder is shifted each through the 5th shift register after; Wherein confirm the number of the 3rd adder and the number of the 5th shift register according to second filter factor; And the displacement figure place of confirming each the 5th shift register, first filter factor and the second filter factor sum are 1;
The 6th shift register is with the addition result of the 3rd adder, and second integer-bit moves to right;
Second adder obtains this filtered sampled value and is specially according to the result that the 3rd shift register moves to right:
The results added that result that second adder moves to right the 3rd shift register and the 6th shift register move to right obtains this filtered sampled value.
Further, also comprise:
The 7th shift register arrives current the n time sampled value b-1 time before to non-filtered, and to the 3rd integer-bit that moves to left, the value of b is 2 integral number power, and n is a positive integer, and n is greater than b-1;
The 4th adder is the storing value addition in the output of the 7th shift register and first register;
The output of the first register-stored first adder, and b the back first register zero clearing of first adder addition;
The 8th shift register is with the output valve after first adder addition b time, and the b position that moves right obtains first sampled value.
Further, also comprise:
The 9th shift register is exported the 3rd integer-bit that moves to right with second adder, obtains this filtered sampled value.
Further, first sampled value is the current sampled value of non-filtered.
The embodiment of the invention also provides a kind of single order wave digital lowpass filter, comprising:
First shift register, its to first sampled value to first integer-bit that moves to left, first sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before one of sampled value;
Second shift register, the result that it moves to left first shift register carries out the shifting function of corresponding figure place;
First adder, the data addition after each second shift register displacement of its process is wherein confirmed the number of first adder and the number of second shift register according to first filter factor, and the displacement figure place of confirming each second shift register;
The 3rd shift register, it is with the addition result of first adder, and first integer-bit moves to right;
Second adder, it obtains this filtered sampled value according to the result that the 3rd shift register moves to right.
Further, also comprise
The 4th shift register, its to second sampled value to second integer-bit that moves to left, second sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before in sampled value another;
The 5th shift register, the result that it moves to left the 4th shift register carries out the shifting function of corresponding figure place;
The 3rd adder; Its each through the data addition after the displacement of the 5th shift register; Wherein confirm the number of the 3rd adder and the number of the 5th shift register according to second filter factor; And the displacement figure place of confirming each the 5th shift register, first filter factor and the second filter factor sum are 1;
The 6th shift register, it is with the addition result of the 3rd adder, and second integer-bit moves to right;
Second adder, the results added that result that it moves to right the 3rd shift register and the 6th shift register move to right obtains this filtered sampled value.
Further, also comprise:
The 7th shift register, it arrives current the n time sampled value b-1 time before to non-filtered, and to the 3rd integer-bit that moves to left, the value of b is 2 integral number power, and n is a positive integer, and n is greater than b-1;
The 4th adder, the storing value addition in the output of its 7th shift register and first register;
First register, the output of its storage first adder, and b back zero clearing of first adder addition;
The 8th shift register, it is with the output valve after first adder addition b time, and the b position that moves right obtains first sampled value.
Further, also comprise:
The 9th shift register, it exports the 3rd integer-bit that moves to right with second adder, obtains this filtered sampled value.
Further, first sampled value is the current sampled value of non-filtered.
The embodiment of the invention also provides a kind of electronic equipment, comprises aforesaid single order wave digital lowpass filter on the body.
Owing to convert multiplying to shift operation, can reduce the realization cost.
Description of drawings
Fig. 1 representes single order wave digital lowpass filter circuit theory diagrams of the present invention;
Fig. 2 representes single order wave digital lowpass filter circuit theory diagrams of averaging of the present invention.
Embodiment
Carry out detailed explanation below in conjunction with accompanying drawing and embodiment.
Fig. 1 is the circuit diagram of high accuracy single order lowpass digital filter, and element 104, element 107 are cores of this algorithm, and their function is to realize (1-a) * X (n) and a*Y (n-1) respectively; Be converted into the displacement add operation to multiplying, X (n) can be current the n time sampled value of non-filtered, and the mathematics of its realization is originally: a can be expressed as binary number; For binary number; Its radix is 2, and it has only two numerical chracters, promptly 0 and 1.Calculating rule is " meet two advance one " or " borrow one when two ".For example binary number (101.01) 2: (101.01) 2=1*2
2+ 0*2
1+ 1*2
0+ 0*2
-1+ 1*2
-2, any one binary number N2 can represent with multinomial: N2=d
N-1* 2
N-1+ d
N-2* 2
N-2+ ... + d
1* 2
1+ d
0* 2
0+ d
-1* 2
-1+ d
-2* 2
-2+ ... + d
-m* 2
-mThe equal sign left side is a parallel representation, and equal sign the right is the polynomial repressentation method, and obviously the number represented of these two kinds of representations is of equal value.In the polynomial repressentation method, 1,0,1,0,1 is called as coefficient entry on the right, and 2
2, 2
1, 2
0, 2
-1, 2
-2Deng " power " that is called as this.The size of any one digit number value can be used this coefficient entry d in the formula
iWith weights 2
iLong-pending confirm that wherein, subscript n is represented the figure place of integer part, subscript m is represented the figure place of fractional part, d is a certain number in 0,1, i.e. di ∈ (0,1).
Can be converted into the displacement add operation to multiplying by top derivation, a fixes for each particular instance, so after being converted into the displacement addition; The number of adder is also fixed, because a is in [1,0] interval value; Therefore can amplify 1024 times earlier, promptly X (n) moves to left 10, and the result of last computing moves to right and 10 gets final product; Be 0.4 to be that example describes with (1-a) below, (1-a) amplify 1024 times earlier and equal 409.6 and round and obtain 409 that binary form is shown 110011001.
According to X (n) * N2=X (n) * d
N-1* 2
N-1+ X (n) * d
N-2* 2
N-2+ ... + X (n) * d
1* 2
1+ X (n) * d
0* 2
0+ X (n) * d
-1* 2
-1+ X (n) * d
-2* 2
-2+ ... + X (n) * d
-m* 2
-m
X(n)*（110011001）2=X(n)*1*2
8+X(n)*1*2
7+X(n)*0*2
6+X(n)*0*2
5+X(n)*1*2
4+X(n)*1*2
3+X(n)*0*2
2+X(n)*0*2
1+X(n)*1*2
0
=X(n)<<8+X(n)<<7+X(n)<<4+X(n)<<3+X(n)<<1…
(X wherein
(n)<<8) be exactly X
(n)Move to left 8, (X
(n)<<7) be exactly X
(n)Move to left 7, (X
(n)<<4) be exactly X
(n)Move to left 4, (X
(n)<<3) be exactly X
(n)Move to left 3, (X
(n)<<1) be exactly X
(n)Move to left 1, and the like (X
(n)<<k) be exactly X
(n)The k position that moves to left, k is a positive integer.The result of last computing moves to right after 10, promptly is converted into the displacement add operation to multiplying.
The concrete performing step of element 104 is following:
Step 1,110 couples of X of shift register (n) promptly amplify 1024 times to (1-a) to moving to left 10.
Can confirm the number of adder and the number of shift register according to (1-a).Certainly 110 couples of X of shift register (n) are to 10 the just examples that move to left, and the integer-bit such as 8,11 that move to left all can.
The result that step 2, shift register 113 move to left shift register 110 carries out the shifting function of corresponding figure place.
With (1-a) is 0.4 to be example, and totally 5 shift registers 113 move to left 8,7,4,3,1 respectively.
Step 3, adder 112 are the data addition after being shifted through each shift register 113.
Wherein according to filter factor (1-a) be 0.4 confirm adder 112 number be 4 with the number of shift register 113 be 5, and the displacement figure place of confirming each shift register 113.
Step 4, shift register 111 move to right 10 with the addition result of adder 112.
Through the data addition after being shifted, move to right each 10 to the result of addition again and just accomplished whole displacement add operation.
Afterwards, adder 106 obtains this filtered sampled value according to the result that shift register 111 moves to right.
Similarly method can realize in element 107 that the concrete performing step of element 107 is following:
Step 11,114 couples of Y of shift register (n-1) promptly amplify 1024 times to a to moving to left 10, confirm the number of adder and the number of shift register.
The result that step 12, shift register 115 move to left shift register 114 carries out the shifting function of corresponding figure place.
Step 13, adder 117 are the data addition after being shifted through each shift register 115.
Step 14, shift register 116 move to right 10 with the addition result of adder 117.
In conjunction with before description, the results added that result that adder 106 moves to right shift register 116 and shift register 111 move to right obtains this filtered sampled value.
Like Fig. 2; Certainly measured signal can be delivered to shift register 101 earlier after sampling; The effect of shift register 101 is that a primary signal of sampling is the current sampled value of non-filtered; The d position low level zero padding that moves to left, low d position is exactly the decimal place of expansion, and the purpose of doing like this has two: avoid faint sampled signal to be fallen by the shift operation intercepting of back; Let each sampled signal fractional part all participate in the computing of back, improved processing accuracy.For example, arrive current the n time sampled value b-1 time before 101 pairs of non-filtered of shift register, to moving to left 8, the value of b be 2 integral number power as 4, n is a positive integer, and n is greater than b-1.Adder is the storing value addition in the output of the 7th shift register and first register
Measured signal is after shift register 101 displacement expansions; Through adder 103 just and the value addition of register 102, adder 103 is deposited 102 li in register to the result of addition again, so the value of register 102 is exactly the front result that adds up mutually of signal several times; Register 102 realizes exactly that with 103 two elements of adder b the sampled data in a front adds up; The selection of register 102 bit wides should be to add up for b time not overflow, and the value of b is 2 integral number power, and b back of addition is 102 zero clearings.
The function that shift register 105 is realized is data shift right b position; The data of register 102 are through shift register 105, exactly the result who adds up divided by the b b position that moves right exactly, because the value of b is 2 integral number power; Shift register 105 has just been realized the function of asking average; Average the summation that adds up of b time sampled value as current sampled value X (n), purpose is can PERIODIC INTERFERENCE, and smoothness is high.
The embodiment of the invention also provides a kind of electronic equipment, comprises on the body like aforesaid single order wave digital lowpass filter.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also do some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (11)
1. a single order digital low-pass filtering method is characterized in that, comprising:
First shift register to first sampled value to first integer-bit that moves to left, first sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before one of sampled value;
The result that second shift register moves to left first shift register carries out the shifting function of corresponding figure place;
First adder is wherein confirmed the number of first adder and the number of second shift register according to first filter factor through the data addition after each second shift register displacement, and the displacement figure place of confirming each second shift register;
The 3rd shift register is with the addition result of first adder, and first integer-bit moves to right;
Second adder obtains this filtered sampled value according to the result that the 3rd shift register moves to right.
2. method according to claim 1 is characterized in that, also comprises:
The 4th shift register to second sampled value to second integer-bit that moves to left, second sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before in sampled value another;
The result that the 5th shift register moves to left the 4th shift register carries out the shifting function of corresponding figure place;
Data addition the 3rd adder is shifted each through the 5th shift register after; Wherein confirm the number of the 3rd adder and the number of the 5th shift register according to second filter factor; And the displacement figure place of confirming each the 5th shift register, first filter factor and the second filter factor sum are 1;
The 6th shift register is with the addition result of the 3rd adder, and second integer-bit moves to right;
Second adder obtains this filtered sampled value and is specially according to the result that the 3rd shift register moves to right:
The results added that result that second adder moves to right the 3rd shift register and the 6th shift register move to right obtains this filtered sampled value.
3. method according to claim 2 is characterized in that, also comprises:
The 7th shift register arrives current the n time sampled value b-1 time before to non-filtered, and to the 3rd integer-bit that moves to left, the value of b is 2 integral number power, and n is a positive integer, and n is greater than b-1;
The 4th adder is the storing value addition in the output of the 7th shift register and first register;
The output of the first register-stored first adder, and b the back first register zero clearing of first adder addition;
The 8th shift register is with the output valve after first adder addition b time, and the b position that moves right obtains first sampled value.
4. method according to claim 1 is characterized in that, also comprises:
The 9th shift register is exported the 3rd integer-bit that moves to right with second adder, obtains this filtered sampled value.
5. method according to claim 1 is characterized in that, first sampled value is the current sampled value of non-filtered.
6. a single order wave digital lowpass filter is characterized in that, comprising:
First shift register, its to first sampled value to first integer-bit that moves to left, first sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before one of sampled value;
Second shift register, the result that it moves to left first shift register carries out the shifting function of corresponding figure place;
First adder, the data addition after each second shift register displacement of its process is wherein confirmed the number of first adder and the number of second shift register according to first filter factor, and the displacement figure place of confirming each second shift register;
The 3rd shift register, it is with the addition result of first adder, and first integer-bit moves to right;
Second adder, it obtains this filtered sampled value according to the result that the 3rd shift register moves to right.
7. filter according to claim 6 is characterized in that, also comprises
The 4th shift register, its to second sampled value to second integer-bit that moves to left, second sampled value for the sampled value that obtains according to the current sampled value of non-filtered and filtered before in sampled value another;
The 5th shift register, the result that it moves to left the 4th shift register carries out the shifting function of corresponding figure place;
The 3rd adder; Its each through the data addition after the displacement of the 5th shift register; Wherein confirm the number of the 3rd adder and the number of the 5th shift register according to second filter factor; And the displacement figure place of confirming each the 5th shift register, first filter factor and the second filter factor sum are 1;
The 6th shift register, it is with the addition result of the 3rd adder, and second integer-bit moves to right;
Second adder, the results added that result that it moves to right the 3rd shift register and the 6th shift register move to right obtains this filtered sampled value.
8. filter according to claim 7 is characterized in that, also comprises:
The 7th shift register, it arrives current the n time sampled value b-1 time before to non-filtered, and to the 3rd integer-bit that moves to left, the value of b is 2 integral number power, and n is a positive integer, and n is greater than b-1;
The 4th adder, the storing value addition in the output of its 7th shift register and first register;
First register, the output of its storage first adder, and b back zero clearing of first adder addition;
The 8th shift register, it is with the output valve after first adder addition b time, and the b position that moves right obtains first sampled value.
9. filter according to claim 6 is characterized in that, also comprises:
The 9th shift register, it exports the 3rd integer-bit that moves to right with second adder, obtains this filtered sampled value.
10. filter according to claim 6 is characterized in that, first sampled value is the current sampled value of non-filtered.
11. an electronic equipment is characterized in that, comprises on the body like the described single order wave digital lowpass filter of the arbitrary claim of claim 5 to 10.
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Address after: 611731, room 1, building 3, No. 401, West Avenue, Chengdu hi tech Zone (West District, Sichuan) Patentee after: Chengdu Qi Chen electronic Limited by Share Ltd Address before: 611731 innovation center, No. 4, West core road, hi tech West District, Sichuan, Chengdu C341-343 Patentee before: Chengdu Chip-Rail Microelectronic Co., Ltd. |