CN102708219B - Method for predicting voltage value of full-open defect of interconnecting wire of deep sub-micron integrated circuit - Google Patents

Abstract

The invention discloses a method for predicting a voltage value of a full-open defect of an interconnecting wire of a deep sub-micron integrated circuit. By the method, the voltage at a full-open defect spot of an interconnecting wire can be accurately and efficiently determined in the designing stage of a chip. The method comprises the following steps of: establishing a first voltage prediction model, and establishing a second voltage prediction model based on the first voltage prediction model; extracting coupling capacitance values of peripheral signal wires of a metal wire which is suspected to have an open defect, and calculating a voltage logic by using the second voltage prediction model; and in the automatic test vector generating step of testability design, loading a test vector which is opposite to the calculated voltage logic, and finding the full-open defect on the metal wire if the situation that an open voltage logic is equal to the calculated value obtained by the second voltage prediction model is observed. The method has the advantages that two voltage models which are accurate and feasible in engineering are established, and a complete method for combining the two models is provided.

Description

The method of the full open circuit defect magnitude of voltage of prediction deep submicron integrated circuit interconnection line

Technical field:

The invention belongs to integrated circuit fields, relate to a kind of fault testing method of Design for testability of digital integrated circuits, especially a kind of method of predicting the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line.

Background technology:

Open circuit defect is one of fault common in integrated circuit.In chip design, manufacture and application, all likely introduce open circuit defect, cause the mistake of circuit electrology characteristic.In chip physical Design, flow step and chip application process, cause the main cause of open circuit defect to have:

(1) in layout design, implicit manufacturability design aspect is considered deficiency, for example, do not insert fully multi-through hole.

(2) defect that lithography step is introduced during chip manufacturing.

(3) defect that etch step is introduced during chip manufacturing.

(4) contact hole or through hole have disappearance or imperfect completely during chip manufacturing.

(5) metal wire or the through hole that due to electromigration effect, cause rupture.

The voltage of open circuit defect point is subject to the impact of following factor:

(1) coupling capacitance between other adjacent signals line and open circuit metal wire, and the variation of the logic state of adjacent signals line own.

(2) coupling capacitance between adjacent power lead, ground wire and open circuit metal wire.

(3) the inner gate capacitance of transistor of the gate circuit that disconnection metal wire drives.

(4) electric charge of accumulating on floating empty metal wire in manufacture process.

(5) chip surface resistance, capacitance characteristic.

(6) threshold voltage of institute's driving gate circuit---: Byzantium's effect (Byzantine Effect).

In above all six influence factors, first factor: the impact of the coupling capacitance between adjacent signals line and open circuit metal wire occupies most important, conclusive status.

In technique, be while being greater than or equal to the large-size of 0.13 micron, relative intrinsic capacity, between signal wire coupling capacitance to affect effect very little.Under such condition, although first factor listed above---coupling capacitance can play most important influence, under large-size, the effect that it plays is also very little.So in the time in the past few decades, in Design for testability of digital integrated circuits before process enters deep-submicron, think that the magnitude of voltage at open circuit defect place is to stablize constant high level " 1 " or stablize constant low level " 0 "---this approximate error of bringing is very little, is rational substantially.So such in the situation that, by traditional static defect model: being fixed as 0 model (stuck-at 0) to carry out open defect magnitude of voltage be low level " 0 ", be fixed as 1 model (stuck-at 1), to carry out open defect magnitude of voltage be high level " 1 " and fixing test (N-detection stuck-at) repeatedly, substantially can cover preferably open circuit defect.

But along with technique enters the size of deep-submicron and sub-micro, copper has substituted aluminium and has made metal interconnecting wires; And interconnection line width, spacing reduce; Density increases, the number of plies increases and the surge of number of openings, and these factors have all further increased the probability that open circuit defect occurs.And the more important thing is, now between signal wire, the relative intrinsic capacity of the impact of coupling capacitance no longer can be ignored.Therefore when those and open circuit defect are put adjacent signal wire logic and changed, because causing the voltage at open circuit defect place, capacitance coupling effect also there is corresponding change.Because the voltage of open circuit defect point is no longer fixed value, if continue, continue to use above traditional static defect model: be fixed as 0 model (stuck-at 0), be fixed as 1 model (stuck-at 1) and the words of fixing test (N-detection stuck-at) repeatedly, the full open circuit defect that can find a greater number in the chip testing stage no longer can be detected by existing test vector, and chip testing coverage rate will no longer can meet the demands.And really, in 90 nanometers, 65 nanometers, 45 nanometers, 40 nanometers and the 23 nanometer projects of reality, having been found that increasing real open fault is missed, chip electric property makes a mistake and but cannot be detected by existing test vector.Chip testing slip-stick artist have to cannot be measured by these, containing defective chip be sent to can test design (DFT) slip-stick artist act as a guest number of households involved product return (Customer Retain) analysis, greatly wasted the test duration.Even and if entered after client's substandard products return to the flow process of analysis, not having reliably, for the voltage prediction formula of open circuit defect, also can not have effectively these defects are diagnosed, determined and location, still has no idea to reach high test coverage.

So when technique enters the deep-submicron that is less than after 0.13 micron and less sub-micro scope, we are badly in need of finding method accurately and efficiently to determine the magnitude of voltage of interconnection line standard-sized sheet road defect point.

Summary of the invention:

The object of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of method of predicting the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line is provided, the method can be determined the magnitude of voltage of interconnection line standard-sized sheet road defect point accurately and efficiently, comprises the following steps:

(1) set up first voltage-prediction model:

$V_{\mathrm{floating}}=\underset{i=0}{\overset{8}{\mathrm{\Σ}}}{V}_i+V_{\mathrm{trap}}=\left[\underset{i=0}{\overset{8}{\mathrm{\Σ}}}(V_i^1-V_i^0)\right]+V_{\mathrm{trap}}$

$=\left\{\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}\right[K_i*{\left(C_{1\_f}\right)}_i-K_i*{\left({\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="HDA00001887061600071.png,HDA00001887061600081.png"\; state="\{\{state\}\}">C</figure-callout>}}_{0\_f}\right)}_i\left]\right\}+V_{\mathrm{trap}}---\left(1\right)$

V in formula (1) _floatingfor the magnitude of voltage of open circuit defect point, take millivolt as unit; V _ithe voltage change inducing in open circuit point for single adjacent signals line;

be expressed as the voltage change that a certain adjacent signals line induced in open circuit point to high level saltus step by low level;

be expressed as the voltage change that another root adjacent signals line of synchronization is induced in open circuit point to low transition by high level; V _traprepresent the impact of stored charge effect on voltage on floating empty metal wire; C _{1_f}coupling capacitance between the signal wire that expression open circuit metal and this moment logical value saltus step are high level; C _{0_f}represent that open circuit metal and this moment logical value saltus step are the coupling capacitance between low level signal wire; Label in formula " i " characterizes the label with the tight adjacent ambient signals line of open circuit defect, and " i " do not comprise the signal wire itself that open circuit defect occurs; K _ilinearization coefficient for the different adjacent situation coupling capacitances of correspondence.

(2) set up second voltage-prediction model:

$C_i^1=C_{\mathrm{Vdd}\_f}+\mathrm{\&Sigma;}{C}_{1\_f}---\left(3\right)$

$C_i^0=C_{\mathrm{Vss}\_f}+\mathrm{\&Sigma;}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="HDA00001887061600071.png,HDA00001887061600081.png"\; state="\{\{state\}\}">C</figure-callout>}}_{0\_f}---\left(4\right)$

$C_{\mathrm{total}}=C_i^1+C_i^0---\left(5\right)$

V in formula (2) _floatingvoltage logical value for open circuit defect point: 0 and 1 represents respectively low-voltage and high voltage; In formula (2)～(5), the intermetallic coupling capacitance of adjacent power lead, ground wire and open circuit is also counted to calculating: capacitor C _{vdd_f}represent the coupling capacitance between open circuit metal and neighboring power wires Vdd; C _{vss_f}represent the coupling capacitance between open circuit metal and adjacent ground wire Vss; C _{1_f}coupling capacitance between the signal wire that expression open circuit metal and this moment logical value saltus step are high level; C _{0_f}represent that open circuit metal and this moment logical value saltus step are the coupling capacitance between low level signal wire;

that voltage logic is the coupling capacitance sum of the line of high level;

that voltage logic is the coupling capacitance sum of low level line; C _totalit is total coupling capacitance;

the high level number percent thresholding for definition, with

for example: be high level higher than 75% times of supply voltage;

for the low level number percent thresholding of definition, with

for example: be low level lower than (1-75%) supply voltage doubly.

(3) extract the doubtful coupling capacitance that has the metal wire ambient signals line of open circuit defect to be measured, utilize second voltage-prediction model to calculate voltage logic; Automatic test vector in design for Measurability generates in step, load test vector, the voltage logic that the doubtful input terminal voltage logical and that has a metal wire of open circuit defect is calculated is contrary, if the open-circuit voltage logic observing equals the calculated value of formula (2) really, explanation has full open circuit defect herein.

Described step (1) is set up first voltage-prediction model, comprising:

Steps A: the capacitor model of setting up full open circuit defect;

Step B: design test module, in module, insert the full open circuit defect of interconnection line, around this open circuit point be built with adjacent signals line closely around domain situation;

Step C:

First, for a specific open-circuit position, extract the coupling capacitance of adjacent signals line with it.And change the logic state of these adjacent signals lines, for the different situations of adjacent signals line logic state saltus step, by the emulation of SPICE device level, obtain the magnitude of voltage of corresponding this open circuit defect point.Simulate: at a time, while only having single adjacent signals line logical changes, the voltage change V inducing in open circuit point _i.

Next, change open-circuit position, change itself and the size of adjacent signals line coupling capacitance around, again by the emulation of SPICE device level, obtain the magnitude of voltage on the open circuit defect of corresponding diverse location.

Then, utilize MATLAB matched curve, analyze in different open-circuit positions the relation of adjacent signals line coupling capacitance and open circuit point voltage.

Finally, again utilize MATLAB, the relation curve of coupling capacitance and voltage is got to first approximation, and calculate linear coupling coefficient (that is: the K in formula (1) _i), obtain the analytical expression of first complete voltage-prediction model.

In described step (2), when the adjacent signals coupling capacitance of low saltus step and the ratio of total coupling capacitance surpass low level number percent thresholding, open circuit point is low-level logic; When the adjacent signals coupling capacitance of high saltus step and the ratio of total coupling capacitance surpass high level number percent thresholding, open circuit point is high level logic.

Model is the basis of all working of the full open circuit defect of testing integrated circuits interconnection line accurately.After only having possessed accurate feasible magnitude of voltage model, could be based on this model, for the specific doubtful candidate point that has the full open circuit defect of interconnection line in integrated circuit, carry out the generation (Test-Pattern-Generation) of test vector, or the generation (Automatic-Test-Pattern-Generation) of test vector automatically, whether then in the chip testing stage, with the candidate point that these special-purpose test vectors may be opened a way to those, diagnose quickly and accurately, testing out is real fault.Like this, reduce the test duration, improved test coverage.

That is to say, the voltage-prediction model that the present invention proposes is the cornerstone in the whole testing process of the full open circuit defect of deep submicron integrated circuit interconnection line.

The invention has the beneficial effects as follows: two voltage model formula setting up accurately and have feasibility meaning in engineering; And the complete method that two models couplings are used is proposed.Make us for the chip of deep-submicron and sub-micro technique, in its design phase, just can predict interconnection line standard-sized sheet road defect point magnitude of voltage.

Accompanying drawing explanation:

Fig. 1 is the capacitor model figure of full open circuit defect of the present invention;

Fig. 2 is the logi function chart of test module of the present invention;

Fig. 3 is the domain sectional view of standard-sized sheet of the present invention road signal wire and 8 adjacent lines;

Fig. 4 is the paramount level diagram of the single saltus step of adjacent signals line of the present invention;

Fig. 5 is the voltage influence figure of the high saltus step open-circuit of single signal wire of the present invention metal;

Fig. 6 is the paramount level diagram of adjacent signals line stack saltus step of the present invention;

Fig. 7 is the superpose voltage influence figure of high saltus step open-circuit metal of adjacent signals line of the present invention;

Fig. 8 is the comparison diagram that is related to of different its change in voltage of adjacent situation of the present invention and coupling capacitance;

Fig. 9 is of the present invention adjacent with layer: the relation of change in voltage and coupling capacitance---approximately linear figure;

Figure 10 be different layers of the present invention over against adjacent: the relation of change in voltage and coupling capacitance---linear graph;

Figure 11 is that different layers of the present invention is non-over against adjacent: relation---the linear graph of change in voltage and border coupling capacitance.

Embodiment:

Below in conjunction with accompanying drawing, the present invention is described in further detail:

Referring to Fig. 1-11, due under deep-submicron, sub-micro process conditions, in integrated circuit diagram (Layout), between other signal wire adjacent with open circuit defect point physical location and open circuit metal wire, exist larger coupling capacitance.Under the impact of coupling capacitance, when the logic state of other adjacent signals line changes, also there is corresponding variation in the voltage at open circuit defect place.The voltage-prediction method proposing in the present invention is exactly the relation of setting up between open circuit point voltage and coupling capacitance, characterizes magnitude of voltage and the voltage logic of circuit defect point by the coupling capacitance of adjacent signals line.

The present invention carries out transistor level circuit simulation, analysis, has finally proposed the method for the full open circuit defect magnitude of voltage of prediction deep submicron integrated circuit interconnection line based on Taiwan Semiconductor Manufacturing Co. (TSMC) 40 nanometer digital CMOS process.The open-circuit voltage Forecasting Methodology proposing comprises two voltage-prediction model formula.The principle of these two voltage-prediction model formula is consistent: be all the impact of considering emphatically capacitance coupling effect open-circuit voltage, by coupling capacitance, characterize voltage.In the design phase of integrated circuit, for the specific doubtful open circuit defect candidate point (Open Candidate) that has open circuit defect (open circuit defect possibility occurring high), DFT slip-stick artist can extract by eda tool the size of the signal wire coupling capacitance that obtains being adjacent, that is to say that coupling capacitance is the information that just can obtain in the integrated circuit (IC) design stage, can be considered as is known quantity, and the voltage of open circuit point is the unknown quantity of wanting to ask, two voltage prediction formula that the present invention proposes are all to characterize unknown open-circuit voltage values by this known quantity of coupling capacitance.

First model formula has high precision, has not only considered the capacitance coupling effect that plays a decisive role, and has comprised electric charge accumulation effect ((4) the individual influence factor that affects open circuit point voltage of mentioning in background of invention) above.Second model is the voltage prediction formula of simplifying on the basis of first model, has stronger engineering significance, can in DFT design, use by the fault model (Fault Model) as test vector generating algorithm.Describe respectively the particular content of these two models below in detail; And they are combined with, thereby effective engineering method of definite interconnection line standard-sized sheet road defect point magnitude of voltage or voltage logic.

In conceptual phase of the present invention, through three steps, obtained first voltage-prediction model.

First step: the capacitor model of setting up full open circuit defect.The present invention will characterize with coupling capacitance the magnitude of voltage of open circuit point, so electric capacity is the emphasis of research.First we set up capacitor model accurately for full open circuit defect.Fig. 1 is the capacitor model figure of full open circuit defect, in the 14th page, this instructions, Fig. 1 is carried out to specific explanations.

Second step: design test module, in module, insert the full open circuit defect of interconnection line, around this open circuit point be built with adjacent signals line closely around domain situation.Fig. 2 is the logi function chart of test module; Fig. 3 is the domain sectional view of test module.The explanation of logi function chart and domain sectional view is in the 14th page, this instructions.This domain situation accurately and has all sidedly been simulated the situation that affects of adjacent signals line open-circuit defect in the actual domain of integrated circuit.

Third step:

First, for a specific open-circuit position, extract the coupling capacitance (table 1) of adjacent signals line with it, change the logic state of these adjacent signals lines, by the emulation of SPICE device level, obtain the magnitude of voltage (Fig. 4 to Fig. 7) of this position open circuit defect point.

Next, change open-circuit position, change the size of coupling capacitance, again by the emulation of SPICE device level, obtain the magnitude of voltage of diverse location open circuit defect point.

Then, utilize MATLAB matched curve, analyze in different open-circuit positions the relation (Fig. 8 to Figure 11) of adjacent signals line coupling capacitance and open circuit point voltage.

Finally, again utilize MATLAB, the relation curve of coupling capacitance and voltage is got to first approximation, and calculate linear coupling coefficient (that is: the K in formula (1) _i), obtain the analytical expression of first complete voltage-prediction model.

The content of first voltage-prediction model is:

(1) change of the capacitance coupling effect between adjacent signals line and open circuit metal wire and adjacent signals line logic can cause the respective change of open circuit defect place voltage.

(2) relation that many adjacent signals line capacitance coupling effects are linear superposition for the impact of open circuit defect place voltage.

(3) between the relative variation and the size of coupling capacitance of the open circuit defect place voltage causing due to capacitance coupling effect: be linear approximate relationship.

The analytical expression of first voltage-prediction model is:

$V_{\mathrm{floating}}=\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}{V}_i+V_{\mathrm{trap}}=\left[\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}(V_i^1-V_i^0)\right]+V_{\mathrm{trap}}$

$=\left\{\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}\right[K_i*{\left(C_{1\_f}\right)}_i-K_i*{\left({\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="HDA00001887061600071.png,HDA00001887061600081.png"\; state="\{\{state\}\}">C</figure-callout>}}_{0\_f}\right)}_i\left]\right\}+V_{\mathrm{trap}}---\left(1\right)$

Explanation to first voltage prediction formula: V _floatingfor the magnitude of voltage of open circuit defect point, take millivolt as unit.V _ithe voltage change inducing in open circuit point for single adjacent signals line.Specifically:

be expressed as the voltage change that a certain adjacent signals line induced in open circuit point to high level saltus step by low level;

be expressed as the voltage change that another root adjacent signals line of synchronization is induced in open circuit point to low transition by high level.V _trapon the floating empty metal wire of expression, the impact of the effect of stored charge on voltage, simulates and characterizes the magnitude of voltage inducing in open circuit point due to charge accumulation effects with the magnitude of voltage of quiescent point in the present invention.In the process that the automatic test vector of design for Measurability generates, the input voltage of open circuit signaling line own keeps fixing, therefore for test module of the present invention: i ≠ 4 (as Fig. 2, open circuit defect design is on the signal wire of " 4 " at label).

In first voltage prediction formula, K _ifor the linearization coefficient of the different adjacent situation coupling capacitances of correspondence, the voltage that Fig. 8 obtains by MATLAB the Fitting Calculation and the linearizing slope of electric capacity, have 3 different K _i, be respectively:

(1) 186.51---with the metal wire of open circuit metal wire at same wiring layer, the slope of coupling effect (corresponding electric capacity is that fF, voltage are mV).

(2) 128.44---and open circuit metal wire is at same wiring layer, but layer next-door neighbour upper and lower with it over against metal wire, the slope of coupling effect (corresponding electric capacity is that fF, voltage are mV).

(3) 90.04---and open circuit metal wire is at same wiring layer, thereon, lower floor, but position is non-over against adjacent metal wire, the slope of border coupling effect (corresponding electric capacity is that fF, voltage are mV).

C in first voltage prediction formula _{1_f}and C _{0_f}implication in the 14th page, this instructions, the declaratives of the capacitor model of the full open circuit defect of Fig. 1 are made an explanation.For different technique, linearization COEFFICIENT K _ivalue different.Therefore for different technique, repeat the present invention and obtain second step and the third step that first voltage prediction formula experiences, recalculate linearization COEFFICIENT K accurately _i, obtain complete model formation.

Second voltage-prediction model continues to simplify on the basis of first model, and the impact of suppose to float stored charge on empty metal wire and chip surface effect is all little of ignoring, and only has the coupling capacitance between adjacent lines to play unique conclusive influence.Second voltage-prediction model only be take measurable coupling capacitance as independent variable, by coupling capacitance, characterizes voltage.

The content of second voltage-prediction model is: when the adjacent signals coupling capacitance of low saltus step and the ratio of total coupling capacitance surpass low level number percent thresholding, open circuit point is low-level logic.When the adjacent signals coupling capacitance of high saltus step and the ratio of total coupling capacitance surpass high level number percent thresholding, open circuit point is high level logic.

The analytical expression of second voltage-prediction model is:

$C_i^1=C_{\mathrm{Vdd}\_f}+\mathrm{\&Sigma;}{C}_{1\_f}---\left(3\right)$

${\mathrm{<figure-callout\; id="0"\; label="C\; i"\; filenames="HDA00001887061600071.png,HDA00001887061600081.png"\; state="\{\{state\}\}">C</figure-callout>}}_i^{}=C_{\mathrm{Vss}\_f}+\mathrm{\&Sigma;}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="HDA00001887061600071.png,HDA00001887061600081.png"\; state="\{\{state\}\}">C</figure-callout>}}_{0\_f}---\left(4\right)$

$C_{\mathrm{total}}=C_i^1+C_i^0---\left(5\right)$

Explanation to second voltage prediction formula: V in formula (2) _floatingfor the voltage logical value of open circuit defect point, 0 and 1 represents respectively low-voltage and high voltage.In formula (2)～(5), the intermetallic coupling capacitance of adjacent power lead, ground wire and open circuit is also counted to calculating, C _{vdd_f}and C _{vss_f}consistent with the implication characterizing in Fig. 1.

the high level number percent thresholding for definition, with

for example: higher than the high level that is of 75% times of supply voltage.Similarly,

for the low level number percent thresholding of definition, with

for example: be low level lower than (1-75%) supply voltage doubly.

In order to guarantee that simplified model (formula (2)) has equal logic corresponding with high precision model (formula (1)), before use formula (2) carries out voltage calculating, first to determine reasonably

with

whether high level, low level number percent thresholding definition value are rationally to be judged by first voltage-prediction model.

In conceptual phase of the present invention, through four steps, obtained second voltage-prediction model.Concrete steps are:

First step: according to the requirement to high and low level in product design, then the scope of elementary cell threshold voltage in the special process storehouse adopting in conjunction with this chip design, first define initial high and low level number percent threshold value.

Second step: calculated the magnitude of voltage of open circuit point by first voltage-prediction model, this magnitude of voltage be take millivolt as unit; The concrete magnitude of voltage that the millivolt of again this being take is unit becomes voltage logical value by high level, the conversion of low level number percent thresholding of original definition.

Third step: by second voltage-prediction model of high and low level number percent thresholding substitution of original definition, then utilization second voltage-prediction model now calculates the logical value of open circuit point voltage.

The 4th step: if the voltage logical value that two models obtain is consistent, explanation now the original definition value of the high and low level number percent thresholding in second voltage-prediction model be rational; If the voltage logical value that two models obtain is inconsistent, need to adjust the definition value of high and low level number percent thresholding, and then by the value after adjusting, repeat step 2 and the step 3 of this process, until final second voltage-prediction model adopted rational high and low level number percent thresholding definition value, the voltage logical value at the open circuit defect place calculating equates with first voltage-prediction model, obtains the analytical expression of second voltage-prediction model.

The test module of corresponding Taiwan Semiconductor Manufacturing Co. (TSMC) 40 nanometer digital CMOS process, after repeatedly analyzing relatively, definition

this is to be the most reasonably worth.

The situation of the adjacent lines coupling capacitance based on table 1, carries out different assignment (listing the high saltus step situation of input) for 9 parallel lines input signals, directly utilizes first voltage-prediction model (formula (1)) to calculate absolute voltage value, utilizes

with

absolute value of voltage is interpreted as to low and high level logic.Recycle second voltage-prediction model (formula (2)) and calculate low and high level logic, both are contrasted, list in table 2.Now, because the impact of hypothesis coupling capacitance accounts for unique leading effect, therefore ignore the effect of stored charge on floating empty metal wire completely, in formula (1), make V _trapequal 0.From the results shown in Table 2: this high and low level threshold voltage

very reasonably to arrange.Carry out with this understanding open circuit defect point voltage and calculate, consistent with the result that high precision model obtains with simplified model.

The engineering significance of open circuit defect voltage-prediction model is: in chip design stage, when suspecting that certain wires is standard-sized sheet road, can extract the coupling capacitance of its ambient signals line, utilize second voltage-prediction model to calculate voltage logic.Automatic test vector in design for Measurability generates in step, the voltage logic that the input vector logical and of order open circuit metal calculates is contrary, if the open-circuit voltage logic observing still really for formula (2), calculated value, explanation has full open circuit defect herein.

To being described as follows of the capacitor model figure of the full open circuit defect of Fig. 1.In Fig. 1: capacitor C _{vdd_f}represent the coupling capacitance between open circuit metal and neighboring power wires Vdd; C _{vss_f}represent the coupling capacitance between itself and adjacent ground wire Vss; C _{1_f}represent the coupling capacitance between signal wire that itself and this moment logical value saltus step is high level; C _{0_f}represent that open circuit metal and this moment logical value saltus step are the coupling capacitance between low level signal wire.In Fig. 1, on the right of dotted line, cut apart and illustrate that open circuit metal wire drives the inside gate capacitance equivalent electrical circuit of single load door circuit.C _{gb (p)}the electric capacity between P pipe grid and substrate; C _{gs (p)}the electric capacity of P pipe grid and source; C _{gd (p)}the electric capacity of P pipe grid and drain terminal; C _{gb (n)}the electric capacity of N pipe grid and P trap; C _{gs (n)}the electric capacity of N pipe grid and source; C _{gd (n)}the electric capacity of N pipe grid and drain terminal.

To being described as follows of Fig. 2 test module logi function chart and Fig. 3 domain sectional view.In Fig. 1, test module contains 9 input ends, 9 output terminals, and each input and output side is corresponding.Between one group of input and output, there is two-stage buffer cascade.In Fig. 2, layout design is done the specially parallel coiling of form by the line (NET0 to NET8) between two-stage impact damper, and the cross-section structure of parallel lines domain is illustrated in Fig. 2.9 parallel lines are the signal wire of minimum feature, and parallel length total length is 18 microns.NET7, NET4 and NET8 are at same layer (a three-layer metal layer M3), and the spacing between them is all the minimum spacing of design rule scope.Other 6 lines with coordinate overlay these three signal wires above and below, M3 metal level is two-layer up and down: M2 and M4.The faultiness design on standard-sized sheet road, in stacking on the signal wire NET4 at center, cuts off NET4, and the distance between centers of tracks of fracture meets the requirement of the minimum spacing of DRC.L_floating represents the length of floating empty metal.Under the prerequisite that between online, parallel length is constant, change the position of standard-sized sheet waypoint, L_floating length changes, coupling capacitance respective change, and the voltage of open circuit point also changes.Table 1 has represented the coupling capacitance (corresponding open-circuit position is that L_floating equals 14.64 microns) between open circuit metal wire and adjacent lines.

Table 1

Fig. 4 to Fig. 7 carries out the excitation waveform of SPICE emulation and the simulation result waveform of open circuit point voltage to test module.Wherein, the situation of Fig. 4 and Fig. 5 emulation is: analyze the variation of the upper voltage of caused NET4 when only having one to close on line states variation.The form that Fig. 4 superposes with waveform is described 8 closing signal lines and sequentially from low level (0V), is jumped to high level (1.2V) singlely, keeps 1 microsecond, returns again low level.Fig. 5 is the relative variation of floating in this case voltage on empty metal.And in Fig. 5, marking out relative variation, voltage starting point is quiescent operation voltage (559.730 millivolts).

Comparison diagram 5 can be found out with table 1: the voltage difference inducing presents corresponding consistent proportionate relationship with the size of coupling capacitance.NET7, NET8 and NET4 are closely adjacent with layer, and coupling capacitance is maximum, and the voltage jump amount inducing is maximum.NET5 and NET3 be the upper and lower layer in open circuit metal NET4 respectively, though different layers upper and lower over against front coupling, the size of coupling capacitance is taken second place, the voltage difference inducing is larger.Another 4 line: NET1, NET2, NET6, NET0 and NET4 are in different layers, and non-capacitance under ， edge, the position coupling effect of coupling is minimum with it, and the change in voltage inducing is also minimum.

When in circuit, adjacent signals line has many to change to high level, can by initial voltage, be that low level NET4 is induced to high level.Fig. 6 and Fig. 7 make a concrete analysis of the superposition (effect of low level voltage coupling stack is similar) of this high level coupling.Fig. 6 represents that 8 adjacent signals lines sequentially jump to high level (1.2V) from low level (0V), and keeps always, and final all adjacent signals lines are all in high level state.In Fig. 7, open circuit metal NET4 still be take 559.730 millivolts as voltage initial value, and the forward voltage saltus step inducing on it is cumulative gradually, finally reaches 1.315 volts.Analysis chart 7 simulation results it can also be seen that: the variation step value of every step voltage equals the voltage jump value that in Fig. 5 situation, single coupling causes just---it is linear superposition relation that voltage that the floating dead end of open circuit produces due to coupling capacitance and adjacent signals line voltage jump changes.

Fig. 8 to Figure 11 is by MATLAB matched curve: the size of the change of voltage and coupling capacitance is directly shone upon.The relation curve of the variation of open circuit point voltage and coupling capacitance is made to first-order linear in first voltage-prediction model approximate, obtained the relative changes of voltage and the approximately linear slope of a curve of coupling capacitance size.Corresponding diagram 9: being positioned at adjacent metal with layer, to cause the slope of change in voltage and coupling capacitance relation curve be 186.51.Corresponding Figure 10: different layers but to cause the slope of change in voltage and coupling capacitance relation curve over against position adjacent metal be 128.44.Corresponding Figure 11: belonging to different layers and non-adjacent metal over against location boundary coupling, to cause the slope of change in voltage and coupling capacitance relation curve be 90.04.The influence power of slope reflection coupling effect: the change in voltage of the larger inductive coupling of slope value is larger.It is unit that above 3 slope value corresponding voltage be take millivolt (mV), and it is unit that coupling capacitance be take pico farad (fF).

Table 2 provide result of the present invention: by selecting rational high and low level threshold voltage, utilize open-circuit voltage predictor formula (i.e. second voltage-prediction model) the open-circuit defect point voltage of simplifying to calculate, obtain first voltage-prediction model consistent result high with precision.

Table 2 formula (1) and formula (2) are for the logical value contrast table of open circuit point voltage

Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; for general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by submitted to claims.

Claims (5)

1. predict the method for the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line, it is characterized in that:

(1) set up first voltage-prediction model:

$\begin{array}{c}{V}_{\mathrm{floating}}=\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}{V}_i+V_{\mathrm{trap}}=\left[\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}({V_i}^1-{V_i}^0)\right]+V_{\mathrm{trap}}\\ =\left\{\underset{i=0}{\overset{8}{\mathrm{\&Sigma;}}}\right[K_i*{\left(C_{1\_f}\right)}_i-K_i*{\left(C_{0\_f}\right)}_i\left]\right\}+V_{\mathrm{trap}}\end{array}---\left(1\right)$

V in formula (1) _floatingfor the magnitude of voltage of open circuit defect point, take millivolt as unit; V _ithe voltage change inducing in open circuit point for single adjacent signals line; V _i ¹be expressed as the voltage change that a certain adjacent signals line induced in open circuit point to high level saltus step by low level; V _i ⁰be expressed as the voltage change that another root adjacent signals line of synchronization is induced in open circuit point to low transition by high level; V _traprepresent the impact of stored charge effect on voltage on floating empty metal wire; C _{1_f}coupling capacitance between the signal wire that expression open circuit metal and this moment logical value saltus step are high level; C _{0_f}represent that open circuit metal and this moment logical value saltus step are the coupling capacitance between low level signal wire; Label in formula " i " characterizes the label with the tight adjacent ambient signals line of open circuit defect, and " i " do not comprise the signal wire itself that open circuit defect occurs; K _ilinearization coefficient for the different adjacent situation coupling capacitances of correspondence;

(2) set up second voltage-prediction model:

${C_i}^1=C_{\mathrm{Vdd}\_f}+\mathrm{\&Sigma;}{C}_{1\_f}---\left(3\right)$

${C_i}^0=C_{\mathrm{Vss}\_f}+{\mathrm{\&Sigma;C}}_{0\_f}---\left(4\right)$

$C_{\mathrm{total}}={C_i}^1+{C_i}^0---\left(5\right)$

V in formula (2) _floatingvoltage logical value for open circuit defect point: 0 and 1 represents respectively low-voltage and high voltage; In formula (2)～(5), the intermetallic coupling capacitance of adjacent power lead, ground wire and open circuit is also counted to calculating: capacitor C _{vdd_f}represent the coupling capacitance between open circuit metal and neighboring power wires Vdd; C _{vss_f}represent the coupling capacitance between open circuit metal and adjacent ground wire Vss; C _{1_f}coupling capacitance between the signal wire that expression open circuit metal and this moment logical value saltus step are high level; C _{0_f}represent that open circuit metal and this moment logical value saltus step are the coupling capacitance between low level signal wire; C _i ¹that voltage logic is the coupling capacitance sum of the line of high level; C _i ⁰that voltage logic is the coupling capacitance sum of low level line; C _totalit is total coupling capacitance;

it is the high level number percent thresholding of definition;

low level number percent thresholding for definition;

(3) extract the doubtful coupling capacitance that has the metal wire ambient signals line of open circuit defect to be measured, utilize second voltage-prediction model to calculate voltage logic; Automatic test vector in design for Measurability generates in step, load test vector, the voltage logic that the doubtful input terminal voltage logical and that has a metal wire of open circuit defect is calculated is contrary, if the open-circuit voltage logic observing equals the calculated value of formula (2) really, explanation has full open circuit defect herein.

2. predict as claimed in claim 1 the method for the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line, it is characterized in that:

Described step (1) is set up first voltage-prediction model, comprising:

A: the capacitor model of setting up full open circuit defect;

B: the special process storehouse adopting for the chip design of deep-submicron and sub-micro technique, design test module; In test module, insert the full open circuit defect of interconnection line, around this open circuit defect be built with adjacent signals line closely around domain situation;

C: first, for a specific open-circuit position, extract the coupling capacitance of adjacent signals line with it; And change the logic state of these adjacent signals lines, for the different situations of adjacent signals line logic state saltus step, by the emulation of SPICE device level, obtain the magnitude of voltage of corresponding this open circuit defect point; Simulate: at a time, while only having single adjacent signals line logical changes, the voltage change V inducing in open circuit point _i;

Next, change open-circuit position, change itself and the size of adjacent signals line coupling capacitance around, again by the emulation of SPICE device level, obtain the magnitude of voltage on the open circuit defect of corresponding diverse location;

Then, utilize MATLAB matched curve, analyze in different open-circuit positions the relation of adjacent signals line coupling capacitance and open circuit point voltage;

Finally, again utilize MATLAB, the relation curve of coupling capacitance and voltage is got to first approximation, and calculate linear coupling coefficient, that is: the K in formula (1) _i, obtain the analytical expression of first complete voltage-prediction model.

3. predict as claimed in claim 2 the method for the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line, it is characterized in that:

Described step (1) is set up first voltage-prediction model: the technology library that chip design adopts changes, linear coupling COEFFICIENT K _ialso change; Therefore,, for different technique, answer B and two processes of C in repeating step (1), to obtain first voltage-prediction model corresponding with technique;

C in described step (1): by MATLAB matching, the open circuit point voltage occurrence that the emulation of SPICE device level is obtained has been mapped in coupling capacitance;

And A in described step (1): complete set up the capacitor model of open circuit defect---this capacitor model is complete, and with technique change, does not change; In capacitor model, comprised the immeasurablel variable V of chip design stage _trap, comprised the impact of stored charge effect on voltage on floating empty metal wire.

4. predict as claimed in claim 1 the method for the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line, it is characterized in that:

Described step (2) is set up second voltage-prediction model: define rational high level number percent thresholding

, and low level number percent thresholding

, obtain the analytical expression of second complete voltage-prediction model;

Whether high level, low level number percent thresholding definition value are rationally to be judged by first voltage-prediction model; Concrete steps are:

A: according to the requirement to high and low level in product design, then the scope of elementary cell threshold voltage in the special process storehouse adopting in conjunction with the chip design of deep-submicron and sub-micro technique, first define initial high and low level number percent threshold value;

B: calculated the magnitude of voltage of open circuit point by first voltage-prediction model, this magnitude of voltage be take millivolt as unit; The concrete magnitude of voltage that the millivolt of again this being take is unit becomes voltage logical value by high level, the conversion of low level number percent thresholding of original definition;

C: by second voltage-prediction model of high and low level number percent thresholding substitution of original definition, then utilization second voltage-prediction model now calculates the logical value of open circuit point voltage;

D: if the voltage logical value that two models obtain is consistent, explanation now the original definition value of the high and low level number percent thresholding in second voltage-prediction model be rational; If the voltage logical value that two models obtain is inconsistent, need to adjust the definition value of high and low level number percent thresholding, and then by the value after adjusting, repeat step B and the step C of this process, until final second voltage-prediction model adopted rational high and low level number percent thresholding definition value, the voltage logical value at the open circuit defect place calculating equates with first voltage-prediction model; Obtain the analytical expression of second voltage-prediction model.

5. predict as claimed in claim 1 the method for the full open circuit defect magnitude of voltage of deep submicron integrated circuit interconnection line, it is characterized in that:

In described step (2), second voltage model simplified on the basis of first voltage model: ignore the immeasurablel variable V of chip design stage _trap, ignore the impact of stored charge effect on voltage on floating empty metal wire; And using the coupling capacitance that can measure in chip design step as unique variable, characterize the voltage logic state of open circuit point; When the adjacent signals coupling capacitance of low saltus step and the ratio of total coupling capacitance surpass low level number percent thresholding, open circuit point is low-level logic; When the adjacent signals coupling capacitance of high saltus step and the ratio of total coupling capacitance surpass high level number percent thresholding, open circuit point is high level logic;

Simultaneously, by arranging and verifying, obtain rational high and low level number percent threshold value, the analytical expression of second voltage model of substitution, makes: second voltage model formula is consistent for the judgement of open circuit point logic state with first voltage model formula---guaranteed that second voltage model has and the akin accuracy of first voltage-prediction model;

Therefore, in step (3): in the automatic test vector step of chip design for Measurability, directly use second voltage model formula as the fault model of the full open circuit defect of interconnection line.

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