CN105629154B - A kind of method and device for realizing chip top-layer metal covering circuit test - Google Patents
A kind of method and device for realizing chip top-layer metal covering circuit test Download PDFInfo
- Publication number
- CN105629154B CN105629154B CN201510994235.1A CN201510994235A CN105629154B CN 105629154 B CN105629154 B CN 105629154B CN 201510994235 A CN201510994235 A CN 201510994235A CN 105629154 B CN105629154 B CN 105629154B
- Authority
- CN
- China
- Prior art keywords
- metal wire
- input data
- data
- circuit
- level metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of method and devices for realizing the test of chip top-layer metal covering, comprising: to all metal wires of top-level metallic covering circuit, gradually selected section metal wire in batches carries out the signal overturning of input data；When each batch metal wire completes the signal overturning of input data, input data and output data to all metal wires are compared analysis；Summarized according to the comparative analysis result of the input data of all batches and output data, determines whether the function of chip top-layer metal covering circuit is normal according to summarized results.The method of the present invention is overturn by the signal that gradually selected section metal wire carries out input data in batches, analysis is compared to the input data and output data of the overturning of all batch signals, it is realized by logic integrity circuit and whether circuit function, which normally judges, is covered to top-level metallic, top-level metallic covering circuit test cost is reduced, the working efficiency of top-level metallic covering circuit test is improved.
Description
Technical field
The present invention relates to Circuit Measurement Technology, espespecially a kind of method and dress for realizing chip top-layer metal covering circuit test
It sets.
Background technique
Chip top-layer metal covering is one of the design method of high safety intelligent card chip.By covering one in chip top-layer
Layer metal medium, can not be carried out malicious external attack with effective protection chip bottom circuit and signal.Due to producing and processing
Journey may cause the disabler of the top-level metallic covering of segment chip, and the safety of critical data in chip is caused to be unable to get guarantor
Card.Therefore it needs to reject the chip that top-level metallic covering function fails.
Top-level metallic covering is generally tested by logic integrity circuit: the design principle of logic integrity circuit
It is: logic gates is increased separately at the metal wire both ends of top layer covering, by increased logic gates test data from gold
Belong to whether line input terminal is correctly transmitted to output end, if the data of all metal wires are by normal transmission, it is determined that top layer covers
The metal wire of lid is effectively connection, and then determines that top-level metallic covering function is normal；If there is metal wire data not by just
Often transmission, such as metal wire are drawn and are broken, then the circuit logic value at metal wire both ends differs, it is determined that top-level metallic covering function
There are exceptions.Fig. 1 is the logic integrity circuit schematic diagram of single metal line, as shown in Figure 1, respectively adding at metal wire both ends one anti-
Phase device determines that metal wire effectively connects if the data output of metal wire is equal to data input (Dout=Din)；If metal wire
Data output inputs not identical with data, it is determined that metal wire connection is invalid, and chip protects circuit to pass through report by malicious sabotage
Alert signal notifies chip control circuit, realizes the protection to chip.Fig. 2 is the principle of existing chip logic integrity circuit
Figure, as shown in Fig. 2, the metal wire that top layer covers is divided into n group (n >=2) by logic integrity circuit, every group includes m metal
Line (m >=2).When logic integrity circuit works, applies certain data in the input of metal wire, judge whether Din [i] is equal to
Dout [i] (i=1~m), by comparing, whether two end data of n*m metal line is equal to judge whether chip is attacked.Base
In the method that logic integrity circuit carries out the test of chip top-layer metal covering include following two: the first is, passes through logic
Whether integrity circuit, which generates alarm signal, determines chip whether function is normal；Second is that logic integrity circuit does not generate
Under the premise of alarm signal, draws selected several metal lines of breaking and determine chip if logic integrity circuit produces alarm
Function is normal.
Existing chip top-layer metal covering test method has the following problems: when being tested using first method,
Only there is no whether to generate alarm signal in situation under attack to logic integrity circuit and determines whether top-level metallic covering is complete；
Alarm signal whether can be generated when not under attack to logic integrity circuit to test, and cannot achieve the number to chip interior
According to offer protection.Second of test method is to make chip by destroying several metal wires on the basis of the first test method
Top-level metallic covering goes wrong, and generates alarm by logic integrity circuit and determines that logic integrity circuit function is normal, the
Two kinds of test methods are destructive testings, and chip top-layer metal covering one can not be represented by drawing the test that several metal wires carry out of breaking
It is fixed that there is no problem；In addition, the result individually tested cannot represent the test of all chips, this test method is not used to core
The volume production of piece is tested；In addition, there is also inefficiency, problems at high cost for this test method.Summary, existing method can not
It determines the test of chip top-layer metal covering effectively, can not effectively reject the chip of metal wire Joint failure.
Summary of the invention
In order to solve the above technical problem, the present invention provides a kind of methods for realizing chip top-layer metal covering circuit test
And device, it can determine logic integrity circuit function under normal circumstances, chip top-layer metal covering circuit is being tested.
It is right the present invention provides a kind of method for realizing the test of chip top-layer metal covering in order to reach the object of the invention
All metal wires of top-level metallic covering circuit, comprising:
Gradually selected section metal wire in batches carries out the signal overturning of input data；
Input data and output number when each batch metal wire completes the signal overturning of input data, to all metal wires
It is analyzed according to being compared；
Summarized according to the comparative analysis result of the input data of all batches and output data, it is true according to summarized results
Whether the function of determining chip top-layer metal covering circuit is normal.
Optionally, selected section metal wire progress input data signal gradually in batches, which is overturn, includes:
The each group metal wire of top-level metallic covering circuit is ranked up respectively；
Successively according to sequence, it did not carried out gradually selecting the first default number of branches in the metal wire of the signal overturning from each group
Metal wire carry out input data signal overturning；
First default number of branches be one or one or more.
Optionally, being compared analysis to input data and output data includes:
When each batch metal wire completes the signal overturning of input data,
Each metal wire input data of circuit and defeated is covered by top-level metallic described in logic integrity circuit comparative analysis
Data out, determine whether each metal wire input data and output data are equal；
The anti-data for taking the input data of each metal wire of the top-level metallic covering circuit, pass through the logic integrality
Whether the anti-data of the input data of each metal wire of circuit comparative analysis are unequal with output data.
Optionally, determine chip top-layer metal covering circuit function whether normally include:
The comparative analysis result of the input data and the output data to all batches summarizes,
If the input data and the output data of each metal wire are equal, the input data of each metal wire
Anti- data and the output data it is unequal when, it is determined that chip the top-level metallic covering circuit function it is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the defeated of metal wire
The anti-data for entering data are equal with the output data of metal wire, it is determined that the top-level metallic covering circuit function of chip is different
Often.
On the other hand, the application also provides a kind of device for realizing the test of chip top-layer metal covering, comprising: signal overturning
Unit, in batches analytical unit and determination unit；Wherein,
Signal roll-over unit is used for, and all metal wires of circuit is covered to top-level metallic, gradually selector parting in batches
Belong to the signal overturning that line carries out input data；
Analytical unit is used in batches, when each batch metal wire completes the signal overturning of input data, to all metals
The input data and output data of line are compared analysis；
Determination unit is used for, and is summarized according to the comparative analysis result of the input data of all batches and output data,
Determine whether the function of chip top-layer metal covering circuit is normal according to summarized results.
Optionally, signal roll-over unit is specifically used for, to all metal wires of top-level metallic covering circuit, to each group metal
Line is ranked up respectively；
Successively according to sequence, the gold that the first default number of branches are selected in the metal wire of signal overturning was not carried out from each group gradually
Belong to the signal overturning that line carries out input data；
First default number of branches be one or one or more.
Optionally, analytical unit is specifically used in batches,
When each batch metal wire completes the overturning of input data signal,
Each metal wire input data of circuit and defeated is covered by top-level metallic described in logic integrity circuit comparative analysis
Data out, determine whether each metal wire input data and output data are equal；
The anti-data for taking the input data of each metal wire of the top-level metallic covering circuit, pass through the logic integrality
Whether the anti-data of the input data of each metal wire of circuit comparative analysis are unequal with output data.
Optionally, determination unit is specifically used for,
The comparative analysis result of the input data and the output data to all batches summarizes,
If the input data and the output data of each metal wire are equal, the input data of each metal wire
Anti- data and the output data it is unequal when, it is determined that chip the top-level metallic covering circuit function it is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the defeated of metal wire
The anti-data for entering data are equal with the output data of metal wire, it is determined that the top-level metallic covering circuit function of chip is different
Often.
Compared with prior art, technical scheme includes: all metal wires to top-level metallic covering circuit, gradually
Selected section metal wire in batches carries out the signal overturning of input data；The signal that each batch metal wire completes input data turns over
When turning, input data and output data to all metal wires are compared analysis；According to the input data of all batches and defeated
The comparative analysis result of data is summarized out, whether just to determine the function of chip top-layer metal covering circuit according to summarized results
Often.The method of the present invention is overturn by the signal that gradually selected section metal wire carries out input data in batches, to all batch signals
The input data and output data of overturning are compared analysis, are realized by logic integrity circuit and cover electricity to top-level metallic
Whether road function normally judges, reduces top-level metallic covering circuit test cost, improves top-level metallic covering circuit and surveys
The working efficiency of examination.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the logic integrity circuit schematic diagram of single metal line；
Fig. 2 is the schematic diagram of existing chip logic integrity circuit；
Fig. 3 is the flow chart for the method that the present invention realizes the test of chip top-layer metal covering；
Fig. 4 is the structural block diagram for the device that the present invention realizes the test of chip top-layer metal covering；
Fig. 5 is the structural block diagram that the present invention applies example logic integrity circuit；
Fig. 6 is this application example metals line line open circuit schematic diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Fig. 3 is the flow chart for the method that the present invention realizes the test of chip top-layer metal covering, as shown in figure 3, to top layer gold
Belong to all metal wires of covering circuit, comprising:
Step 300, selected section metal wire gradually in batches carry out the signal overturning of input data；
This step specifically includes: gradually selected section metal wire progress input data signal overturning in batches includes:
The each group metal wire of top-level metallic covering circuit is ranked up respectively；
Successively according to sequence, the gold that the first default number of branches are selected in the metal wire of signal overturning was not carried out from each group gradually
Belong to the signal overturning that line carries out input data；
First default number of branches be one or one or more.
It should be noted that the general value of the first default number of branches, which is one, carries out the test analysis that top-level metallic covers circuit
Relatively sharp convenience；When default number of branches are one, in the group of each group metal wire, each metal wire is compared with the metal wire in group
The overturning of signal is certainly existed, may be implemented that there are the case where adhesion to test to metal wire in organizing；It is above-mentioned gradually in batches
Selected section metal wire carry out input data signal overturning method be the embodiment of the present invention alternative embodiment；Whether
Be ranked up, whether the identical item number metal wire of every group selection, if every group require selection metal wire carry out input data letter
Number overturning, can be adjusted according to practical application by those skilled in the art.Optionally, present invention progress signal overturning can
To be that each metal wire has and only once carry out signal overturning, i.e., all metal wires necessarily pass a signal overturning.
When step 301, each batch metal wire complete the signal overturning of input data, to the input data of all metal wires
Analysis is compared with output data；
In this step, being compared analysis to input data and output data includes:
When each batch metal wire completes the overturning of input data signal,
Each metal wire input data and output number of circuit are covered by logic integrity circuit comparative analysis top-level metallic
According to determining whether each metal wire input data and output data are equal；
The anti-data for taking the input data of each metal wire of top-level metallic covering circuit, are compared by logic integrity circuit
Whether anti-data and the output data for analyzing the input data of each metal wire are unequal.
Step 302 is summarized according to the input data of all batches and the comparative analysis result of output data, according to remittance
Overall result determines whether the function of chip top-layer metal covering circuit is normal.
In this step, determine chip top-layer metal covering circuit function whether normally include:
The comparative analysis result of input data and output data to all batches summarizes,
If each metal wire input data and output data are equal, the anti-data and output of the input data of each metal wire
When data are unequal, it is determined that the top-level metallic covering circuit function of chip is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the defeated of metal wire
The anti-data for entering data are equal with the output data of metal wire, it is determined that the top-level metallic covering circuit function of chip is abnormal.
The method of the present invention is overturn by the signal that gradually selected section metal wire carries out input data in batches, to all batches
The input data and output data of signal overturning are compared analysis, and avoiding logic integrity circuit operation irregularity influences to top
Whether layer metal covering circuit function normally judges；Top-level metallic covering circuit test cost is reduced, top layer gold is improved
Belong to the working efficiency of covering circuit test.
Fig. 4 is the structural block diagram for the device that the present invention realizes the test of chip top-layer metal covering, as shown in Figure 4, comprising: letter
Number roll-over unit, in batches analytical unit and determination unit；Wherein,
Signal roll-over unit is used for, and all metal wires of circuit is covered to top-level metallic, gradually selector parting in batches
Belong to the signal overturning that line carries out input data；
Signal roll-over unit is specifically used for, and to all metal wires of top-level metallic covering circuit, distinguishes each group metal wire
It is ranked up；
Successively according to sequence, the gold that the first default number of branches are selected in the metal wire of signal overturning was not carried out from each group gradually
Belong to the signal overturning that line carries out input data；
First default number of branches be one or one or more.
Analytical unit is used in batches, when each batch metal wire completes the signal overturning of input data, to all metals
The input data and output data of line are compared analysis；
Analytical unit is specifically used in batches,
When each batch metal wire completes the overturning of input data signal,
Each metal wire input data and output number of circuit are covered by logic integrity circuit comparative analysis top-level metallic
According to determining whether each metal wire input data and output data are equal；
The anti-data for taking the input data of each metal wire of top-level metallic covering circuit, are compared by logic integrity circuit
Whether anti-data and the output data for analyzing the input data of each metal wire are unequal.
Determination unit is used for, and is summarized according to the comparative analysis result of the input data of all batches and output data,
Determine whether the function of chip top-layer metal covering circuit is normal according to summarized results.
Determination unit is specifically used for,
The comparative analysis result of input data and output data to all batches summarizes；
If each metal wire input data and output data are equal, the anti-data and output of the input data of each metal wire
When data are unequal, it is determined that the top-level metallic covering circuit function of chip is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the defeated of metal wire
The anti-data for entering data are equal with the output data of metal wire, it is determined that the top-level metallic covering circuit function of chip is abnormal.
The method of the present invention is carried out below by way of specific embodiment to understand that detailed description, embodiment are only used for stating this hair
It is bright, it is not intended to limit the present invention the protection scope of method.
Embodiment
Fig. 5 is the structural block diagram that the present invention applies example logic integrity circuit, as shown in figure 5, clk is clock signal,
Rst is reset signal, and en is work enable signal, and rn is random number input signal, and te is test enable signal, and error is top
The alarm signal of layer metal covering circuit operation irregularity.
The metal wire of the top-level metallic covering circuit of chip is divided into n group, every group of 8 metal lines, i.e. m=by this application example
8.After system reset, every group of metal wire ([8:1]) initial value is complete " 0 ".Work is enabled to open (en=" 1 "), and logic is complete
Property circuit enters operating mode, and whether the top-level metallic circuit for starting detection chip is working properly.Logic integrity circuit is supported
Cycle detection.
Metal wire covers entire chip, when testing chip top-layer metal covering circuit, if metal wire line is just
Often, then the input data with output data of metal wire should be all equal.It is unequal with output data if there is input data
Situation, it is determined that the top-level metallic of chip covers circuit operation irregularity.
The selected section metal wire of this application example successive in batches carries out the signal overturning of input data；
Input data and output number when each batch metal wire completes the signal overturning of input data, to all metal wires
It is analyzed according to being compared；
Summarized according to the comparative analysis result of the input data of all batches and output data, it is true according to summarized results
Whether the function of determining chip top-layer metal covering circuit is normal.
Fig. 6 is this application example metals line line open circuit schematic diagram, as shown in fig. 6, after being ranked up to every group of metal wire,
Successively according to sequence, it selects one group of metal wire to carry out the Data flipping of input signal each time, i.e., circuit is covered to top-level metallic
Metal wire carried out one by one according to single-bit signal overturning mode traversed, due to metal wire disconnect, input data with
Output data is inevitable different, it can be determined that the top-level metallic of the chip covers circuit abnormality, i.e. chip exists abnormal, by should
Determine there is abnormal chip with exemplary test method object, to carry out the screening and rejecting processing of chip.This application example
Design is simple, and test is efficient, can be used for the test of top-level metallic covering circuit when chip volume production.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (6)
1. a kind of method for realizing the test of chip top-layer metal covering characterized by comprising
The signal that gradually the part metals line of selection each group top-level metallic covering electric circuit metal line carries out input data in batches turns over
Turn；
The every group of metal wire input data and output of circuit are covered by top-level metallic described in logic integrity circuit comparative analysis
Data, determine whether each metal wire input data and output data are equal；
The anti-data for taking the input data of every group of metal wire of the top-level metallic covering circuit pass through the logic integrality electricity
Whether the anti-data of the input data of each metal wire of road comparative analysis are unequal with output data；
Summarized according to the comparative analysis result of the input data of all batches and output data, core is determined according to summarized results
Whether the function that piece top-level metallic covers circuit is normal.
2. the method according to claim 1, wherein described, gradually the covering of selection each group top-level metallic is electric in batches
The part metals line of road metal wire carries out the overturning of input data signal
The each group metal wire of top-level metallic covering circuit is ranked up respectively；
Successively according to sequence, the gold that the first default number of branches are selected in the metal wire of the signal overturning was not carried out from each group gradually
Belong to the signal overturning that line carries out input data；
First default number of branches be one or one or more.
3. method according to claim 1 or 2, which is characterized in that the function of the determining chip top-layer metal covering circuit
Can whether normally include:
The comparative analysis result of the input data and the output data to all batches summarizes,
If the input data and the output data of every group of metal wire are equal, the input data of every group of metal wire
Anti- data and the output data it is unequal when, it is determined that chip the top-level metallic covering circuit function it is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the input numbers of metal wire
According to anti-data it is equal with the output data of metal wire, it is determined that the top-level metallic of chip covering circuit function is abnormal.
4. a kind of device for realizing the test of chip top-layer metal covering in batches characterized by comprising signal roll-over unit divides
Analyse unit and determination unit；Wherein,
Signal roll-over unit is used for, gradually in batches selection each group top-level metallic covering electric circuit metal line part metals line into
The signal of row input data is overturn；
Analytical unit is used in batches, and every group of metal of circuit is covered by top-level metallic described in logic integrity circuit comparative analysis
Line input data and output data, determine whether each metal wire input data and output data are equal；
The anti-data for taking the input data of every group of metal wire of the top-level metallic covering circuit pass through the logic integrality electricity
Whether the anti-data of the input data of each metal wire of road comparative analysis are unequal with output data；
Determination unit is used for, and is summarized according to the comparative analysis result of the input data of all batches and output data, according to
Summarized results determines whether the function of chip top-layer metal covering circuit is normal.
5. device according to claim 4, which is characterized in that signal roll-over unit is specifically used for, and covers to top-level metallic
The each group metal wire of circuit is ranked up respectively；
Successively according to sequence, the metal wire that the first default number of branches are selected in the metal wire of signal overturning was not carried out from each group gradually
Carry out the signal overturning of input data；
First default number of branches be one or one or more.
6. device according to claim 4 or 5, which is characterized in that the determination unit is specifically used for,
The comparative analysis result of the input data and the output data to all batches summarizes,
If the input data and the output data of each metal wire are equal, the input data of each metal wire it is anti-
When data and the output data are unequal, it is determined that the top-level metallic covering circuit function of chip is normal；
The output data of input data and metal wire if there is metal wire is unequal；And/or there are the input numbers of metal wire
According to anti-data it is equal with the output data of metal wire, it is determined that the top-level metallic of chip covering circuit function is abnormal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510994235.1A CN105629154B (en) | 2015-12-25 | 2015-12-25 | A kind of method and device for realizing chip top-layer metal covering circuit test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510994235.1A CN105629154B (en) | 2015-12-25 | 2015-12-25 | A kind of method and device for realizing chip top-layer metal covering circuit test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105629154A CN105629154A (en) | 2016-06-01 |
| CN105629154B true CN105629154B (en) | 2019-01-25 |
Family
ID=56044272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510994235.1A Active CN105629154B (en) | 2015-12-25 | 2015-12-25 | A kind of method and device for realizing chip top-layer metal covering circuit test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105629154B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106503780B (en) * | 2016-10-31 | 2019-05-14 | 天津大学 | Integrality detection method and device for chip top-layer metal protection layer |
| CN108090384B (en) * | 2017-11-06 | 2021-08-03 | 大唐微电子技术有限公司 | Metal wire detection device and chip |
| CN109726507B (en) * | 2019-01-17 | 2023-04-18 | 湖南进芯电子科技有限公司 | Efficient multifunctional verification method |
| CN109782154A (en) * | 2019-02-27 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of tamper detection protection circuit, implementation method and tamper chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162484A (en) * | 2006-10-10 | 2008-04-16 | 北京中电华大电子设计有限责任公司 | Method for preventing from active-attacking |
| CN102708219A (en) * | 2011-12-13 | 2012-10-03 | 西安交通大学 | Method for predicting voltage value of full-open defect of interconnecting wire of deep sub-micron integrated circuit |
| CN202512206U (en) * | 2011-11-17 | 2012-10-31 | 大唐微电子技术有限公司 | Detection device and system of physical integrality of chip |
| CN103413106A (en) * | 2013-08-05 | 2013-11-27 | 大唐微电子技术有限公司 | Method and device for protecting chip top-layer covering integrity |
| CN103440452A (en) * | 2013-08-20 | 2013-12-11 | 大唐微电子技术有限公司 | Chip physical integrity detecting device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3112076B2 (en) * | 1998-05-21 | 2000-11-27 | 豊 保倉 | User authentication system |
| US6750506B2 (en) * | 1999-12-17 | 2004-06-15 | Matsushita Electric Industrial Co., Ltd. | High-voltage semiconductor device |
| CN1128510C (en) * | 2001-01-13 | 2003-11-19 | 深圳市中兴通讯股份有限公司 | Single board with non-return standby protection |
| US20080114582A1 (en) * | 2006-11-10 | 2008-05-15 | Texas Instruments Incorporated | Detecting tampering of a signal |
| US8154315B2 (en) * | 2008-04-08 | 2012-04-10 | Formfactor, Inc. | Self-referencing voltage regulator |
| JP5326359B2 (en) * | 2008-05-23 | 2013-10-30 | 東京エレクトロン株式会社 | Needle mark inspection device, probe device, needle mark inspection method, and storage medium |
| CN101655922B (en) * | 2009-09-11 | 2012-05-09 | 西安电子科技大学 | Passive ultrahigh frequency radio frequency identification chip backscatter link frequency generation circuit and method |
| CN101865977B (en) * | 2010-05-27 | 2015-11-25 | 复旦大学 | Based on the traversal method of testing of the FPGA programmable logic cells of look-up table configuration |
| US8558613B2 (en) * | 2011-08-02 | 2013-10-15 | Analog Devices, Inc. | Apparatus and method for digitally-controlled automatic gain amplification |
| US10678951B2 (en) * | 2011-10-24 | 2020-06-09 | Maxim Integrated Products, Inc. | Tamper detection countermeasures to deter physical attack on a security ASIC |
-
2015
- 2015-12-25 CN CN201510994235.1A patent/CN105629154B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162484A (en) * | 2006-10-10 | 2008-04-16 | 北京中电华大电子设计有限责任公司 | Method for preventing from active-attacking |
| CN202512206U (en) * | 2011-11-17 | 2012-10-31 | 大唐微电子技术有限公司 | Detection device and system of physical integrality of chip |
| CN102708219A (en) * | 2011-12-13 | 2012-10-03 | 西安交通大学 | Method for predicting voltage value of full-open defect of interconnecting wire of deep sub-micron integrated circuit |
| CN103413106A (en) * | 2013-08-05 | 2013-11-27 | 大唐微电子技术有限公司 | Method and device for protecting chip top-layer covering integrity |
| CN103440452A (en) * | 2013-08-20 | 2013-12-11 | 大唐微电子技术有限公司 | Chip physical integrity detecting device |
Non-Patent Citations (1)
| Title |
|---|
| 电信智能卡芯片安全技术分析;薛元星 等;《中国集成电路》;20050310;83-85,88 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105629154A (en) | 2016-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105629154B (en) | A kind of method and device for realizing chip top-layer metal covering circuit test | |
| CN106506556B (en) | A kind of network flow abnormal detecting method and device | |
| CN103926496B (en) | The test device and method and touch-screen module of touch-screen module | |
| US10249125B2 (en) | Seal and method for testing a product for manipulation | |
| CN104422816B (en) | Residual current detection method and apparatus | |
| CN106411956A (en) | Method and device for analyzing automobile bus safety | |
| CN107636922A (en) | The improvement of DC plating system or and its related improvement | |
| CN111667476B (en) | Cloth flaw detection method and device, electronic equipment and readable storage medium | |
| CN104298586A (en) | Web system exception analytical method and device based on system log | |
| CN109470978A (en) | Determine the method and device of the shorted-turn fault of reactor | |
| CN105765683A (en) | Method and apparatus for monitoring at least one electronic switching contact for a vehicle | |
| CN106680649A (en) | Nuclear power plant earth fault detecting method and device | |
| CN113010577A (en) | Cable insulation defect detection method and device and terminal equipment | |
| CN104501873B (en) | Integrated information monitoring system for ring main unit | |
| CN110162973A (en) | A kind of Webshell file test method and device | |
| CN103400308A (en) | Online detection method and online detection system for running state of GIS (gas insulated switchgear) equipment | |
| CN107464333A (en) | Paper Currency Identification, device and terminal device | |
| CN104062555B (en) | The discrimination method of distribution line high resistance earthing fault characteristic harmonics | |
| CN110825630B (en) | Vulnerability mining method and device | |
| CN109325539A (en) | Insulator falls crosstalk detecting method and device | |
| CN104967113B (en) | It is identified using the electrical load of system line voltage | |
| CN104280189A (en) | Pressure sensor fault hardware detection method and device | |
| CN109698997B (en) | System and method for accessory and impedance detection | |
| CN106410764B (en) | A kind of calculation method and device of positive sequence polarization voltage | |
| CN105659624B (en) | Battery, battery control device and the method for safely Digital Transmission current measurement value |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200729 Address after: 2505 COFCO Plaza, No.2, nanmenwai street, Nankai District, Tianjin Patentee after: Xin Xin finance leasing (Tianjin) Co.,Ltd. Address before: 100094 No. 6 Yongjia North Road, Beijing, Haidian District Co-patentee before: DATANG SEMICONDUCTOR DESIGN Co.,Ltd. Patentee before: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211026 Address after: 100094 No. 6 Yongjia North Road, Beijing, Haidian District Patentee after: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Patentee after: DATANG SEMICONDUCTOR DESIGN Co.,Ltd. Address before: 300110 2505 COFCO Plaza, No. 2, nanmenwai street, Nankai District, Tianjin Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd. |