CN102695405A - Wafer level electromagnetic protection structure and manufacturing method thereof - Google Patents
Wafer level electromagnetic protection structure and manufacturing method thereof Download PDFInfo
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- CN102695405A CN102695405A CN2011100713359A CN201110071335A CN102695405A CN 102695405 A CN102695405 A CN 102695405A CN 2011100713359 A CN2011100713359 A CN 2011100713359A CN 201110071335 A CN201110071335 A CN 201110071335A CN 102695405 A CN102695405 A CN 102695405A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention discloses a wafer level electromagnetic protection structure which comprises a wafer and an electromagnetic protection unit. A top surface of the wafer has an exposed circuit unit, and a surface of the exposed circuit unit has a plurality of conductors. The electromagnetic protection unit has a first electromagnetic protection layer which is around the wafer and is arranged on a surrounding surface of the wafer and a second wafer electromagnetic protection layer which covers a bottom surface of the wafer. The invention also discloses a manufacturing method of the wafer level electromagnetic protection structure. According to the wafer level electromagnetic protection structure, through a wafer level fabrication method, the electromagnetic protection structure is a miniature electromagnetic protection structure, and thus each wafer has a shielding effect of preventing electromagnetic interference.
Description
Technical field
The present invention relates to a kind of electromagnetic protection structure and manufacturing approach thereof, particularly relate to a kind of wafer scale electromagnetic protection structure and manufacturing approach thereof.
Background technology
The topmost purposes of electromagnetic protection structure (EMI Shielding Structure) is the generation that prevents the electromagnetic interference phenomenon between the various electronic circuit components; From textural theory, the electromagnetic protection structure is mainly formed by base board unit, electronic circuit cell, metal protection unit, electric connection unit combination.Electronic circuit component with electromagnetic protection structure can be widely used in the middle of the product miscellaneous, and for example each items such as notebook computer, mobile phone, e-book, panel computer, electronic game main frame, communication product, digital frame, automobile-used satellite navigation, DTV are used.
Existing related techniques is such; When making the electromagnetic protection structure, the substrate of electromagnetic protection structure and electronic circuit component must adopt various electric connection modes, cause overall structure too huge; Perhaps the thickness of finished product is blocked up, and this has just run counter to the compact trend of electronic product now.Therefore, be badly in need of a kind of frivolous, miniature electromagnetic protection structure of research and development at present.
Summary of the invention
The technical problem that the present invention will solve is to electrically connect the mode complicacy and cause the blocked up defective of electromagnetic protection structural entity structure thickness too huge, finished product in order to overcome prior art electromagnetic protection structure, and a kind of frivolous, micro electromagnetic safeguard structure and manufacturing approach thereof are provided.
The present invention solves above-mentioned technical problem through following technical proposals:
A kind of wafer scale electromagnetic protection structure comprises: a wafer and an electromagnetic protection unit.The end face of wafer has one and exposes line unit, and exposes on the surface of line unit and have a plurality of conductors.The electromagnetic protection unit have one around and be arranged at second overcoat that the first electromagnetic protection layer and on the circumferential surface of wafer is covered in the wafer bottom surface.The first electromagnetic protection layer and the second electromagnetic protection layer interconnect, and make both form electric connection to each other.
Preferably, this wafer is a Silicon Wafer, and this conductor is tin ball or metal coupling.
Preferably, this first electromagnetic protection layer is a metal material, and this second electromagnetic protection layer is the metal sputtering layer.
Another technical scheme of the present invention is: a kind of manufacturing approach of wafer scale electromagnetic protection structure, and its characteristics are that it may further comprise the steps:
One wafer substrate is provided, and wherein the end face of this wafer substrate has a plurality of line units that expose;
End face in this wafer substrate forms many grooves, and wherein each bar groove exposes between the line unit at two;
In those grooves, form one first electric conducting material;
Expose at each and to form a plurality of conductors on the surface of line unit;
Remove the bottom surface of this wafer substrate, to form a plurality of wafers and to make the bottom surface of this first electric conducting material expose out, those wafers distance separated from one another and correspond respectively to those and expose line unit wherein;
One second electric conducting material is covered simultaneously on the bottom surface of those wafers and on the bottom surface of this first electric conducting material; And
Along those groove this first electric conducting material of cutting and this second electric conducting material, to form a plurality of wafer scale electromagnetic protection structures.
Preferably, this second electric conducting material forms through sputtering way.
Preferably, the underrun lapping mode of this wafer substrate removes.
Preferably, those conductors are tin ball or metal coupling.
Preferably, in the above-mentioned cutting step, this first electric conducting material is cut into a plurality of first electromagnetic protection layers, and this second electric conducting material is cut into a plurality of second electromagnetic protection layers.
Preferably, each wafer scale electromagnetic protection structure includes:
One wafer, this wafer end face has one and exposes line unit, and this exposes on the surface of line unit and has a plurality of conductors; And
One electromagnetic protection unit; This electromagnetic protection unit has one first electromagnetic protection layer and one second electromagnetic protection layer; This first electromagnetic protection layer centers on and is arranged on the circumferential surface of this wafer, and this second electromagnetic protection layer is covered in the bottom surface of this wafer and links this first electromagnetic protection layer.
Preferably, this first electromagnetic protection layer and this second electromagnetic protection layer are formed by metal material.
Preferably, this first electromagnetic protection layer and this second electromagnetic protection layer constitute an electromagnetic protection unit, and this electromagnetic protection unit is used to prevent that this wafer and external environment condition from producing the electromagnetic interference effect.
Positive progressive effect of the present invention is: wafer scale electromagnetic protection structure provided by the present invention is the electromagnetic protection structure with microstructure.Can be through the manufacturing method thereof of wafer scale; And through on the circumferential surface that the first electromagnetic protection layer and the second electromagnetic protection layer is arranged at wafer respectively and on the bottom surface; Constitute the electromagnetic protection unit, make wafer and expose the effect that line unit all has the electromagnetic interference of preventing.
Description of drawings
Fig. 1 is the generalized section of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 A is the generalized section of the first step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 B is the generalized section of second step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 C is the generalized section of the third step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 D is the generalized section of the 4th step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 E is the generalized section of the 5th step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 F is the generalized section of the 6th step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 2 G is the generalized section of the 7th step of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.
Fig. 3 is the vertical view of Fig. 2 B.
Fig. 4 is the schematic flow sheet of each step of the manufacturing approach of wafer scale electromagnetic protection structure of the present invention.
Description of reference numerals
1 wafer
1 ' wafer substrate
2 expose line unit
3 electromagnetic protection unit
31 first electromagnetic protection layers
31 ' first electric conducting material
32 second electromagnetic protection layers
32 ' second electric conducting material
4 conductors
Embodiment
In order to further specify technical characterictic of the present invention and technology contents, will be described with reference to the accompanying drawings technical scheme of the present invention below, but here explanation and accompanying drawing only are to be used for explaining the present invention, and unrestricted claim scope of the present invention.
See also shown in Figure 1ly, it is the generalized section of one of them embodiment of wafer scale electromagnetic protection structure of the present invention.According to one of them embodiment of wafer scale electromagnetic protection structure of the present invention, this wafer scale electromagnetic protection structure comprises: a wafer 1, exposes a line unit 2 and an electromagnetic protection unit 3.
It is made that wafer 1 can be a silicon wafer substrate (Silicon wafer substrate) material.The end face of wafer 1 has the line unit of exposing 2, and exposes on the surface of line unit 2 and have a plurality of conductors 4.In addition, conductor 4 can be tin ball or other conductive projection (for example metal coupling), makes conductor 4 have good electrical conductivity concurrently.Expose the circuit that exposes that line unit 2 can be integrated circuit (Integrated circuit), but be not limited to this.
In order to form good electromagnetic shielding action, then the overall structure of wafer scale electromagnetic protection structure need have the characteristic of ground connection.Therefore, electromagnetic protection unit 3 need form with the ground connection position of wafer 1 and electrically connect.Above-mentioned ground connection position is arranged at the side of wafer 1, just the circumferential surface of wafer 1.In other words, when the first electromagnetic protection layer 31 contacts with the circumferential surface of wafer 1, just formed electrical connection.Through above-mentioned electrical connection, make electromagnetic protection unit 3 can bring into play best effectiveness.
See also shown in Fig. 2 A to Fig. 2 G, its be respectively one of them embodiment of the present invention first, second, third and fourth, the generalized section of the manufacture method of five, six and seven steps.The manufacture method of wafer scale electromagnetic protection structure according to the present invention, it comprises step:
First step (seeing also Fig. 2 A) at first, provides a wafer substrate 1 ', and wherein the end face of this wafer substrate 1 ' has a plurality of line units 2 that expose.Certainly, the end face of this wafer substrate 1 ' also can only be provided with at least one and exposes line unit 2.Therefore, the quantity that exposes line unit 2 of the present invention can decide along with different design requirements.
Second step (seeing also Fig. 2 B) forms many grooves 11 at the end face of wafer substrate 1 ', and wherein each bar groove 11 exposes between the line unit 2 at two.That is to say; Be made on the wafer substrate 1 ' if will expose line unit 2 with array format; Then groove 11 will be checkerboard and be arranged at wafer substrate 1 ' crisscrossly and go up and (see also shown in Figure 3; Fig. 3 is the vertical view of Fig. 2 B, and this helps those skilled in the art more to understand the configuration mode of the groove 11 described in this step).Certainly, the groove 11 that forms at wafer substrate 1 ' end face also can be at least one.Therefore, the quantity of groove 11 of the present invention can decide along with different design requirements.
Third step (seeing also Fig. 2 C) forms one first electric conducting material 31 ' in groove 11.That is to say, first electric conducting material 31 ' is inserted in all grooves 11.
The 4th step (seeing also Fig. 2 D) exposes to form a plurality of conductors 4 on the surface of line unit 2 at each, and conductor is electrically connected at respectively and exposes line unit 2.Wherein, above-mentioned conductor 4 can be tin ball or other conductive projection (for example metal coupling).
The 5th step (seeing also Fig. 2 E) removes the bottom surface of wafer substrate 1 ', to form a plurality of wafers 1 and to make the bottom surface of the electric conducting material 31 ' of winning expose out, and wafer 1 specific range separated from one another and correspond respectively to and expose line unit 2 wherein.The mode that removes of the bottom surface of above-mentioned wafer substrate 1 ' can be grinding.Also we can say, through the mode of grinding, make the thickness attenuation of wafer substrate 1 ', and then make the bottom surface of the electric conducting material 31 ' of winning expose out.Therefore, wafer substrate 1 ' is separated out by first electric conducting material 31 ' and exposes a plurality of zones that line unit 2 quantity equate, wherein each zone is separately independently wafer 1.
The 6th step (seeing also Fig. 2 F) covers one second electric conducting material 32 ' on the bottom surface of each wafer 1 and on the bottom surface of first electric conducting material 31 ' simultaneously.Wherein second electric conducting material 32 ' can form through sputter or other mode.
The 7th step (seeing also Fig. 2 G), along each bar groove 11 cutting first electric conducting materials 31 ' and second electric conducting material 32 ' to form a plurality of wafer scale electromagnetic protection structures.To this stage, just accomplished the manufacturing of wafer scale electromagnetic protection structure of the present invention.
Through above-mentioned cutting step, first electric conducting material 31 ' is cut into a plurality of first electromagnetic protection layer, 31, the second electric conducting material 32 ' and is cut into a plurality of second electromagnetic protection layers 32.Wherein the first electromagnetic protection layer 31 and the second electromagnetic protection layer 32 constitute a plurality of electromagnetic protections unit 3, and this a plurality of electromagnetic protections unit 3 is used to prevent to expose line unit 2 and produces the electromagnetic interference effect with external environment condition.And electromagnetic protection unit 3 electrically connects through directly contacting to form with the ground connection position of wafer 1.In the present invention, the material of each element is selected for use and is met economic benefits and conductor characteristics fine copper or copper alloy preferably most, but is not limited to this, and the material of each element also can be other metal materials with good conductive properties.Therefore, the first electromagnetic protection layer 31 and the second electromagnetic protection layer 32 can be formed by copper metal material.
See also shown in Figure 4ly, it is the schematic flow sheet of each step of the manufacturing approach of wafer scale electromagnetic protection structure of the present invention.Mark S401～S407 among the figure representes first step to the seven steps of one of them embodiment of the present invention respectively.Can more understand the flow process of integral manufacturing method of the present invention through Fig. 4.
According to the embodiment of the invention, above-mentioned wafer scale electromagnetic protection structure makes that through the manufacturing method thereof of wafer scale the electromagnetic protection structure is miniature electromagnetic protection structure.And,, make wafer and expose the shield effectiveness that line unit all has the electromagnetic interference of preventing to constitute the electromagnetic protection unit through on the circumferential surface that the first electromagnetic protection layer and the second electromagnetic protection layer is arranged at wafer respectively and on the bottom surface.
The above is merely embodiments of the invention, and it is not the restriction to claim of the present invention.
Though more than described embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, protection scope of the present invention is limited appended claims.Those skilled in the art can make numerous variations or modification to these execution modes under the prerequisite that does not deviate from principle of the present invention and essence, but these changes and modification all fall into protection scope of the present invention.
Claims (11)
1. wafer scale electromagnetic protection structure is characterized in that it comprises:
One wafer, this wafer end face has one and exposes line unit, and this exposes on the surface of line unit and has a plurality of conductors; And
One electromagnetic protection unit; This electromagnetic protection unit has one first electromagnetic protection layer and one second electromagnetic protection layer; This first electromagnetic protection layer centers on and is arranged on the circumferential surface of this wafer, and this second electromagnetic protection layer is covered in the bottom surface of this wafer and is connected with this first electromagnetic protection layer.
2. wafer scale electromagnetic protection structure as claimed in claim 1 is characterized in that this wafer is a Silicon Wafer, and this conductor is tin ball or metal coupling.
3. wafer scale electromagnetic protection structure as claimed in claim 1 is characterized in that, this first electromagnetic protection layer is a metal material, and this second electromagnetic protection layer is the metal sputtering layer.
4. the manufacturing approach of a wafer scale electromagnetic protection structure is characterized in that it may further comprise the steps:
One wafer substrate is provided, and wherein the end face of this wafer substrate has a plurality of line units that expose;
End face in this wafer substrate forms many grooves, and wherein each bar groove exposes between the line unit at two;
In those grooves, form one first electric conducting material;
Expose at each and to form a plurality of conductors on the surface of line unit;
Remove the bottom surface of this wafer substrate, to form a plurality of wafers and to make the bottom surface of this first electric conducting material expose out, those wafers distance separated from one another and correspond respectively to those and expose line unit wherein;
One second electric conducting material is covered simultaneously on the bottom surface of those wafers and on the bottom surface of this first electric conducting material; And
Along those groove this first electric conducting material of cutting and this second electric conducting material, to form a plurality of wafer scale electromagnetic protection structures.
5. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 4 is characterized in that, this second electric conducting material forms through sputtering way.
6. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 4 is characterized in that, the underrun lapping mode of this wafer substrate removes.
7. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 4 is characterized in that, those conductors are tin ball or metal coupling.
8. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 4 is characterized in that, in the above-mentioned cutting step, this first electric conducting material is cut into a plurality of first electromagnetic protection layers, and this second electric conducting material is cut into a plurality of second electromagnetic protection layers.
9. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 8 is characterized in that, each wafer scale electromagnetic protection structure includes:
One wafer, this wafer end face has one and exposes line unit, and this exposes on the surface of line unit and has a plurality of conductors; And
One electromagnetic protection unit; This electromagnetic protection unit has one first electromagnetic protection layer and one second electromagnetic protection layer; This first electromagnetic protection layer centers on and is arranged on the circumferential surface of this wafer, and this second electromagnetic protection layer is covered in the bottom surface of this wafer and links this first electromagnetic protection layer.
10. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 9 is characterized in that, this first electromagnetic protection layer and this second electromagnetic protection layer are formed by metal material.
11. the manufacturing approach of wafer scale electromagnetic protection structure as claimed in claim 9; It is characterized in that; This first electromagnetic protection layer and this second electromagnetic protection layer constitute an electromagnetic protection unit, and this electromagnetic protection unit is used to prevent that this wafer and external environment condition from producing the electromagnetic interference effect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011100713359A CN102695405A (en) | 2011-03-23 | 2011-03-23 | Wafer level electromagnetic protection structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100713359A CN102695405A (en) | 2011-03-23 | 2011-03-23 | Wafer level electromagnetic protection structure and manufacturing method thereof |
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| CN102695405A true CN102695405A (en) | 2012-09-26 |
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| CN2011100713359A Pending CN102695405A (en) | 2011-03-23 | 2011-03-23 | Wafer level electromagnetic protection structure and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104051433A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System And Method For Preventing Etch Arcing During Semiconductor Processing |
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
| CN110233139A (en) * | 2019-06-18 | 2019-09-13 | 青岛歌尔微电子研究院有限公司 | A kind of circuit unit packaging method |
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| US20030218257A1 (en) * | 2002-05-22 | 2003-11-27 | Toshiya Ishio | Semiconductor element, semiconductor device, and method for manufacturing semiconductor element |
| CN101075594A (en) * | 2006-05-16 | 2007-11-21 | 三星电机株式会社 | Semiconductor chip, method for manufacturing semiconductor chip and package of semiconductor chip |
| CN101150116A (en) * | 2007-06-14 | 2008-03-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure with electromagnetic shielding function and its making method |
| CN101290892A (en) * | 2007-04-17 | 2008-10-22 | 矽品精密工业股份有限公司 | Sensing type semiconductor device and its manufacture |
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2011
- 2011-03-23 CN CN2011100713359A patent/CN102695405A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030218257A1 (en) * | 2002-05-22 | 2003-11-27 | Toshiya Ishio | Semiconductor element, semiconductor device, and method for manufacturing semiconductor element |
| CN101075594A (en) * | 2006-05-16 | 2007-11-21 | 三星电机株式会社 | Semiconductor chip, method for manufacturing semiconductor chip and package of semiconductor chip |
| CN101290892A (en) * | 2007-04-17 | 2008-10-22 | 矽品精密工业股份有限公司 | Sensing type semiconductor device and its manufacture |
| CN101150116A (en) * | 2007-06-14 | 2008-03-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure with electromagnetic shielding function and its making method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051433A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System And Method For Preventing Etch Arcing During Semiconductor Processing |
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
| CN105405819B (en) * | 2015-11-06 | 2018-12-11 | 通富微电子股份有限公司 | Metallize wafer-level packaging method |
| CN110233139A (en) * | 2019-06-18 | 2019-09-13 | 青岛歌尔微电子研究院有限公司 | A kind of circuit unit packaging method |
| WO2020253148A1 (en) * | 2019-06-18 | 2020-12-24 | 潍坊歌尔微电子有限公司 | Encapsulation method for circuit units |
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Application publication date: 20120926 |