CN102655125A - Structure of two-sided sputtering metal layer for reducing warpage of silicon wafer - Google Patents
Structure of two-sided sputtering metal layer for reducing warpage of silicon wafer Download PDFInfo
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- CN102655125A CN102655125A CN2012100128542A CN201210012854A CN102655125A CN 102655125 A CN102655125 A CN 102655125A CN 2012100128542 A CN2012100128542 A CN 2012100128542A CN 201210012854 A CN201210012854 A CN 201210012854A CN 102655125 A CN102655125 A CN 102655125A
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Abstract
The invention relates to a structure of a two-sided sputtering metal layer for reducing warpage of a silicon wafer, and the structure is applied to the technical field of wafer-level chip size package. The structure is characterized in that a metal layer (2) is sputtered on the front surface of a silicon wafer (1) and is used for forming a graph, and another metal layer (3) is sputtered on the back surface of the silicon wafer (1) and is used for reducing the warpage of the silicon wafer; the thermal expansion coefficient of the metal layer sputtered on the back surface is larger than that of the metal layer sputtered on the front surface, the thickness of the metal layer sputtered on the back surface is smaller than that of the metal layer sputtered on the front surface, and vice versa; and when the expansion coefficient of the metal layers sputtered on the front surface and the back surface are same, the thicknesses of the metal layers sputtered on the front surface and the back surface are same. The structure has the characteristics that the warpage of the wafer is reduced by sputtering the metal layers on the back surface of the silicon wafer, wherein the metal layer is sputtered on the front surface of the silicon wafer.
Description
Technical field
The present invention relates to the structure that a kind of double-faced sputter metal level reduces the silicon wafer warpage, be applied to disc grade chip size encapsulation technology field.
Background technology
In recent years, electronic device develops with miniaturization to multi-functional, the disc grade chip size encapsulation in order to adapt to this requirement, to develop, and it can reduce production costs when satisfying these needs, the very potential main flow that becomes encapsulation technology of future generation.
A technical characterstic of disc grade chip size encapsulation is that it accomplishes encapsulation on disk.In the encapsulation process, be that carrier transmits in technical process with the disk, the operation that is cut into single chip is located at the last of assembling process.Because whole process is implemented under the disk state, thereby can batch processing reduce assembly cost.Wafer level packaging replaced in the encapsulation in the past chip with encapsulate between interconnection technique; Like line weldering, TAB, flip-chip welding etc.; Be characterized in before being cut into single chip; Employing is technological with the semiconductor preceding working procedure distribution of flip-chip same principle, and the method for chip bonding pad and outside terminal tie lines is the most basic, and tin ball bonding subsequently connects with electric test then to be carried out under the disk state.
Technology commonly used has that the splash-proofing sputtering metal layer carries out next step technologies such as plating soldered ball as Seed Layer on disk in this encapsulation.For guarantee the conductivity of metal level, metal level sputters on the whole wafer often, just after technologies such as electroplating soldered ball finishes, remove.
The problem here is that the residual stress that the splash-proofing sputtering metal layer causes on the silicon wafer can cause warpage.Residual stress comprises the intrinsic stress that forms in the splash-proofing sputtering metal layer process, the thermal stress that coefficient of thermal expansion mismatch causes.The warpage that residual stress causes can seriously cause the alignment issues of subsequent optical carving technology, and especially under the increasing trend of silicon wafer size, the residual stress of identical size can cause bigger warpage, causes more serious lithography alignment problem then.
Reduce the method that stress reduces the disk warpage thereby there have been some researchers to develop; Main method has, the suitable buffering metal level of sputter one deck thermal coefficient of expansion between metal level and disk; The sputter multiple layer metal; Reduce coefficient of thermal expansion mismatch or the like method through the material properties gradual change; Mention among the document Simulation of thermal stress in magnetron sputtered thin coating by finite element analysis like Julfikar Haider, the Ti metal level can cushion the stress between TiN material and the iron disk.But these methods can not reduce the warpage issues of silicon wafer effectively, and warpage issues still exists.Thereby, be guided out the application's inventive concept.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of method that can effectively reduce the silicon wafer warpage issues is provided, the present invention can eliminate the warpage issues that exists in the structure fully, has improved the precision of subsequent techniques such as photoetching etc. greatly.
The objective of the invention is to realize like this: a kind of structure of disk double-faced sputter metal level, the splash-proofing sputtering metal layer in the silicon wafer front is used to make figure and realizes functions such as follow-up electroplating technology; At silicon wafer back spatter metal level, be used to reduce warpage.It is characterized in that: silicon wafer double-faced sputter metal level reduces the silicon wafer warpage, improves the lithographic accuracy of subsequent technique.
Silicon wafer double-faced sputter metal level of the present invention; Described metal layer on back can be identical with front metal; During the situation identical with front metal; Or when the thermal coefficient of expansion of the metal level of front and back sputter was identical or rather, then back metal thickness should just can play the best effect that reduces warpage in front metal thickness is identical.
Silicon wafer double-faced sputter metal level of the present invention, described metal layer on back also can be selected other metal for use, comprises and is not limited to Ti, TiW, Cu, Cr, Ni.The back metal layer thickness is relevant with the thermal coefficient of expansion of selected metal level; If the thermal coefficient of expansion of back metal is greater than the thermal coefficient of expansion of front metal; Then the thickness of metal layer on back should be less than the thickness of front metal layer, otherwise, then should be greater than the thickness of front metal layer.Concrete thickness can use finite element software to calculate perhaps the metal level of sputter different-thickness overleaf, the thickness when choosing disk warpage minimum.
Silicon wafer double-faced sputter metal level of the present invention, metal layer on back can be a kind of metal level, also can be multiple metal level.The concrete number of plies of using can be chosen in practical application as required, plays cushioning effect and gets final product.
Silicon wafer double-faced sputter metal level of the present invention; Metal layer on back can keep up to positive all subsequent optical carving technologies always fully to be accomplished; Also can carry out technologies such as photoetching corrosion with the front metal layer synchronously; Keep consistent, thereby better reduce the silicon wafer warpage with the figure of front metal layer.
The positive metal level of making figure of the present invention can comprise that generally metal level making as thin as a wafer such as Ti/W or TiW/Cu is as adhesion layer.
When characteristics of the present invention were silicon wafer front splash-proofing sputtering metal layer, the back side is the splash-proofing sputtering metal layer also, thereby effectively reduced the silicon wafer warpage; Under the ideal situation; The stress that the metal level of silicon chip front and back causes is identical, stresses counteract, thus can eliminate the warpage of disk fully.
Description of drawings
Fig. 1 (a) is that the present invention is at silicon wafer initial condition sketch map.
(b) for the present invention in the silicon wafer front splash-proofing sputtering metal layer sketch map
(c) be that the present invention is at silicon wafer back spatter metal level sketch map
(d) be the present invention's sketch map after silicon wafer front metal layer is done photoetching corrosion
(e) be the present invention's sketch map after the silicon wafer metal layer on back is done photoetching corrosion
Fig. 2 is that the present invention is at silicon wafer back spatter and positive same metal layer sketch map
Fig. 3 is that the present invention is at silicon wafer back spatter multiple layer metal layer sketch map
Fig. 4 is the present invention's sketch map after removing metal layer on back after the completion of silicon wafer front lighting carving technology.
Among the figure, 1, silicon wafer; 2, front splash-proofing sputtering metal layer; 3, back spatter ground floor metal level; 4, back spatter second layer metal layer; 5, the three-layer metal layer of back spatter.
Embodiment
Fig. 2 is a kind of wafer level stress buffer structure provided by the invention, mainly is made up of the metal level (2) of silicon wafer (1), the positive sputter of silicon wafer (1), the metal level (3) that back spatter prevents warpage.
Shown in Fig. 1 (a), the splash-proofing sputtering metal layer 2 in the front of silicon wafer 1 (Fig. 1 (b)); Sputter is used to reduce the metal level 3 (like Fig. 1 (c)) of warpage overleaf then; Then make required figure (like Fig. 1 (d)) at the metal level 2 photoetching corrosion metal levels of positive sputter; Metal level 3 photoetching corrosions go out same figure (like Fig. 1 (e)) overleaf at last.
When sputter is used to reduce the metal level 3 of warpage overleaf, but sputter and front metal different metallic comprise being not limited to Ti, TiW, Cu, Cr or Ni; But also sputter and positive identical metal (as shown in Figure 2).
When the sputter metal level that is respectively ground floor, the second layer and the 3rd layer is used to reduce the metal level of warpage overleaf; But the multiple layer metal 3,4,5 (as shown in Figure 3) that the sputter thermal coefficient of expansion is different, this figure only limits to explain the multiple layer metal situation, multilayer can be three layers; But it is three layers that multiple layer metal does not refer in particular to; Can be greater than three layers, the concrete number of plies of using can be chosen in practical application as required, plays cushioning effect and gets final product.
The metal level of back spatter can be removed after photoetching process is accomplished in the front, and is as shown in Figure 4.
Sputtering technology can be used sputtering methods such as magnetron sputtering; Generally; Front metal should use identical technological parameter with back metal, produces identical as far as possible metal-layer structure producing identical stress, thereby thereby front back metal stress cancel out each other and eliminate the disk warpage.
Claims (10)
1. a double-faced sputter metal level reduces the structure of silicon wafer warpage, it is characterized in that being sputtered in the metal level (3) that positive being used for of silicon wafer (1) made the metal level (2) of figure in the future, is used to reduce the silicon wafer warpage at the back spatter of silicon wafer (1); The thermal coefficient of expansion of the back metal of institute's sputter is greater than the thermal coefficient of expansion of front splash-proofing sputtering metal, and then the metal layer thickness of back spatter is less than the thickness of front splash-proofing sputtering metal layer, and vice versa; Then the metal layer thickness of obverse and reverse sputter is identical when the expansion of metal coefficient of front and back sputter is identical.
2. structure according to claim 1 is characterized in that, the metal layer on back metal can be identical with front metal layer metal, also can be different with the metal of front metal layer, and the metal of described metal level includes, but are not limited to Ti, TiW, Cu, Cr or Ni.
3. according to claim 1,2 described structures, it is characterized in that: metal layer on back is layer of metal or multiple layer metal.
4. structure according to claim 3 is characterized in that: the multiple layer metal layer is three layers, but is not limited to three layers.
5. structure according to claim 1 and 2 is characterized in that: metal layer on back can be made with the identical figure of front metal layer and come further to reduce warpage.
6. structure according to claim 1 and 2 is characterized in that: metal layer on back is removed after positive all subsequent optical carving technologies are accomplished; Or carry out lithography corrosion process synchronously with the front metal layer.
7. structure according to claim 1 and 2 is characterized in that: the metal level (2) of making figure comprises that Ti/W layer or TiW/Cu layer play the metal level of adhesive attraction.
8. structure according to claim 3 is characterized in that: metal layer on back can be made with the identical figure of front metal layer and come further to reduce warpage.
9. structure according to claim 3 is characterized in that: metal layer on back is removed after positive all subsequent optical carving technologies are accomplished; Or carry out lithography corrosion process synchronously with the front metal layer.
10. structure according to claim 3 is characterized in that: the metal level (2) of making figure comprises that Ti/W layer or TiW/Cu layer play the metal level of adhesive attraction.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100128542A CN102655125A (en) | 2012-01-16 | 2012-01-16 | Structure of two-sided sputtering metal layer for reducing warpage of silicon wafer |
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| CN2012100128542A CN102655125A (en) | 2012-01-16 | 2012-01-16 | Structure of two-sided sputtering metal layer for reducing warpage of silicon wafer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102015104570B4 (en) | 2015-03-26 | 2019-07-11 | Infineon Technologies Ag | POWER CHIP AND CHIP ASSEMBLY |
| CN111555112A (en) * | 2020-05-21 | 2020-08-18 | 常州纵慧芯光半导体科技有限公司 | Light-emitting device, manufacturing method thereof and laser equipment |
| CN113140541A (en) * | 2021-03-31 | 2021-07-20 | 成都芯源系统有限公司 | Integrated circuit unit and wafer with integrated circuit unit |
| CN113866860A (en) * | 2021-09-22 | 2021-12-31 | 华天慧创科技（西安）有限公司 | Ultrathin wafer optical narrowband filter and preparation method thereof |
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| JPH02246117A (en) * | 1989-03-17 | 1990-10-01 | Mitsubishi Electric Corp | Formation of thin film |
| US20030117784A1 (en) * | 2001-12-05 | 2003-06-26 | Kenji Fukunabe | Circuit board device and mounting method therefor |
| CN101714538A (en) * | 2008-10-03 | 2010-05-26 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| WO2011002086A1 (en) * | 2009-07-03 | 2011-01-06 | 株式会社カネカ | Crystalline silicon type solar cell and process for manufacture thereof |
| CN102254836A (en) * | 2010-03-26 | 2011-11-23 | 精工电子有限公司 | Manufacturing method of electronic device package, electronic device package, and oscillator |
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2012
- 2012-01-16 CN CN2012100128542A patent/CN102655125A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02246117A (en) * | 1989-03-17 | 1990-10-01 | Mitsubishi Electric Corp | Formation of thin film |
| US20030117784A1 (en) * | 2001-12-05 | 2003-06-26 | Kenji Fukunabe | Circuit board device and mounting method therefor |
| CN101714538A (en) * | 2008-10-03 | 2010-05-26 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| WO2011002086A1 (en) * | 2009-07-03 | 2011-01-06 | 株式会社カネカ | Crystalline silicon type solar cell and process for manufacture thereof |
| CN102254836A (en) * | 2010-03-26 | 2011-11-23 | 精工电子有限公司 | Manufacturing method of electronic device package, electronic device package, and oscillator |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102015104570B4 (en) | 2015-03-26 | 2019-07-11 | Infineon Technologies Ag | POWER CHIP AND CHIP ASSEMBLY |
| CN111555112A (en) * | 2020-05-21 | 2020-08-18 | 常州纵慧芯光半导体科技有限公司 | Light-emitting device, manufacturing method thereof and laser equipment |
| CN113140541A (en) * | 2021-03-31 | 2021-07-20 | 成都芯源系统有限公司 | Integrated circuit unit and wafer with integrated circuit unit |
| CN113140541B (en) * | 2021-03-31 | 2023-09-05 | 成都芯源系统有限公司 | Integrated circuit unit and wafer with integrated circuit unit |
| CN113866860A (en) * | 2021-09-22 | 2021-12-31 | 华天慧创科技（西安）有限公司 | Ultrathin wafer optical narrowband filter and preparation method thereof |
| CN113866860B (en) * | 2021-09-22 | 2024-01-12 | 华天慧创科技（西安）有限公司 | Ultrathin wafer optical narrowband optical filter and preparation method thereof |
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Application publication date: 20120905 |