CN102651318A - High-voltage transistor manufacturing method - Google Patents
High-voltage transistor manufacturing method Download PDFInfo
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- CN102651318A CN102651318A CN2011100432374A CN201110043237A CN102651318A CN 102651318 A CN102651318 A CN 102651318A CN 2011100432374 A CN2011100432374 A CN 2011100432374A CN 201110043237 A CN201110043237 A CN 201110043237A CN 102651318 A CN102651318 A CN 102651318A
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Abstract
The invention discloses a high-voltage transistor manufacturing method, which includes the following steps: providing a substrate; providing a P-type epitaxial layer, or P-epilayer on the substrate; forming an N-Well in the P-type epitaxial layer; forming a P-Well in the P-type epitaxial layer; forming a plurality of FOX layers on the P-type epitaxial layer; forming a GOX layer between the FOX layers; and injecting a P-type implant in the P-Well or injecting an N-type implant in the N-Well, so as to adjust the electric property function of the high-voltage transistor.
Description
Technical field
The invention relates to a kind of transistorized manufacturing approach, and particularly relevant for a kind of manufacturing approach of high voltage transistor.
Background technology
Along with the semiconductor development of science and technology, develop and a kind of high voltage transistor.High voltage transistor is the deep trap that on substrate, forms dopant ion, and transistor then is arranged in this deep trap, to create higher reference withstand voltage (being called breakdown voltage or puncture voltage again).
In many application, the designer must see through various process meanses, and to increase the reference of high voltage transistor withstand voltage.Yet will increase the reference of high voltage transistor withstand voltage is a quite very difficult thing.Often under various factors, substrate current of high voltage transistor (Isub) and specific on-resistance (Ronsp) can't obtain stable result.
In addition, high voltage transistor also often suffers from the problem of Ke Erke effect (Kirk ' s effect).When the Ke Erke effect was meant the transistor drain electric current increased progressively, the blocking frequency will be successively decreased.It is owing to inject the carrier of volume, and the vague and general layer width that drain electrode, source electrode engage increases stenosis and produce false source width.
Above-mentioned various phenomenons are the technical great bottleneck that suffers from of present high voltage transistor, and therefore how developing new technology improves above-mentioned various phenomenon, and real is an important goal of present semiconductor industry research and development.
Summary of the invention
The invention relates to a kind of manufacturing approach of high voltage transistor; It see through to inject p type impurity (P-type implant) in P type trap (P-Well) or inject N type impurity (N-type implant) in the design of the step of N type trap (N-Well), makes that injecting the result can keep stable.Further can improve the wild effect of substrate current (Isub) and specific on-resistance (Ronsp), and improve Ke Erke effect (Kirk ' s effect).In addition, more see through the design of sharing mask, significantly reduced manufacturing cost.
A kind of manufacturing approach of high voltage transistor is proposed according to an aspect of the present invention.The manufacturing approach of high voltage transistor may further comprise the steps.One substrate is provided.Provide a P type epitaxial loayer (P-type epitaxiallayer, P-epi layer) on this substrate.Form a N type trap in P type epitaxial loayer.Form a P type trap in P type epitaxial loayer.Form a plurality of field oxides (Field oxide layer, FOX layer) on P type epitaxial loayer.Form a grid oxic horizon (Gate oxide layer, GOX layer) between these a little field oxides.Inject p type impurity in P type trap, with the electrical functionality of adjustment high voltage transistor.
A kind of manufacturing approach of high voltage transistor is proposed according to a further aspect in the invention.The manufacturing approach of high voltage transistor may further comprise the steps.One substrate is provided.Provide a P type epitaxial loayer (P-epi layer) on substrate.Form a N type trap in P type epitaxial loayer.Form a P type trap in P type epitaxial loayer.Form a plurality of field oxides (FOX layer) on P type epitaxial loayer.Form a grid oxic horizon (GOX layer) between these a little field oxides.Inject N type impurity (N-type implant) in N type trap, with the electrical functionality of adjustment high voltage transistor.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts various embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Figure 1A～Figure 1B illustrates the flow chart of manufacturing approach of the N type high voltage transistor of first embodiment.
Fig. 2 A～Fig. 2 C illustrates the sketch map of each step of Figure 1A～Figure 1B.
Fig. 3 illustrates specific on-resistance (Ronsp) curve chart of the N type high voltage transistor of first embodiment.
Fig. 4 A～Fig. 4 B illustrates the flow chart of manufacturing approach of the P type high voltage transistor of second embodiment.
Fig. 5 A～Fig. 5 C illustrates the sketch map of each step of Fig. 4 A～Fig. 4 B.
Fig. 6 illustrates the specific on-resistance curve chart of the P type high voltage transistor of second embodiment.
[main element symbol description]
S101～S114, S201～S214: process step
100P, 200P: high voltage transistor
110,210: substrate
120N, 220N:N type buried horizon (NBL)
130P, 230P:P type bottom (P-CO layer)
140P, 240P:P type epitaxial loayer (P-epi layer)
150N, 250N:N type trap (N-Well)
150P, 250P:P type trap (P-Well)
160F, 260F: field oxide (FOX layer)
160G, 260G: grid oxic horizon (GOX layer)
160P, 260P:P type field layer (P-field layer)
170P, 270P:P type impurity (P-type implant)
181N: a N type doped region (N+region)
182N: the 2nd N type doped region (N+region)
181P: a P type doped region (P+region)
190D, 290D: drain electrode (Drain electrode)
190G, 290G: gate electrode (Gate electrode)
190S, 290S: source electrode (Source electrode)
283N: the 3rd N type doped region (N+region)
282P: the 2nd P type doped region (P+region)
283P: the 3rd P type doped region (P+region)
NEW1, NEW2, OLD1, OLD2: specific on-resistance (Ronsp) curve
Embodiment
Embodiments of the invention will be illustrated and be shown in the accompanying drawing, and the example should be interpreted into and cooperate some embodiment adjustment, and is not to be like this in other embodiment about each instance.Implement in appearance attitude at some, in the accompanying drawings with specification in employed similar or identical reference numeral represent identical, similar or similar element and/or element, and should not be like this according to the identical usage of other embodiment.According to some embodiment; The direction term (for example; Upper and lower, left and right, rising, decline, up, in the above, below, below, in the back with in front) use should be by literalization, and should not be like this in the same usage of other embodiment.The present invention possibly cooperate various integrated circuit manufacturings and other technology to realize, and for needs provide understanding of the present invention, only comprises processing step partly in this.The present invention generally has the applicability in the field of semiconductor device and technology.Yet for illustrative purposes, following explanation is the manufacturing approach about high voltage transistor.
In addition, embodiment is only in order to as example explanation, scope that can't limit desire protection of the present invention.Moreover graphic among the embodiment is to omit unnecessary element, shows technical characterstic of the present invention with clear.
Following examples see through to be injected p type impurity (P-type implant) in P type trap (P-well) or inject N type impurity (N-type implant) in the design of the step of N type trap (N-well), make that injecting the result can keep stable.Further can improve the wild effect of substrate current (Isub) and specific on-resistance (Ronsp), and improve Ke Erke effect (Kirk ' s effect).In addition, more see through the design of sharing mask, significantly reduced manufacturing cost.
Wherein, first embodiment adopts with N type high voltage transistor to inject be designed to routine explain of p type impurity in P type trap; Second embodiment then adopts with P type high voltage transistor and injects be designed to routine explain of p type impurity in P type trap.Yet first embodiment and second embodiment also can change employing and inject N type impurity in the design of N type trap.
First embodiment
Please with reference to Figure 1A～Figure 1B and Fig. 2 A～Fig. 2 C, Figure 1A～Figure 1B illustrates the flow chart of manufacturing approach of the N type high voltage transistor 100N of first embodiment, and Fig. 2 A～Fig. 2 C illustrates the sketch map of each step of Figure 1A～Figure 1B.
At first, in step S101, shown in Fig. 2 A, a substrate 110 is provided, substrate 110 for example is (but being not limited to) P type substrate.
Then, in step S102, shown in Fig. 2 A, (N-buriedlayer, NBL) 120N is in the surface of substrate 110 to form a N type buried horizon.The position that N type buried horizon 120N is provided with is looked following the P type trap 150P that step institute desire forms and decide, and generally speaking, the scope that N type buried horizon 120N is provided with will surpass the scope of the position that P type trap 150P presets.N type buried horizon 120N can provide between P type trap 150P and following P type epitaxial loayer (P-type epitaxial layer, the P-epi layer) 140P has the good insulation performance characteristic.In one embodiment, the step that forms N type buried horizon 120N also can be omitted, or replaces with other technology.
Then, in step S103, shown in Fig. 2 A, form P type bottom (P-CO layer) 130P on the surface and N type buried horizon (NBL) 120N of substrate 110.In one embodiment, the step that forms P type bottom 130P also can be omitted, or replaces with other technology.
Then, in step S104, shown in Fig. 2 A, provide P type epitaxial loayer (P-epilayer) 140P on substrate 110.
Then, in step S105, shown in Fig. 2 A, form N type trap (N-well) 150N in P type epitaxial loayer (P-epi layer) 140P.This step is after carrying out exposure imaging technology through particular mask, to form a patterning photoresist layer, and carry out ion implantation technology, and form N type trap 150N.
Then, in step S106, shown in Fig. 2 A, form P type trap (P-well) 150P in P type epitaxial loayer (P-epi layer) 140P.This step is after carrying out exposure imaging technology through particular mask, to form a patterning photoresist layer, and carry out ion implantation technology, and form P type trap 150P.
Shown in Fig. 2 A, N type buried horizon (NBL) 120N is arranged at the below of P type trap (P-well) 150P, so that P type trap 150P good insulation performance characteristic to be provided.
Then, in step S107, shown in Fig. 2 B, form a plurality of P types field layer (P-field layer) 160P.These a little P types field layer 160P is formed on the predetermined position that forms of following field oxide (FOX layer) 160F.In one embodiment, the step of formation P type field layer 160P can also be omitted or replace with other technology.
Then, in step S108, shown in Fig. 2 B, form a plurality of field oxides (FOX layer) 160F on P type epitaxial loayer (P-epi layer) 140P.In this step, be to form field oxide 160F with thermal process.
Then, in step S109, shown in Fig. 2 B, form a grid oxic horizon (GOX layer) 160G between these a little field oxides (FOX layer) 160F.In this step, be to form field oxide 160G with thermal process.In one embodiment, grid oxic horizon 160G can only be formed between these a little field oxide 160F; In one embodiment, grid oxic horizon 160G can be formed on above-mentioned each layer structure by whole face.
Then, in step S110, shown in Fig. 2 B～Fig. 2 C, inject p type impurity (P-typeimplant) 170P, with the electrical functionality of adjustment high voltage transistor 100N in P type trap (P-well) 150P.This step is after carrying out exposure imaging technology through particular mask, to form a patterning photoresist layer, injects the technology of p type impurity 170P again.In one embodiment, inject p type impurity 170P and can adopt same mask with the step S106 that forms P type trap 150P in the step S110 of P type trap 150P.Thus, needn't be extra the expensive mask expense of increase, will significantly reduce manufacturing cost.
In addition, inject p type impurity (P-type implant) 170P in the step S110 of P type trap (P-well) 150P be executed in the step S108 that forms these a little field oxides (FOX layer) 160F and form the step S109 of these a little grid oxic horizons (GOX layer) 160G after.Thus, the thermal process that step S109 carried out that can avoid forming the step S108 of these a little field oxide 160F and form these a little grid oxic horizon 160G influences the result that p type impurity 170P injects.
In one embodiment, this step also can change to adopt injects N type impurity (N-type implant) (not illustrating) in the mode of N type trap (N-well) 150N, adjusts the electrical functionality of high voltage transistor 100N.
Then, in step S111, shown in Fig. 2 C, form one the one N type doped region (N+region) 181N in N type trap (N-well) 150N.
Then, in step S112, shown in Fig. 2 C, form one the 2nd N type doped region (N+region) 182N in P type trap (P-well) 150P.
Then, in step S113, shown in Fig. 2 C, form one the one P type doped region (P+region) 181P in P type trap (P-well) 150N, the 2nd N type doped region 182N is between the first N type doped region 181N and a P type doped region 181P.
Then, in step S114, shown in Fig. 2 C, form a gate electrode (Gate electrode) 190G, one source pole electrode (Source electrode) 190S and a drain electrode (Drain electrode) 190D.Gate electrode 190G is between source electrode 190S and drain electrode 190D.Source electrode 190S electrically connects the 2nd a N type doped region 182N and a P type doped region 181P, and drain electrode 190D electrically connects a N type doped region 181N.
Thus, promptly accomplish the N type high voltage transistor 100N of present embodiment.The N type high voltage transistor 100N of present embodiment will inject p type impurity (P-type implant) 170P after the step S110 of P type trap (P-well) 150P is arranged in the step S108 that forms these a little field oxides (FOX layer) 160F and forms the step S109 of these a little grid oxic horizons (GOX layer) 160G, make the injection result of p type impurity 170P can keep stable.Please with reference to Fig. 3, it illustrates specific on-resistance (Ronsp) curve chart of the N type high voltage transistor 100N of first embodiment.The specific on-resistance curve N EW1 that can find out present embodiment from the left side of Fig. 3 is improved in the wild effect of substrate current (Isub) and specific on-resistance compared to known specific on-resistance curve OLD1.The specific on-resistance curve N EW1 that can find out present embodiment from the right side of Fig. 3 has also obtained improvement compared to known specific on-resistance curve OLD1 in the phenomenon of Ke Erke effect (Kirk ' s effect).
In addition, adopt same mask in the step S110 of P type trap (P-well) 150P with the step S106 that forms P type trap 150P owing to inject p type impurity (P-type implant) 170P, thus needn't the expensive mask expense of extra increase, significantly reduced manufacturing cost.
Second embodiment
Please with reference to Fig. 4 A～Fig. 4 B and Fig. 5 A～Fig. 5 C, Fig. 4 A～Fig. 4 B illustrates the flow chart of manufacturing approach of the P type high voltage transistor 200P of second embodiment, and Fig. 5 A～Fig. 5 C illustrates the sketch map of each step of Fig. 4 A～Fig. 4 B.The manufacturing approach similarity of the manufacturing approach of the P type high voltage transistor 200P of present embodiment and the N type high voltage transistor 100N of first embodiment is repeated description no longer.
At first; After step S201～S209 carries out; Shown in Fig. 5 A～Fig. 5 B, elements such as substrate 210, N type buried horizon (NBL) 220N, P type bottom (P-CO layer) 230P, P type epitaxial loayer (P-epi layer) 240P, P type trap (P-well) 250P, N type trap (N-well) 250N, P type field layer 260P (P-field layer), field oxide (FOX layer) 260F, grid oxic horizon (GOX layer) 260G have been formed.
Then, in step S210, shown in Fig. 5 B, inject p type impurity (P-type implant) 270P, with the electrical functionality of adjustment high voltage transistor 200P in P type trap (P-well) 250P.This step is after carrying out exposure imaging technology through particular mask, to form a patterning photoresist layer, injects the technology of p type impurity 270P again.In one embodiment, inject p type impurity 270P and can adopt same mask with the step S206 that forms P type trap 250P in the step S210 of P type trap 250P.Thus, needn't be extra the expensive mask expense of increase, will significantly reduce manufacturing cost.
In addition, inject p type impurity (P-type implant) 270P in the step S210 of P type trap (P-well) 250P be executed in the step S208 that forms these a little field oxides (FOX layer) 260F and form the step S209 of these a little grid oxic horizons (GOX layer) 260G after.Thus, the thermal process that step S209 carried out that can avoid forming the step S208 of these a little field oxide 260F and form these a little grid oxic horizon 260G influences the result that p type impurity 270P injects.
In one embodiment, this step also can change to adopt injects N type impurity (N-type implant) (not illustrating) in the mode of N type trap (N-well) 250N, adjusts the electrical functionality of high voltage transistor 200P.
Then, in step S211, shown in Fig. 5 C, form one the 2nd P type doped region (P+region) 282P in P type trap (P-well) 250P.
Then, in step S212, shown in Fig. 5 C, form one the 3rd P type doped region (P+region) 283P in N type trap (N-well) 250N.
Then, in step S213, shown in Fig. 5 C, form one the 3rd N type doped region (N+region) 283N in N type trap (N-well) 250N, the 3rd P type doped region 280P is between the 2nd P type doped region 282P and the 3rd N type doped region 283N.
Then, in step S214, shown in Fig. 5 C, form a gate electrode (Gate electrode) 290G, one source pole electrode (Source electrode) 290S and a drain electrode (Drain electrode) 290D.Gate electrode 290G is between source electrode 290S and drain electrode 290D.Source electrode 290S electrically connects the 3rd N type doped region (N+region) 283N and the 3rd P type doped region 283P, and drain electrode 290D electrically connects the 3rd N type doped region 283N.
Thus, promptly accomplish the P type high voltage transistor 200P of present embodiment.The P type high voltage transistor 200P of present embodiment will inject p type impurity (P-type implant) 270P after the step S210 of P type trap (P-well) 250P is arranged in the step S208 that forms these a little field oxides (FOX layer) 260F and forms the step S209 of these a little grid oxic horizons (GOX layer) 260G, make the injection result of p type impurity (P-type implant) 270P can keep stable.Please with reference to Fig. 6, it illustrates specific on-resistance (Ronsp) curve chart of the P type high voltage transistor 200P of second embodiment.The specific on-resistance curve N EW2 that can find out present embodiment from the left side of Fig. 6 is improved in the wild effect of substrate current (Isub) and specific on-resistance compared to known specific on-resistance curve OLD2.
In addition, adopt same mask in the step S210 of P type trap (P-well) 250P with the step S206 that forms P type trap 250P owing to inject p type impurity (P-type implant) 270P, thus needn't the expensive mask expense of extra increase, significantly reduced manufacturing cost.
In sum, though the present invention discloses as above with various embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defined.
Claims (10)
1. the manufacturing approach of a high voltage transistor comprises:
One substrate is provided;
Provide a P type epitaxial loayer (P-type epitaxial layer, P-epi layer) on this substrate;
Form a N type trap (N-Well) in this P type epitaxial loayer;
Form a P type trap (P-Well) in this P type epitaxial loayer;
Form a plurality of field oxides (Field oxide layer, FOX layer) on this P type epitaxial loayer;
Form a grid oxic horizon (Gate oxide layer, GOX layer) between these a plurality of field oxides;
Inject p type impurity (P-type implant) in this P type trap, to adjust the electrical functionality of this high voltage transistor.
2. the manufacturing approach of high voltage transistor according to claim 1, wherein this injection p type impurity in the step of this P type trap be executed in the step that forms these a plurality of field oxides after.
3. the manufacturing approach of high voltage transistor according to claim 1, wherein this injection p type impurity in the step of this P type trap be executed in the step that forms this grid oxic horizon after.
4. the manufacturing approach of high voltage transistor according to claim 1 is wherein injected p type impurity and is adopted same mask in the step of this P type trap with the step that forms this P type trap.
5. the manufacturing approach of high voltage transistor according to claim 1, before the step that this P type epitaxial loayer is provided, this manufacturing approach more comprises:
(N-buried layer, NBL) in the surface of this substrate, this N type buried horizon is positioned at the preset position of this P type trap to form a N type buried horizon.
6. the manufacturing approach of high voltage transistor according to claim 5, wherein after the step that forms this N type buried horizon, this manufacturing approach more comprises:
Form a P type bottom (P-CO layer) on the surface and this N type buried horizon of this substrate.
7. the manufacturing approach of high voltage transistor according to claim 1, wherein form the step of these a plurality of field oxides before, this manufacturing approach more comprises:
Form a plurality of P types field layer (P-field layer) in the predetermined position that forms of these a plurality of field oxides.
8. the manufacturing approach of high voltage transistor according to claim 1 more comprises:
Form one the one N type doped region (N+region) in this N type trap;
Form one the 2nd N type doped region in this P type trap; And
Form one the one P type doped region (P+region) in this P type trap, the 2nd N type doped region is between a N type doped region and a P type doped region.
9. the manufacturing approach of high voltage transistor according to claim 1 more comprises:
Form one the 2nd P type doped region in this P type trap;
Form one the 3rd P type doped region in this N type trap; And
Form one the 3rd N type doped region in this N type trap, the 3rd P type doped region is between the 2nd P type doped region and the 3rd N type doped region.
10. the manufacturing approach of a high voltage transistor comprises:
One substrate is provided;
Provide a P type epitaxial loayer (P-epi layer) on this substrate;
Form a N type trap (N-Well) in this P type epitaxial loayer;
Form a P type trap (P-Well) in this P type epitaxial loayer;
Form a plurality of field oxides (FOX layer) on this P type epitaxial loayer;
Form a grid oxic horizon (GOX layer) between these a plurality of field oxides;
Inject N type impurity (N-type implant) in this N type trap, to adjust the electrical functionality of this high voltage transistor.
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| CN101656215A (en) * | 2008-10-23 | 2010-02-24 | 杭州矽力杰半导体技术有限公司 | Laterally double diffused metal oxide semiconductor transistor and manufacturing method thereof |
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| JPH11266018A (en) * | 1998-03-16 | 1999-09-28 | Toshiba Corp | Semiconductor device |
| US6424005B1 (en) * | 1998-12-03 | 2002-07-23 | Texas Instruments Incorporated | LDMOS power device with oversized dwell |
| US20050285198A1 (en) * | 2004-06-25 | 2005-12-29 | Chyh-Yih Chang | High voltage device and high voltage device for electrostatic discharge protection circuit |
| CN101162697A (en) * | 2006-10-13 | 2008-04-16 | 台湾积体电路制造股份有限公司 | Lateral power mosfet with high breakdown voltage and low on-resistance |
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Application publication date: 20120829 |