CN102650982B - LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) - Google Patents
LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) Download PDFInfo
- Publication number
- CN102650982B CN102650982B CN201210085501.5A CN201210085501A CN102650982B CN 102650982 B CN102650982 B CN 102650982B CN 201210085501 A CN201210085501 A CN 201210085501A CN 102650982 B CN102650982 B CN 102650982B
- Authority
- CN
- China
- Prior art keywords
- submodule
- module
- algorithm
- matching
- index
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention relates to an LM (Levenberg-Marquard) algorithm realizing method based on an FPGA (Field Programmable Gate Array), in particular to an FPGA realizing technology for the LM algorithm of Gaussian curve fitting, and belongs to the technical field of data processing. The LM algorithm realizing method based on the FPGA comprises the following steps of: at first, carrying out series-parallel conversion and normalization on an input serial data stream, and then carrying out an LM algorithm iterative loop, wherein the iterative loop comprises the following sub steps of: at first, calculating a fitting variable; carrying out an index search; calculating an iteration coefficient; and after calculating the iteration coefficient, synchronizing time of each parameter reaching function module through a delay sub module, and correcting the iteration coefficient through a parallel judgment sub module, so as to correct the fitting variable. With the adoption of the LM algorithm realizing method provided by the invention, the processing speed of the LM algorithm is improved. Not only can the high-precision measurement be satisfied, but also the requirements of high speed and instantaneity can be met. An algorithm module not only can calculate parameters of a linear model but also can calculate parameters of a non-linear model. Meanwhile, the LM algorithm realizing method provided by the invention has the characteristics of low power consumption, miniaturization, high speed and the like, and can be applied to the field of high-precision real-time signal processing.
Description
Technical field
The present invention relates to a kind of LM algorithm implementation method based on FPGA, particularly a kind of FPGA of the LM algorithm for gaussian curve approximation realizes technology, belongs to technical field of data processing.
Background technology
In current Measurement and Data Processing process, under the prerequisite of observed reading Normal Distribution, least-squares estimation be optimum linearity without inclined to one side estimation, thereby be widely used at Data processing.And in the time that the function model of measuring is nonlinear model, be generally to utilize Taylor's formula to be similar to nonlinear model to turn to linear model, then use least squares estimate processing.Nonlinear least square method has inclined to one side, and in the time that needs high precision solves nonlinear model shape parameter, computational solution precision is lower, and what have even can linear-apporximation, thereby the result practical value of trying to achieve is little.At this moment need to study the accurate numerical solution of nonlinear model.
Levenberg-Marquard algorithm (being often called LM algorithm for short) can calculate PARAMETERS IN THE LINEAR MODEL, can calculate again nonlinear model shape parameter, and no matter normal equation is good state, morbid state or rank defect, and this algorithm can be restrained, and result of calculation is reliable.If function model is linear and is good state, just this algorithm only needs iteration once can obtain exact solution, when wan, iteration can converge to stable solution several times.If function model is nonlinear model, just generally only need iteration can restrain several times, when initial value departs from true value time far away, can obtain optimum solution by increasing iterations.
But need repeatedly iteration just because of LM algorithm, and operand is large, and while calculating with multi-purpose computer or DSP etc., real-time is difficult to ensure, carrys out processing cost very high again with high-performance computer.Although fpga chip in speed with slightly gap of DSP, can realize parallel organization.In the FPGA device of up-to-date release, be not only integrated with abundant configurable logic block resource, also comprise DSP unit, block RAM and the high-speed serial communication unit towards computation-intensive application in a large number.Therefore select programmable logical device to carry out the development trend that digital signal processing is the world today.
Summary of the invention
The object of the invention is the defect in order to overcome above-mentioned prior art, can be in the time realizing LM algorithm not only ensure real-time but also can cost too not high, a kind of LM algorithm implementation method based on FPGA has been proposed, this module is all realized by hardware description language, can promote the travelling speed of data processing and the counting yield of stability and data, save cost of development.
The object of the invention is to be achieved through the following technical solutions.
A kind of LM algorithm implementation method based on FPGA of the present invention, its implementation platform is FPGA, employing hardware description language is realized, module is input as the externally measured data that adopt serial data stream mode, and LM algoritic module comprises following submodule: go here and there and change submodule, normalized submodule, matching variograph operator module, index calculating sub module, iteration coefficient and calculate A submodule, time delay A submodule, iteration coefficient and calculate B submodule, time delay B submodule and parallelly judge submodule, first convert the serial data stream of input to parallel data and send into normalized submodule and be normalized by going here and there and changing submodule, carry out afterwards the circulation of LM algorithm iteration, also first enter matching variograph operator module digital simulation variable, then carrying out index by index calculating sub module searches, and then calculate iteration coefficient by iteration coefficient calculating sub module, iteration coefficient utilizes time delay submodule to realize the time of synchronous parameters arrival functional module after calculating, judge that by parallel submodule revises iteration coefficient, and then correction matching variable.
Above-mentioned a kind of LM algorithm implementation method based on FPGA, its step is as follows:
1) outside this algoritic module input serial data circulation is changed to parallel data stream sends into normalization submodule by going here and there and changing submodule;
2) normalization module is to step 1) parallel data that generates sends into matching variograph operator module after being normalized;
3) matching variograph operator module is according to step 2) data digital simulation variable after normalized and the initial value of matching variable, and this matching variable and matching variable initial value are sent into index calculating sub module;
4) index calculating sub module is to step 3) matching variable carry out index and search, and index calculated value is sent into iteration coefficient calculating sub module;
5) iteration coefficient calculates A submodule to step 4) the index calculated value that produces calculates, calculates the iteration parameter of required correction in iterative process, and each iteration parameter is sent into time delay submodule;
6) utilizing time delay A submodule synchronizing step 5) each iteration parameter of producing arrives parallel time that judge submodule, and result is sent into walk abreast judge submodule;
7) judge that by parallel submodule is to through step 6) each iteration parameter of processing revises, and draws the matching variate-value X under present case
i;
8) to matching variate-value X
icalculate B submodule by iteration coefficient again and time delay B submodule is further processed matching variable;
9) will be through step 8) matching variable after treatment sends into step 3), digital simulation variable initial value, and current matching variable and matching variable initial value are sent into step 4), repeating step 4)～step 9) carry out LM algorithm iteration until reach predefined iterations or algorithm convergence.
Index look-up table in the index search procedure of above-mentioned index calculating sub module adopts staging treating mode, determine the precision of searching of each segment of curve according to index curve probability density characteristics, wherein segment of curve is more precipitous, this section to search precision higher, this mode has not only ensured that the overall precision of look-up table is constant, and has reduced the resource that look-up table takies.
Above-mentioned time delay submodule adopts shift register to realize, the result of calculation of each iteration parameter is stored in shift register, after all calculation of parameter finish, output to that next functional module is parallel judges submodule simultaneously, avoid causing due to time delay the loss of data stream, and realize the time of synchronous parameters arrival functional module;
Walk abreast and judge that first submodule judges and then adopt parallel processing mode iteration parameter, judged result for each iteration parameter is implemented the matching variable algorithm in three kinds of situations, selects the matching variate-value X under output present case according to the judged result to iteration parameter
i, the processing time of having saved algorithm.
Beneficial effect
The present invention proposes a kind of LM algorithm implementation method based on FPGA, improved the processing speed of LM algorithm, this algoritic module is applied to the fields of measurement such as Fibre Optical Sensor measurement, in meeting high-acruracy survey, can also reach the real-time demand of high speed.This algoritic module can calculate PARAMETERS IN THE LINEAR MODEL, can calculate again nonlinear model shape parameter, has the features such as low-power consumption, miniaturization, high speed simultaneously, can be applicable to the signal process field of real-time high-precision, is particularly useful for high-precision gaussian curve approximation.
Brief description of the drawings
Fig. 1 is the overall procedure block diagram of the LM algorithm implementation method based on FPGA;
Fig. 2 is the FB(flow block) of Exponential calculating sub module of the present invention;
Fig. 3 is the parallel theory diagram that judges submodule in the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.
A kind of LM algorithm implementation method based on FPGA, it is input as the externally measured data that adopt serial data stream mode, as shown in Figure 1, LM algoritic module comprises following submodule: go here and there and change submodule, normalized submodule, matching variograph operator module, index calculating sub module, iteration coefficient and calculate A submodule, time delay A submodule, iteration coefficient and calculate B submodule, time delay B submodule and parallelly judge submodule;
First convert the serial data stream of input to parallel data and send into normalized submodule and be normalized by going here and there and changing submodule, carry out afterwards the circulation of LM algorithm iteration;
In the circulation of LM algorithm iteration, first enter matching variograph operator module digital simulation variable, then carrying out index by index calculating sub module searches, and then calculate iteration coefficient by iteration coefficient calculating sub module, iteration coefficient utilizes time delay submodule to realize the time of synchronous parameters arrival functional module after calculating, judge that by parallel submodule revises iteration coefficient, and then correction matching variable.
Above-mentioned a kind of LM algorithm implementation method based on FPGA, its algorithm steps is as follows:
1) outside this algoritic module input serial data circulation is changed to parallel data stream sends into normalization submodule by going here and there and changing submodule;
2) normalization module is to step 1) parallel data that generates sends into matching variograph operator module after being normalized;
3) matching variograph operator module is according to step 2) data digital simulation variable after normalized and the initial value of matching variable, and this matching variable and matching variable initial value are sent into index calculating sub module;
4) index calculating sub module is to step 3) matching variable carry out index and search, and index calculated value is sent into iteration coefficient calculating sub module;
5) iteration coefficient calculates A submodule to step 4) the index calculated value that produces calculates, calculates the iteration parameter of required correction in iterative process, and each iteration parameter is sent into time delay submodule;
6) utilizing time delay A submodule synchronizing step 5) each iteration parameter of producing arrives parallel time that judge submodule, and result is sent into walk abreast judge submodule;
7) judge that by parallel submodule is to through step 6) each iteration parameter of processing revises, and draws the matching variate-value X under present case
i;
8) to matching variate-value X
icalculate B submodule by iteration coefficient again and time delay B submodule is further processed matching variable;
9) will be through step 8) matching variable after treatment sends into step 3), digital simulation variable initial value, and current matching variable and matching variable initial value are sent into step 4), repeating step 4)～step 9) carry out LM algorithm iteration until reach predefined iterations or algorithm convergence.
Index look-up table in the index search procedure of above-mentioned index calculating sub module adopts staging treating mode, determine the precision of searching of each segment of curve according to index curve probability density characteristics, wherein more precipitous this section of segment of curve to search precision higher, this mode has not only ensured that the overall precision of look-up table is constant, and has reduced the resource that look-up table takies.
Above-mentioned time delay submodule adopts shift register to realize, the result of calculation of each parameter is stored in shift register, after all calculation of parameter finish, output to next functional module simultaneously, avoid causing due to time delay the loss of data stream, and realize the time of synchronous parameters arrival functional module;
Walk abreast and judge that first submodule judges and then adopt parallel processing mode iteration parameter, calculate three matching variable algorithms, select the matching variate-value X under output present case according to the judged result to iteration parameter
i, the processing time of having saved algorithm.
Embodiment
The serial data stream that above-mentioned a kind of LM algorithm implementation method based on FPGA is inputted this module is processed, and goes here and there and change submodule the serial data stream of input is converted to parallel N data output Y
1, Y
2... Y
n, normalization submodule is normalized output to all data, first searches N data maximal value Y wherein
max, after normalization module, be output as (Y
1/ Y
max), (Y
2/ Y
max) ..., (Y
max/ Y
max) ..., (Y
n/ Y
max);
Obtain after normalization data, enter the circulation of LM algorithm iteration, first digital simulation variable X=(A, B, C) in matching variograph operator module, obtains matching variable initial value X
0, then by matching variable X and initial value X
0send into index calculating sub module;
The internal process structure of index calculating sub module as shown in Figure 2, comprise exponential depth calculating sub module, positive number look-up table, negative look-up table and index output sub-module, index look-up table adopts staging treating mode, according to index curve probability density characteristics, curve flat sections search the search precision of precision lower than curve abrupt segment, there is positive negative situation for the power of index, whole locating function completes by two look-up tables of positive number sum of powers negative power, and index calculating sub module realizes by following steps:
41) calculate power value for just or bear by exponential depth calculating sub module;
42) according to the positive negative signal of index calculating sub module, select positive number look-up table or negative look-up table, carry out index and search;
43) export the index calculated value after searching through index output sub-module;
The index calculated value of index calculating sub module output is input to iteration parameter and calculates A submodule, be used for calculating the parameter of required correction in iterative process, comprising damping factor, Jacobi matrix etc., this module mainly comprises matrix inversion, matrix and the column vector partial content such as multiply each other, and the each iteration parameter recycling time delay A submodule calculating is realized synchronous parameters and arrived the parallel time that judges submodule of next functional module;
Judge that by parallel submodule carries out the judgement of iteration criterion to select, walk abreast and judge submodule theory diagram as shown in Figure 3, taking calculate after iteration parameter rat as example, there are three kinds of situation: situation A according to the value that enters the rat that judges submodule, corresponding matching variable algorithm A when 0 < rat < 0.5, nu=max (nu*10,0.1); Situation B, corresponding matching variable algorithm B when 0.5 < rat < 1, nu=0; Situation C, corresponding matching variable algorithm C when rat > 1, the value of nu does not change, and the matching variate-value X of judgement output exports by output sub-module; Walk abreast and judge that first submodule judges and then adopt parallel processing mode iteration parameter, calculate A, B, tri-matching variable algorithms of C, select the matching variate-value X under output present case according to the judged result to iteration parameter
i;
By matching variate-value X
icalculate B submodule and time delay B submodule by iteration coefficient again, and then correction iteration coefficient, the matching variograph operator module entering in Fig. 1 enters secondary iterative process, judges whether to carry out next iteration, thereby complete the LM algorithm matching to matching variable according to iterations.
The above is preferred embodiment of the present invention, and the present invention should not be confined to the disclosed content of this embodiment and accompanying drawing.Every do not depart under spirit disclosed in this invention, complete equivalence or amendment, all fall into the scope of protection of the invention.
Claims (2)
1. the LM algorithm implementation method based on FPGA, its implementation platform is FPGA, employing hardware description language is realized, module is input as the externally measured data that adopt serial data stream mode, it is characterized in that, LM algoritic module comprises following submodule: go here and there and change submodule, normalized submodule, matching variograph operator module, index calculating sub module, iteration coefficient and calculate A submodule, time delay A submodule, iteration coefficient and calculate B submodule, time delay B submodule and parallelly judge submodule;
Described a kind of LM algorithm implementation method based on FPGA, its step is as follows:
1) outside this algoritic module input serial data circulation is changed to parallel data stream sends into normalized submodule by going here and there and changing submodule;
2) normalized submodule is to step 1) parallel data that generates sends into matching variograph operator module after being normalized;
3) matching variograph operator module is according to step 2) data digital simulation variable after normalized and the initial value of matching variable, and this matching variable and matching variable initial value are sent into index calculating sub module;
4) index calculating sub module is to step 3) matching variable carry out index and search, and index calculated value is sent into iteration coefficient and calculates A submodule;
5) iteration coefficient calculates A submodule to step 4) the index calculated value that produces calculates, calculates the iteration parameter of required correction in iterative process, and each iteration parameter is sent into time delay A submodule;
6) utilizing time delay A submodule synchronizing step 5) each iteration parameter of producing arrives parallel time that judge submodule, and result is sent into walk abreast judge submodule;
7) judge that by parallel submodule is to through step 6) each iteration parameter of processing revises, and draws the matching variate-value Xi under present case;
8) matching variate-value Xi is calculated to B submodule by iteration coefficient again and time delay B submodule is further processed matching variable;
9) will be through step 8) matching variable after treatment sends into step 3), digital simulation variable initial value, and current matching variable and matching variable initial value are sent into step 4), repeating step 4)～step 9) carry out LM algorithm iteration until reach predefined iterations or algorithm convergence.
2. a kind of LM algorithm implementation method based on FPGA according to claim 1, it is characterized in that, described index calculating sub module comprises exponential depth calculating sub module, positive number look-up table, negative look-up table and index output sub-module, positive number look-up table and negative look-up table all adopt staging treating mode, determine the precision of searching of each segment of curve according to index curve probability density characteristics, wherein segment of curve is more precipitous, this section to search precision higher, index calculating sub module realizes by following steps:
41) calculate power value for just or bear by exponential depth calculating sub module;
42) according to the positive negative signal of exponential depth calculating sub module, select positive number look-up table or negative look-up table, carry out index and search;
43) export the index calculated value after searching through index output sub-module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210085501.5A CN102650982B (en) | 2012-03-28 | 2012-03-28 | LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210085501.5A CN102650982B (en) | 2012-03-28 | 2012-03-28 | LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102650982A CN102650982A (en) | 2012-08-29 |
| CN102650982B true CN102650982B (en) | 2014-10-08 |
Family
ID=46692990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210085501.5A Active CN102650982B (en) | 2012-03-28 | 2012-03-28 | LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102650982B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105095774B (en) * | 2015-06-12 | 2018-03-23 | 北京京东尚科信息技术有限公司 | Data ciphering method and system |
| CN106198433B (en) * | 2016-06-27 | 2019-04-12 | 中国科学院合肥物质科学研究院 | Infrared spectroscopy method for qualitative analysis based on LM-GA algorithm |
| CN106500671B (en) * | 2016-09-22 | 2020-04-07 | 天津大学 | Method for determining sea water depth by decomposing laser radar waveform based on LM algorithm |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930573A (en) * | 2004-03-16 | 2007-03-14 | 贝克休斯公司 | Method and apparatus for chemometric estimations of fluid density, viscosity, dielectric constant, and resistivity from mechanical resonator data |
| CN101634544A (en) * | 2009-09-02 | 2010-01-27 | 郑州辰维科技有限公司 | Water turbine blade blank profile measuring and machining allowance analyzing method |
| CN101789126A (en) * | 2010-01-26 | 2010-07-28 | 北京航空航天大学 | Three-dimensional human body motion tracking method based on volume pixels |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100996897B1 (en) * | 2009-02-10 | 2010-11-29 | 전남대학교산학협력단 | correction method of Radial Distortion Based on a Line-Fitting |
-
2012
- 2012-03-28 CN CN201210085501.5A patent/CN102650982B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930573A (en) * | 2004-03-16 | 2007-03-14 | 贝克休斯公司 | Method and apparatus for chemometric estimations of fluid density, viscosity, dielectric constant, and resistivity from mechanical resonator data |
| CN101634544A (en) * | 2009-09-02 | 2010-01-27 | 郑州辰维科技有限公司 | Water turbine blade blank profile measuring and machining allowance analyzing method |
| CN101789126A (en) * | 2010-01-26 | 2010-07-28 | 北京航空航天大学 | Three-dimensional human body motion tracking method based on volume pixels |
Non-Patent Citations (2)
| Title |
|---|
| 张欣.递归神经网络的并行LM算法.《机械管理开发》.2008,第23卷(第6期),170-171页. |
| 递归神经网络的并行LM算法;张欣;《机械管理开发》;20081231;第23卷(第6期);170-171页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102650982A (en) | 2012-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Liu et al. | T-MOEA/D: MOEA/D with objective transform in multi-objective problems | |
| CN102650982B (en) | LM (Levenberg-Marquard) algorithm realizing method based on FPGA (Field Programmable Gate Array) | |
| Sun et al. | FPGA acceleration of LSTM based on data for test flight | |
| CN104993525B (en) | A kind of active distribution network coordinating and optimizing control method of meter and ZIP loads | |
| CN104111691A (en) | Photovoltaic inverter MPPT control method based on three-point comparison method | |
| CN106092156A (en) | AC servo serial communication encoder position feedback pulse frequency dividing output system and method | |
| CN105119279B (en) | A kind of distributed power source planing method and its system | |
| Wang et al. | Improved auto disturbance rejection control based on moth flame optimization for permanent magnet synchronous motor | |
| CN104182910A (en) | Correlation-associated wind power output scene construction method | |
| CN108052723B (en) | A kind of broad sense gamut flexibility variable step integration method and electromagnetical transient emulation method | |
| CN102566965B (en) | Floating-point number logarithmic operation device with flat errors | |
| CN107301266B (en) | LOC estimation method and system for lithium iron phosphate battery | |
| Zhou et al. | Backflow power optimization of DAB with gradient descent algorithm based extended-phase-shift control in EER application | |
| CN115577777B (en) | Method and device for determining device inductance energy ratio in superconducting quantum chip layout | |
| Gao et al. | The application of adaptive Kalman filter in traffic flow forecasting | |
| Song et al. | Bsc: Block-based stochastic computing to enable accurate and efficient tinyml | |
| CN113193663B (en) | Load and mutual inductance dual-parameter identification method for magnetic coupling wireless power transmission system | |
| CN104182909A (en) | Multi-core parallel successive approximation method of hydropower system optimal scheduling | |
| Ayhan et al. | Approximate fully connected neural network generation | |
| Yuanfang et al. | System design for real-time image processing based on multi-core DSP | |
| Kang et al. | Design of convolution operation accelerator based on FPGA | |
| Wang et al. | Optimization and implementation of intelligent PID controller based on FPGA | |
| Kang et al. | Hardware-friendly Activation Functions for HybridViT Models | |
| CN108390407A (en) | Distributed photovoltaic access amount computational methods, device and computer equipment | |
| CN114977302A (en) | Small signal equivalent modeling method and system for new energy grid-connected inverter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |