CN102646660B - Semiconductor packaging method - Google Patents
Semiconductor packaging method Download PDFInfo
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- CN102646660B CN102646660B CN201210127276.7A CN201210127276A CN102646660B CN 102646660 B CN102646660 B CN 102646660B CN 201210127276 A CN201210127276 A CN 201210127276A CN 102646660 B CN102646660 B CN 102646660B
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- receiving space
- conducting medium
- chip
- substrate
- optical region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention discloses a semiconductor module, a semiconductor packaging structure and a packaging method for the semiconductor packaging structure, wherein the semiconductor packaging structure comprises chips, substrates, conducting mediums and welding bumps; a plurality of metal bumps are arranged on the chips; each substrate comprises an upper surface and a lower surface which is opposite to the upper surface, the lower surface of the substrate is provided with sunk containing spaces, and the chips are contained in the containing spaces; each substrate also comprises through holes which extend from the upper surface to the lower surface and are communicated with the containing spaces; the conducting mediums are arranged at the inner walls of the containing spaces and on the lower surfaces of the substrates, and the chips are electrically connected with the conducting mediums by the metal bumps; and the welding bumps are electrically connected with the conducting mediums arranged on the lower surface of the substrates. Compared with the prior art, a transparent substrate on an optical zone is removed according to the semiconductor module, the semiconductor packaging structure and the packaging method, so that the receiving and the emitting of light are smooth, thereby improving the overall performance of the chips.
Description
Technical field
The invention belongs to field of semiconductor manufacture technology, relate in particular to a kind of method for packaging semiconductor.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that full wafer wafer is carried out cutting the technology that obtains single finished product chip after packaging and testing again, and chip size and nude film after encapsulation are in full accord.Crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic LeadlessChip Carrier) isotype, has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.
In existing Wafer level packaging, for example, be the encapsulation of sensitive chip, the Optical Region of its sensitization is often subject to the impact of the transparency carrier on it, makes the reception of light not smooth with transmitting, thereby affects the overall performance of chip.
Summary of the invention
For solving the problems of the technologies described above, the object of the present invention is to provide a kind of method for packing of above-mentioned semiconductor package.
In order to solve foregoing invention object, the invention provides a kind of method for packaging semiconductor, the method comprises the following steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, from described lower surface, form the receiving space of a plurality of depressions;
Receiving space inwall and described lower surface at described substrate form conducting medium;
Form the through hole being communicated with described receiving space;
A plurality of chips are provided, on each chip, be provided with Optical Region and a plurality of metal salient point, described chip is positioned in corresponding receiving space, and described chip is electrically connected by described metal salient point and described conducting medium, the Optical Region of described chip is in communication with the outside;
On the conducting medium of described base lower surface, form a plurality of pedestals with its electric connection.
As a further improvement on the present invention, described chip is provided with Optical Region, and described metal salient point and described Optical Region are arranged at described chip the same face.
As a further improvement on the present invention, " receiving space inwall and described lower surface at described substrate form conducting medium " specifically comprises:
On the receiving space inwall of described substrate and described lower surface, form insulating barrier, and form described conducting medium on described insulating barrier.
As a further improvement on the present invention, described method also comprises:
On described conducting medium, form welding resisting layer;
On described welding resisting layer, forming section exposes a plurality of openings of described conducting medium;
Described metal salient point and described pedestal are electrically connected by described opening and described conducting medium.
As a further improvement on the present invention, described " forming the through hole being communicated with described receiving space " specifically comprises:
From described upper surface, form a plurality of through holes that extend and be communicated with described receiving space to described lower surface, described through hole exposes described Optical Region.
Compared with prior art, the present invention has removed the transparency carrier of Optical Region on it, and the reception that makes light and transmitting smoothly, improve the overall performance of chip.
Accompanying drawing explanation
Fig. 1 is the structural representation of an embodiment of the present invention semiconductor package;
Fig. 2 is the structural representation of an embodiment of the present invention semiconductor module;
Fig. 3 is the flow chart of the method for packaging semiconductor of an embodiment of the present invention.
Embodiment
Below with reference to embodiment shown in the drawings, describe the present invention.But these execution modes do not limit the present invention, the conversion in the structure that those of ordinary skill in the art makes according to these execution modes, method or function is all included in protection scope of the present invention.
The mentioned upper surface of the present invention, lower surface without the absolute relation on locus, and be only used to the convenience described.
Shown in ginseng Fig. 1, introduce an embodiment of semiconductor package of the present invention.This encapsulating structure comprises chip 20, substrate 10, conducting medium 12, pedestal 14.Wherein, on described chip 20, be provided with Optical Region 22 and a plurality of metal salient point 21.Preferably, described Optical Region and described metal salient point are arranged at the same face of described chip.
Described substrate 10 comprise upper surface 100a and with the opposing lower surface 100b of upper surface 100a.The material of this substrate 10 can comprise silicon, glass, pottery, metal etc.The lower surface 100b of described substrate 10 is provided with the receiving space 31 of depression, described substrate 10 is also provided with the through hole 32 that extends and be communicated with this receiving space 31 to described lower surface 100b from described upper surface 100a, described chip 20 is contained in this receiving space 31, in the present embodiment, by chip 20 is arranged in the receiving space 31 of substrate 10, can reduce whole package thickness; Meanwhile, the Optical Region 22 on this chip 20 faces through hole 32 on substrate 10 and arranges, and does not need extra medium is set on the Optical Region 22 of this chip 20, makes the reception of light and transmitting smooth, improves the overall performance of chip.Preferably, in an embodiment of the present invention, the cross sectional shape of described through hole 32 is rectangle, certainly, in other modes of the present invention, this cross section also can be other difformities, as long as this through hole can expose the Optical Region on this chip, is the width that the minimum widith of described through hole 32 is more than or equal to described Optical Region.Preferably, these 22 centers, Optical Region and this through hole 32 are centered close on same axis.
Described encapsulating structure in embodiment of the present invention also includes the insulating barrier 11 being arranged on described substrate 10 lower surface 100b and described receiving space 31 inwalls, described conducting medium 12 is uniformly distributed on this insulating barrier 11, and the material of this conducting medium 12 can be selected from copper, aluminium, gold, platinum, tungsten or its combination etc.Preferably, the material of this insulating barrier 13 can be epoxy resin, anti-welding material or other applicable megohmite insulant.The generation type of this insulating barrier 13 can comprise coating method, for example, and rotary coating, spraying, or other applicable depositional mode, for example, physical vapour deposition (PVD), chemical vapour deposition (CVD).
On described conducting medium 12, be also formed with welding resisting layer 13.On welding resisting layer 13, be provided with the opening that part exposes conducting medium 12, preferably, this opening is at least formed on the welding resisting layer 13 of receiving space 31 diapires and substrate 10 lower surface 100b, by these openings, be provided with a plurality of metal salient points 21 and a plurality of pedestal 14 that are electrically connected with conducting medium 12, wherein, described metal salient point 21 is for making described chip be electrically connected described conducting medium 12, described pedestal 14 is for making external circuits plate be electrically connected described conducting medium 12, preferably, described opening can be formed at by the mode of photoetching on described welding resisting layer 13.
Shown in ginseng Fig. 2, for having adopted the semiconductor module of an embodiment of the present invention encapsulating structure as shown in Figure 1, it has comprised semiconductor encapsulating structure, a lens assembly, wherein, said lens assembly comprises lens container 41, and is fixedly installed on a plurality of camera lenses 42 in lens container 41.
Shown in ginseng Fig. 3, be an execution mode of the method for packing of semiconductor package of the present invention, the method comprises:
S1, provide a substrate 10, it comprise upper surface 100a and with the opposing lower surface 100b of upper surface 100a; From the upper receiving space 31 that forms a plurality of depressions of this lower surface 100b.
S2, at receiving space 31 inwalls of described substrate 10 and described lower surface 100b, form conducting medium 12.It is specifically included on described substrate 10 lower surface 100b and described receiving space 31 inwalls and forms insulating barrier 11, and on this insulating barrier 11, forming equally distributed conducting medium 12, the material of this conducting medium 12 can be selected from copper, aluminium, gold, platinum, tungsten or its combination etc.Preferably, the material of this insulating barrier 11 can be epoxy resin, anti-welding material or other applicable megohmite insulant.The generation type of this insulating barrier 11 can comprise coating method, for example, and rotary coating, spraying, or other applicable depositional mode, for example, physical vapour deposition (PVD), chemical vapour deposition (CVD).
In the method for present embodiment, on described insulating barrier 11, form after conducting medium 12, also comprise: on described conducting medium 12, form a welding resisting layer 13; On the welding resisting layer 13 of described base lower surface 100b and described receiving space 31 diapires, forming section exposes a plurality of openings of described conducting medium 12, and described opening can be formed at by the mode of photoetching on described welding resisting layer 13.
The through hole that S3, formation are communicated with described receiving space; Preferably, at this receiving space diapire, form a plurality of through holes 32 that extend and be communicated with receiving space 31 to upper surface 100b, in the present embodiment, this through hole can adopt etch process to make.Wherein, this through hole and described receiving space match, and are the corresponding through holes of a receiving space 31.In an embodiment of the present invention, the cross sectional shape of described through hole 32 is rectangle, certainly, in other modes of the present invention, this cross section also can be other difformities, as long as this through hole can expose the Optical Region on this chip, it is the width that the minimum widith of described through hole 32 is more than or equal to described Optical Region.Preferably, these 22 centers, Optical Region and this through hole 32 are centered close on same axis.
S4, provide a plurality of chips 20, on each chip 20, be provided with Optical Region 22 and a plurality of metal salient point 21, preferably, described Optical Region and described metal salient point are arranged at the same face of described chip, Optical Region on described chip 20 is faced to through hole 21 on substrate 10 and be positioned in corresponding receiving space, and opening and the conducting medium 12 by welding resisting layer 13 on described receiving space 31 diapires is electrically connected by this metal salient point 21 by Au Bump, to connect technique.On the Optical Region 22 of this chip 20, do not need extra medium is set, make the reception of light and transmitting smooth, improve the overall performance of chip.
S5, by the opening of described substrate 10 lower surface 100b welding resisting layers 13, form a plurality of pedestals 14 that are electrically connected with conducting medium 12, for making external circuits plate.Preferably, the pitch between described pedestal 14 is greater than the pitch between described metal salient point.
In the prior art of wafer-level packaging, completely according to the method for packing of crystal wafer chip dimension: first full wafer bare silicon wafer is cut, form single discrete bare chip, again the bare chip after cutting is again arranged on new substrate, form the more suitably new wafer of inter-chip pitch, then adopt Wafer level packaging (WLP, i.e. wafer level package), the wafer of again arranging is carried out after packaging and testing, cut into the welded ball array chip larger than original chip area.Yet, bare chip is again arranged on new substrate, process capability is had relatively high expectations (admissible error is minimum), make complex process, packaging cost is higher.And the present invention is by above-mentioned method for packing, after can first processing new substrate, then the bare chip after cutting is completed is positioned in receiving space corresponding in new substrate, to complete wafer-level packaging, finally cuts into welded ball array chip.The method can not change on the basis of original bare chip design, realizes the fan-out wafer-level packaging of different size bare chip, and lower to process capability requirement, work simplification, and the packaging cost of product is lower.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, technical scheme in each execution mode also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Listed a series of detailed description is above only illustrating for feasibility execution mode of the present invention; they are not in order to limit the scope of the invention, all disengaging within equivalent execution mode that skill spirit of the present invention does or change all should be included in protection scope of the present invention.
Claims (5)
1. a method for packaging semiconductor, is characterized in that, the method comprises the following steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, from described lower surface, form the receiving space of a plurality of depressions;
Receiving space inwall and described lower surface at described substrate form conducting medium;
Form the through hole being communicated with described receiving space;
A plurality of chips are provided, on each chip, be provided with Optical Region and a plurality of metal salient point, described chip is positioned in corresponding receiving space, and described chip is electrically connected by described metal salient point and described conducting medium, the Optical Region of described chip is in communication with the outside;
On the conducting medium of described base lower surface, form a plurality of pedestals with its electric connection.
2. method according to claim 1, is characterized in that, described metal salient point and described Optical Region are arranged at described chip the same face.
3. method according to claim 1, is characterized in that, " receiving space inwall and described lower surface at described substrate form conducting medium " specifically comprises:
On the receiving space inwall of described substrate and described lower surface, form insulating barrier, and form described conducting medium on described insulating barrier.
4. method according to claim 1, is characterized in that, described method also comprises:
On described conducting medium, form welding resisting layer;
On described welding resisting layer, forming section exposes a plurality of openings of described conducting medium;
Described metal salient point and described pedestal are electrically connected by described opening and described conducting medium.
5. method according to claim 1, is characterized in that, described " forming the through hole being communicated with described receiving space " specifically comprises:
From described upper surface, form a plurality of through holes that extend and be communicated with described receiving space to described lower surface, described through hole exposes described Optical Region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210127276.7A CN102646660B (en) | 2012-04-27 | 2012-04-27 | Semiconductor packaging method |
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| CN201210127276.7A CN102646660B (en) | 2012-04-27 | 2012-04-27 | Semiconductor packaging method |
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| CN102646660A CN102646660A (en) | 2012-08-22 |
| CN102646660B true CN102646660B (en) | 2014-11-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109729240B (en) * | 2017-10-27 | 2020-12-18 | 宁波舜宇光电信息有限公司 | Camera module, extended wiring packaging photosensitive assembly thereof and electronic equipment |
| CN111934192A (en) * | 2020-09-29 | 2020-11-13 | 常州纵慧芯光半导体科技有限公司 | Light emitting module and packaging method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459729B2 (en) * | 2006-12-29 | 2008-12-02 | Advanced Chip Engineering Technology, Inc. | Semiconductor image device package with die receiving through-hole and method of the same |
| CN102280391A (en) * | 2011-09-01 | 2011-12-14 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and formation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582435B (en) * | 2008-05-16 | 2012-03-14 | 鸿富锦精密工业（深圳）有限公司 | Packaging structure for image sensing wafer and camera module applying same |
| CN102623477A (en) * | 2012-04-20 | 2012-08-01 | 苏州晶方半导体股份有限公司 | Image sensing module, encapsulation structure and encapsulation method of encapsulation structure |
| CN202601608U (en) * | 2012-04-27 | 2012-12-12 | 苏州晶方半导体科技股份有限公司 | Semiconductor packaging structure and module thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459729B2 (en) * | 2006-12-29 | 2008-12-02 | Advanced Chip Engineering Technology, Inc. | Semiconductor image device package with die receiving through-hole and method of the same |
| CN102280391A (en) * | 2011-09-01 | 2011-12-14 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and formation method thereof |
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Effective date of registration: 20200520 Address after: 215000 room 118, building B, 133 Changyang street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Jingfang Photoelectric Technology Co., Ltd Address before: Suzhou City, Jiangsu province 215000 Industrial Park of Suzhou Bay Bridge No. 29 Lane Patentee before: China Wafer Level CSP Co.,Ltd. |
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