CN102638272A - Interpolation operation circuit - Google Patents
Interpolation operation circuit Download PDFInfo
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- CN102638272A CN102638272A CN2011100359256A CN201110035925A CN102638272A CN 102638272 A CN102638272 A CN 102638272A CN 2011100359256 A CN2011100359256 A CN 2011100359256A CN 201110035925 A CN201110035925 A CN 201110035925A CN 102638272 A CN102638272 A CN 102638272A
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- input
- multiplexer
- output
- interpolative operation
- selector channel
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Abstract
The invention discloses an interpolation operation circuit, which is suitable for receiving multiple inputs. Each input comprises a first input group and a second input group. The interpolation operation circuit comprises a first selection channel, a second selection channel and an interpolation operation unit, wherein the first selection channel is used for receiving the first input group and outputting a first input in the first input group according to a selection signal; the second selection channel is used for receiving the second input group and the first input and outputting a second input in the second input group to the first selection channel according to the selection signal; the first selection channel and the second selection channel are used for outputting a first input or a second input respectively according to the selection signal; and the interpolation operation unit is coupled with the first selection channel and the second selection channel, and is used for receiving the first input and the second input and performing interpolation operation according to the the first input and the second input so as to output an interpolation operation result.
Description
Technical field
The present invention relates to a kind of computing circuit, particularly relate to a kind of interpolative operation circuit.
Prior art
Generally speaking, in existing circuit, value can use the mode of tabling look-up to realize to the exchange of value.When the result who desires to table look-up is continuous function,, can use interpolation method to obtain the result usually for saving the size of circuit.
For example, Fig. 1 illustrates existing interpolative operation circuit, and Fig. 2 illustrates the interior slotting result that the interpolative operation circuit that uses Fig. 1 obtains.Please refer to Fig. 1 and Fig. 2, in the prior art, suppose that former input and output respectively have 256, this moment, the designer can be only with the table of comparisons (look up table) of 16 outputs, and remaining 240 output is inserted generation in 16 output results capable of using.For example, if will obtain interpolate value a, need get V
0With V
1Insert in doing; If will obtain interpolate value b, need get V
1With V
2Insert in doing.In other words, obtain interpolate value, need select its contiguous 2 points, respectively need one (n-1) select 1 multiplexer at these 2 and select, as shown in Figure 1.
Yet, in existing interpolating circuit,, cause circuit huge, and, make circuit layout difficult because coiling is many because the multiplexer use amount is many.Therefore, provide one brief and do not lose that the interpolative operation circuit of its practicality is real to have its necessity.
Summary of the invention
The present invention provides a kind of interpolative operation circuit, can reduce the coiling of multiplexer, reduces the degree of difficulty of circuit layout, and improves its occupation mode.
The present invention provides a kind of interpolative operation circuit, is suitable for receiving a plurality of inputs.Said input comprises one first input crowd and one second input crowd.The interpolative operation circuit comprises one first selector channel, one second selector channel and an interpolative operation unit.First selector channel receives the first input crowd, and selects signal, one first input among the output first input crowd according to one.Second selector channel receives the second input crowd and first input, and according to selecting signal, one second among the output second input crowd inputs to first selector channel.Wherein, first selector channel and second selector channel are exported first input or second input respectively according to selecting signal.The interpolative operation unit couples first selector channel and second selector channel, receives first input and second input, and carries out an interpolative operation in view of the above, to export an interpolative operation result.
In one embodiment of this invention, the first above-mentioned selector channel comprises one first multiplexer and one second multiplexer.First multiplexer has a plurality of inputs and an output.The input of first multiplexer receives the first input crowd.The output of first multiplexer couples second selector channel.First multiplexer is according to selecting signal in its output output first input.Second multiplexer has a first input end, one second input and an output.The first input end of second multiplexer couples the output of first multiplexer, and receives first input.Second input of second multiplexer couples second selector channel, and receives second input.The output of second multiplexer couples the interpolative operation unit.Second multiplexer is according to selecting signal to select output first input or second to input to the interpolative operation unit in its output.
In one embodiment of this invention, the second above-mentioned selector channel comprises one the 3rd multiplexer and one the 4th multiplexer.The 3rd multiplexer has a plurality of inputs and an output.The input of the 3rd multiplexer receives the second input crowd.The output of the 3rd multiplexer couples second input of second multiplexer.The 3rd multiplexer is according to selecting signal in its output output second input.The 4th multiplexer has a first input end, one second input and an output.The first input end of the 4th multiplexer couples the output of first multiplexer, and receives first input.Second input of the 4th multiplexer couples the output of the 3rd multiplexer, and receives second input.The output of the 4th multiplexer couples the interpolative operation unit.The 4th multiplexer is according to selecting signal to select output first input or second to input to the interpolative operation unit in its output.
In one embodiment of this invention, above-mentioned interpolative operation circuit receives N input.The first input crowd comprises N N/2 input in the input, and wherein N is an even number.
In one embodiment of this invention, the first above-mentioned input crowd comprises 2n-1 input in N the input, and wherein n is the positive integer that is less than or equal to N/2.
In one embodiment of this invention, the second above-mentioned input crowd comprises N N/2 input in the input.
In one embodiment of this invention, the second above-mentioned input crowd comprises 2n input in N the input.
In one embodiment of this invention, when first selector channel output first inputed to the interpolative operation unit, second selector channel output second inputed to the interpolative operation unit.When first selector channel output second inputed to the interpolative operation unit, second selector channel output first inputed to the interpolative operation unit.
Based on above-mentioned, exemplary embodiment of the present invention provide one brief and do not lose the interpolative operation circuit of its practicality, can reduce the coiling of multiplexer, reduce the degree of difficulty of circuit layout, and improve its occupation mode.
For making the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and is described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 illustrates existing interpolative operation circuit.
Fig. 2 illustrates the interior slotting result that the interpolative operation circuit that uses Fig. 1 obtains.
Fig. 3 illustrates the interpolative operation circuit of one embodiment of the invention.
Fig. 4 illustrates the interior slotting result that the interpolative operation circuit that uses Fig. 3 obtains.
The reference numeral explanation
100,300: the interpolative operation circuit
310: the first selector channels
312: the first multiplexers
314: the second multiplexers
320: the second selector channels
322: the three multiplexers
324: the four multiplexers
130,330: the interpolative operation unit
A, b: interpolate value
V
0, V
2, V
4..., V
2n-2: the first input crowd
V
1, V
3, V
5..., V
2n-1: the second input crowd
V
0, V
1, V
2..., V
M-1: the input crowd
V
i: first input
V
j: second input
OUT: output
TM1: first input end
TM2: second input
Sel [i], sel [0], sel [1], sel [2n-2]: select signal
Embodiment
Fig. 3 illustrates the interpolative operation circuit of one embodiment of the invention, and Fig. 4 illustrates the interior slotting result that the interpolative operation circuit that uses Fig. 3 obtains.Please refer to Fig. 3 and Fig. 4, in the present embodiment, interpolative operation circuit 300 comprises one first selector channel 310, one second selector channel 320 and an interpolative operation unit 330.Interpolative operation circuit 300 is suitable for receiving a plurality of inputs, so that an interpolative operation is carried out in these inputs, and the interpolative operation result who desires to try to achieve with output.
In the present embodiment, be input as example if handle N with interpolative operation circuit 300, first selector channel 310 and second selector channel 320 for example respectively receive N/2 input.Under this kind framework, compared to prior art, the interpolative operation circuit 300 of present embodiment can effectively reduce the coiling of multiplexer, reduces the degree of difficulty of circuit layout, and improves its occupation mode.
In detail, the 300 handled N input of interpolative operation circuit for example can be divided into one first input crowd and one second input crowd.At this, the first input crowd for example comprises input V
0, V
2, V
4..., V
2n-2, the second input crowd for example comprises input V
1, V
3, V
5..., V
2n-1In the present embodiment, N is an even number, and n is the positive integer that is less than or equal to N/2.In other words, the first input crowd comprises this N the odd number input in the input, and the second input crowd comprises this N the even number input in the input.
In the present embodiment, first selector channel 310 receives the first input crowd V
0, V
2, V
4..., V
2n-2, and according to a selection signal sel [i], one first input V among the output first input crowd
iTo second selector channel 320.Second selector channel 320 receives the second input crowd V
1, V
3, V
5..., V
2n-1, and according to selecting signal sel [i], one second input V among the output second input crowd
jTo first selector channel 310.Then, first selector channel 310 and second selector channel 320 are exported the first input V respectively again according to selecting signal sel [i]
iOr second the input V
jTo interpolative operation unit 330.Continue it, be coupled to the interpolative operation unit 330 of first selector channel 310 and second selector channel 320, it receives the first input V
iReach the second input V
j, and carry out an interpolative operation in view of the above, to export an interpolative operation result.
In the present embodiment, as first selector channel, 310 outputs, the first input V
iDuring to interpolative operation unit 330, second selector channel, 320 outputs, the second input V
jTo interpolative operation unit 330.Otherwise, as first selector channel, 310 outputs, the second input V
jDuring to interpolative operation unit 330, second selector channel, 320 outputs, the first input V
iTo interpolative operation unit 330.In other words, first selector channel 310 of present embodiment and second selector channel 320 can not exported the identical interpolative operation unit 330 that inputs to simultaneously.
Furthermore, in the present embodiment, first selector channel 310 comprises one first multiplexer 312 and one second multiplexer 314.First multiplexer 312 has a plurality of inputs and an output OUT.The input of first multiplexer 312 receives the first input crowd V respectively
0, V
2, V
4..., V
2n-2The output OUT of first multiplexer 312 couples second selector channel 320 and second multiplexer 314.First multiplexer 312 is according to selecting signal sel [i] in its output OUT output first input V
iTo second selector channel 320 and second multiplexer 314.
Second multiplexer 314 has a first input end TM1, one second input TM2 and an output OUT.The first input end TM1 of second multiplexer 320 couples the output OUT of first multiplexer 310, and receives the first input V
iThe second input TM2 of second multiplexer 314 couples second selector channel 320, and receives the second input V
jThe output OUT of second multiplexer 314 couples interpolative operation unit 330.Second multiplexer 314 is according to selecting signal sel [i] to select the output first input V in its output OUT
iOr second the input V
jTo interpolative operation unit 330.
On the other hand, in the present embodiment, second selector channel 320 comprises one the 3rd multiplexer 322 and one the 4th multiplexer 324.The 3rd multiplexer 322 has a plurality of inputs and an output OUT.The input of the 3rd multiplexer 322 receives the second input crowd V respectively
1, V
3, V
5..., V
2n-1The output OUT of the 3rd multiplexer 322 couples the second input TM2 and the 4th multiplexer 324 of second multiplexer 314.The 3rd multiplexer 322 is according to selecting signal sel [i] in its output OUT output second input V
jTo second multiplexer 312 and the 4th multiplexer 324.
The 4th multiplexer 324 has a first input end TM1, one second input TM2 and an output OUT.The first input end TM1 of the 4th multiplexer 324 couples the output OUT of first multiplexer 312, and receives the first input V
iThe second input TM2 of the 4th multiplexer 324 couples the output OUT of the 3rd multiplexer 322, and receives the second input V
jThe output OUT of the 4th multiplexer 324 couples interpolative operation unit 330.The 4th multiplexer 324 is according to selecting signal sel [i] to select the output first input V in its output OUT
iOr second the input V
jTo interpolative operation unit 330.
For example, if will obtain interpolate value a, need get V
0With V
1Insert in doing, at this moment V
0Can be selected by first multiplexer 312 at sel [0]=1 o'clock, and export second multiplexer 314 and the 4th multiplexer 324, V to
1Can or be selected by the 3rd multiplexer 322 in sel [1]=1 o'clock at sel [0]=1, and export second multiplexer 314 and the 4th multiplexer 324 to.That is to say that interpolative operation circuit 300 is earlier no matter the point of selecting is the left side or the right, but the judgement each point is selected under which kind of situation earlier.That is, V
0Can be selected V at sel [0]=1 o'clock
1Can or be selected V at sel [1]=1 o'clock at sel [0]=1
2Can or be selected in sel [2]=1 o'clock at sel [1]=1.
Then, interpolative operation circuit 300 is distinguished this on the left side of what person again, what person this on the right.With interpolate value a is example, V
0The left side point that belongs to interpolate value a, V
1The right point that belongs to interpolate value a.Therefore, V
0Can be selected as left side point by second multiplexer 314 at sel [0]=1 o'clock, promptly this moment second, multiplexer 314 was selected the output first input V
iTo interpolative operation unit 330.And V
1Can be selected as the right point by the 4th multiplexer 324 at sel [0]=1 o'clock, promptly this moment the 4th, multiplexer 324 was selected the output second input V
jTo interpolative operation unit 330.Afterwards, interpolative operation unit 330 receives the first input V
0Reach the second input V
1, and carry out an interpolative operation in view of the above, with output interpolate value a.
On the other hand, if will obtain interpolate value b, need get V
1With V
2Insert in doing, at this moment V
2Can be selected by first multiplexer 312 at sel [1]=1 o'clock, and export second multiplexer 314 and the 4th multiplexer 324, V to
1Can or be selected by the 3rd multiplexer 322 in sel [2]=1 o'clock at sel [1]=1, and export second multiplexer 314 and the 4th multiplexer 324 to.
Then, interpolative operation circuit 300 is distinguished V again
1The left side point that belongs to interpolate value b, V
2The right point that belongs to interpolate value b.Therefore, V
1Can be selected as left side point by second multiplexer 314 at sel [1]=1 o'clock, promptly this moment second, multiplexer 314 was selected the output second input V
jTo interpolative operation unit 330.And V
2Can be selected as the right point by the 4th multiplexer 324 at sel [1]=1 o'clock, promptly this moment the 4th, multiplexer 324 was selected the output first input V
iTo interpolative operation unit 330.Afterwards, interpolative operation unit 330 receives the second input V
1Reach the first input V
2, and carry out an interpolative operation in view of the above, with output interpolate value b.
In other words, first multiplexer 312 was at sel [0]=1 o'clock output V
0As the first input V
i, at sel [1]=1 or sel [2]=1 o'clock output V
2As the first input V
i..., at sel [2n-3]=1 or sel [2n-2]=1 o'clock output V
2n-2As the first input V
iSecond multiplexer 314 sel [0]=1, sel [2]=1 ... or output in sel [2n-2]=1 o'clock first input V
iAs the left side point of interpolate value, sel [1]=1, sel [3]=1 ... or output in sel [2n-3]=1 o'clock second input V
jLeft side point as interpolate value.
The 3rd multiplexer 322 is at sel [0]=1 or sel [1]=1 o'clock output V
1As the second input V
j..., at sel [2n-3]=1 or sel [2n-2]=1 o'clock output V
2n-3As the second input V
j, at sel [2n-2]=1 o'clock output V
2n-1As the second input V
jThe 4th multiplexer 324 sel [0]=1, sel [2]=1 ... or output in sel [2n-2]=1 o'clock second input V
jAs the right point of interpolate value, sel [1]=1, sel [3]=1 ... or output in sel [2n-3]=1 o'clock first input V
iThe right point as interpolate value.
It should be noted that in the present embodiment, the left side point of so-called interpolate value and the right point only are that the direction with reference to annexed drawings illustrates, and are not to be used for limiting the present invention.In addition, the interpolative operation circuit of present embodiment for example can be applicable to gamma (gamma) circuit of image processor.The handled input of interpolative operation circuit for example can be GTG value, color-values or brightness value etc.
In sum, the interpolative operation circuit that exemplary embodiment of the present invention provided can reduce the coiling of multiplexer, and avoids causing circuit huge, with the degree of difficulty of reduction circuit layout, and improves its occupation mode.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; Can do some changes and retouching, so protection scope of the present invention is to be as the criterion with claim of the present invention.
Claims (8)
1. an interpolative operation circuit is suitable for receiving a plurality of inputs, and wherein these inputs comprise one first input crowd and one second input crowd, and this interpolative operation circuit comprises:
One first selector channel receives this first input crowd, and according to a selection signal, exports one first input among this first input crowd;
One second selector channel; Receive this second input crowd and this first input; And according to this selection signal; Export one second among this second input crowd and input to this first selector channel, wherein signal is selected according to this in this first selector channel and this second selector channel, exports this first input or this second input respectively; And
One interpolative operation unit couples this first selector channel and this second selector channel, receives this first input and this second input, and carries out an interpolative operation in view of the above, to export an interpolative operation result.
2. interpolative operation circuit as claimed in claim 1, wherein this first selector channel comprises:
One first multiplexer; Have a plurality of inputs and an output; These inputs of this first multiplexer receive this first input crowd, and this output of this first multiplexer couples this second selector channel, and this first multiplexer selects signal in this first input of its output output according to this; And
One second multiplexer; Have a first input end, one second input and an output; This first input end of this second multiplexer couples this output of this first multiplexer; And receiving this first input, this second input of this second multiplexer couples this second selector channel, and receives this second input; This output of this second multiplexer couples this interpolative operation unit, and this second multiplexer selects this first input of output or this second to input to this interpolative operation unit according to this selection signal in its output.
3. interpolative operation circuit as claimed in claim 2, wherein this second selector channel comprises:
One the 3rd multiplexer; Have a plurality of inputs and an output; These inputs of the 3rd multiplexer receive this second input crowd; This output of the 3rd multiplexer couples this second input of this second multiplexer, and the 3rd multiplexer selects signal in this second input of its output output according to this; And
One the 4th multiplexer; Have a first input end, one second input and an output; This first input end of the 4th multiplexer couples this output of this first multiplexer; And receiving this first input, this second input of the 4th multiplexer couples this output of the 3rd multiplexer, and receives this second input; This output of the 4th multiplexer couples this interpolative operation unit, and the 4th multiplexer selects this first input of output or this second to input to this interpolative operation unit according to this selection signal in its output.
4. interpolative operation circuit as claimed in claim 1, wherein this interpolative operation circuit receives N input, and this first input crowd comprises this N N/2 input in the input, and wherein N is an even number.
5. interpolative operation circuit as claimed in claim 4, wherein this first input crowd comprises 2n-1 input in this N the input, wherein n is the positive integer that is less than or equal to N.
6. interpolative operation circuit as claimed in claim 4, wherein this second input crowd comprises this N N/2 input in the input.
7. interpolative operation circuit as claimed in claim 6, wherein this second input crowd comprises 2n input in this N the input.
8. interpolative operation circuit as claimed in claim 1; Wherein when the output of this first selector channel this first when inputing to this interpolative operation unit; This second inputs to this interpolative operation unit the output of this second selector channel; And when the output of this first selector channel this second when inputing to this interpolative operation unit, this first inputs to this interpolative operation unit this second selector channel output.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100359256A CN102638272A (en) | 2011-02-11 | 2011-02-11 | Interpolation operation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100359256A CN102638272A (en) | 2011-02-11 | 2011-02-11 | Interpolation operation circuit |
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|---|---|
| CN102638272A true CN102638272A (en) | 2012-08-15 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030055853A1 (en) * | 2001-06-02 | 2003-03-20 | Fowler Thomas L. | Transparent data access and interpolation apparatus and method therefor |
| CN1822581A (en) * | 2005-10-04 | 2006-08-23 | 威盛电子股份有限公司 | Interpose module,interposer and its method |
-
2011
- 2011-02-11 CN CN2011100359256A patent/CN102638272A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030055853A1 (en) * | 2001-06-02 | 2003-03-20 | Fowler Thomas L. | Transparent data access and interpolation apparatus and method therefor |
| CN1822581A (en) * | 2005-10-04 | 2006-08-23 | 威盛电子股份有限公司 | Interpose module,interposer and its method |
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Application publication date: 20120815 |