CN102637588A - Grid electrode compensation isolation area etching method - Google Patents
Grid electrode compensation isolation area etching method Download PDFInfo
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- CN102637588A CN102637588A CN2012101381919A CN201210138191A CN102637588A CN 102637588 A CN102637588 A CN 102637588A CN 2012101381919 A CN2012101381919 A CN 2012101381919A CN 201210138191 A CN201210138191 A CN 201210138191A CN 102637588 A CN102637588 A CN 102637588A
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- etching
- etching process
- isolated area
- grid
- oxide layer
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Abstract
The invention discloses a grid electrode compensation isolation area etching method which comprises the following steps: providing a semiconductor substrate; forming a grid electrode structure and an oxide layer on the semiconductor substrate, wherein the grid electrode structure and the semiconductor substrate are covered by the oxide layer; carrying out the first etching process, and etching the oxide layer in the first etching process until an optical happening interferometer determines an etching end point, particularly, the etched oxide layer reaches the preset thickness; carrying out the second etching process, and removing the top of the grid electrode structure and the oxide layer in an open area on the semiconductor substrate in the second etching process; reserving the oxide layer on the side wall of the grid electrode structure; and forming a grid electrode compensation isolation area.
Description
Technical field
The present invention relates to the ic manufacturing technology field, and be particularly related to a kind of grid compensation isolated area lithographic method.
Background technology
In advanced integrated circuit technology, the common all around gate structure of grid compensation isolated area prevents that ion more heavy dose of in the subsequent technique from injecting close region and causing source/leakage break-through.
Grid compensation isolated area etching technics generally has main etching and two key steps of over etching, and main etching is accomplished the etching to oxide layer, and over etching is then accomplished for the residual oxide in spaciousness district and removed.Adopt optics luminescent spectrum appearance (OES) or set time to carry out the detecting of etching terminal as the main etching step 1 in the prior art.With regard to the etching terminal detecting of adopting optics luminescent spectrum appearance; Utilize the principle of the spectral intensity of etching product CO in the detecting plasma, when the most of completion of etching oxidation silicon, the concentration of product CO reduces; The spectral intensity of this wavelength will weaken, and judges etching terminal with this.Adopt traditional optical luminescent spectrum appearance to carry out the etching terminal detecting; Because when etching stops; Often etching interface has reached the substrate silicon surface of bottom, and what be difficult to avoid in the fast slightly zone of etching speed causes a certain amount of substrate silicon loss, influences the performance of device to a certain extent.And with regard to the etching terminal detecting of adopting the set time,, increased the uncontrollability of etching because the variation of etch rate all is difficult to reflection in the Thickness Variation of the silicon oxide layer that is etched and the real-time process cavity on etch period.
The luminous interferometer of optics (IEP:Interferometric Endpoint) generally is used for the shallow trench isolation of the following technology of 90nm from (STI:Shadow Trench Isolation) etching technics and polysilicon gate (Poly) etching technics in integrated circuit, its detecting medium is generally silicon.In shallow groove isolation etching technology, carry out the judgement of etching terminal through the etching depth of detecting groove, the degree of depth of groove is generally 3000 to 4000 dusts, and the wavelength of used light source is generally 200 to 400nm; And in polycrystalline silicon gate grid etching process, carry out the judgement of etching terminal through the remaining polysilicon layer thickness of detecting etching, and can detect minimum polysilicon thickness and be generally the 200 Izods right side, used optical source wavelength is generally 200 to 400nm.
Summary of the invention
In order to overcome the compensation of grid in prior art isolated area etching to the damage for substrate of the damage of bottom substrate silicon and plasma, the present invention provides a kind of grid compensation isolated area lithographic method.
To achieve these goals, the present invention proposes a kind of grid compensation isolated area lithographic method, comprising:
Semiconductor substrate is provided, is formed with the oxide layer of grid structure, the said grid structure of covering and said Semiconductor substrate on the said Semiconductor substrate;
Carry out first etching process, the said oxide layer of the said first etching process etching interferes appearance up to optics and confirms etching terminal, and the said oxide layer that promptly is etched reaches predetermined thickness;
Carry out second etching process, said second etching process is removed the oxide layer in spacious district on said grid structure top and the Semiconductor substrate, keeps the oxide layer of said grid structure sidewall, forms grid compensation isolated area.
Further, said optics interferes the utmost point low ultraviolet that the light source of appearance is wavelength 30nm to 100nm.
Further, the predetermined thickness of said oxide layer is 40 dust to 50 dusts.
Further, said oxide layer material is silica or silicon oxynitride.
Further, said first etching process is an anisotropic etching, and leading etching direction is perpendicular to said Semiconductor substrate direction.
Further, said second etching process is an isotropic etching, and the etching direction is perpendicular to said Semiconductor substrate direction.
Further, the parameter of said first etching process comprises: chamber pressure is 10mtorr to 30mtorr, and RF power is 400W to 700W, and the etching gas flow is 10sccm to 20sccm.
Further, the etching gas of said first etching process comprises CHF
3, CH
2F
2, CH
3F, C
4F
8And C
5F
8In one or more combination.
Further, the etching gas of said first etching process also comprises inert gas.
Further, said second etching process adopts timing controlled.
Further, the parameter of said second etching process comprises: chamber pressure is 10mtorr to 30mtorr, and RF power is 200W to 400W, and the etching gas flow is 12sccm to 24sccm.
Further, the etching gas of said second etching process comprises CHF
3, CH
2F
2, CH
3F, C
4F
8And C
5F
8In one or more combination.
Further, the etching gas of said second etching process also comprises inert gas.
Compared with prior art, the beneficial effect of grid compensation isolated area lithographic method of the present invention mainly shows:
Adopt the light source of the luminous interferometer of optics that first etching process is carried out the etching terminal detecting in first etching process; The predetermined thickness that oxide layer after accurate effectively control first etching process can be arranged; Etching in conjunction with second etching process; In the oxide layer of effectively removing spacious district on said grid structure top and the Semiconductor substrate, formation grid compensation isolated area pattern; Reduce the damage of etching process, effectively prevented oxygen injection and the plasma damage of the plasma in the etching process, thereby improve the performance of device for the spaciousness district for Semiconductor substrate.
Description of drawings
Fig. 1 is the flow chart of grid compensation isolated area lithographic method of the present invention;
Fig. 2 to Fig. 4 is the device architecture generalized section in the grid compensation isolated area etching process of the present invention.
Embodiment
In order to make the object of the invention, characteristic and beneficial effect better obviously understandable, invention is done further to describe below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of grid compensation isolated area lithographic method of the present invention.Fig. 2 to Fig. 4 is the device architecture generalized section in the grid compensation isolated area etching process of the present invention.
Please refer to Fig. 1, grid compensation isolated area lithographic method of the present invention comprises step S101 to S103.
Step S101: Semiconductor substrate is provided, is formed with the oxide layer of grid structure, the said grid structure of covering and said Semiconductor substrate on the said Semiconductor substrate.
Please refer to Fig. 2, Semiconductor substrate 201 is provided, described Semiconductor substrate 201 can be monocrystalline silicon, polysilicon or amorphous silicon; Said Semiconductor substrate 201 also can be silicon, germanium, GaAs or silicon Germanium compound etc.
On said Semiconductor substrate 201, form grid structure 202; Said grid structure 202 comprises bottom gate oxide layer 202a and top grid layer 202b, and the material of said gate oxide 202a comprises silicon dioxide, mixes the dielectric material of hafnium Hf silicon dioxide or other high-ks.Said grid layer 202b is polycrystalline silicon material.
Form the oxide layer 203 of overlies gate structure 202 and Semiconductor substrate 201.Further, oxide layer 203 is a silica material.
Step S102: carry out first etching process, the said oxide layer of the said first etching process etching interferes appearance up to optics and confirms etching terminal, and the oxide layer that promptly is etched reaches predetermined thickness.
Please refer to Fig. 3, said first etching process can be used any one lithographic technique in the prior art, preferred plasma etching technology, and etching gas comprises: CHF
3, CH
2F
2, CH
3F, C
4F
8And C
5F
8In one or more combination, etching gas is specifically leading to show as anisotropic etching, its leading etching direction is perpendicular to said Semiconductor substrate direction.In the oxide layer 203 ' in the said Semiconductor substrate of the first etching process etching 201 spacious districts, also can cause a spot of etching to the oxide layer 203 ' on said grid structure 202 sidewalls.The incident light source 301 that is interfered the appearance (not shown) by optics contacts the said reverberation 302a that is covered in the oxide layer 203 ' surface on the Semiconductor substrate 201 contacts the secondary reflection light 302b at the interface between said oxide layer 203 ' and the base semiconductor substrate 201 with incident light source 301 interference waveform, detects oxide layer 203 ' the covering Semiconductor substrate 201 spacious district residual thicknesses partly that are etched and confirms etching terminal.
Particularly, the optical path difference between reverberation 302a and the reverberation 302b is α
1-α
2, detecting membranous dielectric constant is n, and detecting membranous residual film thickness is Δ X, and optical source wavelength is λ, Δ X=(α
1-α
2) λ/2 π n.
Preferably, the optical source wavelength that the optics that is used for first etching process of the present invention detecting etching terminal interferes appearance is 30 to 100nm utmost point low ultraviolet, and the oxidated layer thickness minimum that can detect is 40 to 50 dusts.
As a preferred embodiment of first etching process of the present invention, the etching gas of said first etching process comprises C
4F
8, O
2And Ar, its range of flow is respectively 10sccm to 20sccm, 3sccm to 9sccm and 400sccm to 600sccm.Said C
4F
8Flow can be 10sccm, 16sccm, 20sccm, said O
2Flow correspond to 4sccm, 6sccm, 9sccm, the flow of said Ar corresponds to 400sccm, 500sccm, 600sccm.Other parameters are: chamber pressure 10mtorr to 30mtorrt, RF power 400W to 700W.
Step S103: carry out second etching process, said second etching process is removed the oxide layer in spacious district on said grid structure top and the Semiconductor substrate, keeps the oxide layer of said grid structure sidewall, forms grid compensation isolated area.
Please refer to Fig. 4, said second etching process can be used any one lithographic technique in the prior art, preferred plasma etching technology, and etching gas comprises: CHF
3, CH
2F
2, CH
3F, C
4F
8Perhaps C
5F
8In one or more combination, the specifically leading isotropic etching that shows as of etching gas.After accomplishing above-mentioned second etching process, the oxide layer 203 that originally was covered in Semiconductor substrate 201 spacious districts and grid structure 202 tops is removed, and finally is formed on the D type oxide layer 203 of grid structure 202 both sides ", accomplish the etching that grid compensates isolated area.
As a preferred embodiment of second etching process of the present invention, the etching gas of said second etching process comprises C
4F
8, O
2And Ar, its range of flow is respectively 12sccm to 24sccm, 2sccm to 6sccm and 400sccm to 600sccm.Said C
4F
8Flow can be 14sccm, 18sccm, 22sccm, said O
2Flow correspond to 3sccm, 5sccm, 6sccm, the flow of said Ar corresponds to 400sccm, 500sccm, 600sccm.Other parameters are: chamber pressure 10mtorr to 30mtorr, RF power 400W to 700W.
In conjunction with above-mentioned, a preferred embodiment of grid compensation isolated area lithographic method of the present invention is provided, comprising:
Deposit thickness is the silicon oxide layer of 300 dusts on the Semiconductor substrate of grid structure having;
Carry out first etching process, the etching gas of first etching process is C
4F
8, O
2And Ar, its flow corresponds to 10sccm, 4sccm, 400sccm, and chamber pressure is 20mtorr, and RF power is 550W; The optical source wavelength of the luminous interferometer of optics is 100nm, and the oxide layer predetermined thickness of detecting is 50 dusts;
Carry out second etching process, the etching of second etching process is mentioned and is C
4F
8, O
2And Ar, its flow corresponds to 14sccm, 3sccm, 400sccm, and chamber pressure is 20mtorr, and RF power is 450W;
In the grid compensation isolated area lithographic method of prior art; Since adopt optics luminescent spectrum appearance or the etching terminal method for detecting of set time, accurate inadequately for the oxide layer residual volume control before entering second etching process, before accomplishing second etching process; Often the oxide layer of Semiconductor substrate top has been removed fully; When whole etching is accomplished, base semiconductor substrate is caused damage, and cause oxygen to inject the spaciousness district of silicon chip.And adopt grid of the present invention to compensate the isolated area lithographic method; Owing to adopt the light source of the luminous interferometer of optics that first etching process is carried out the etching terminal detecting in first etching process; Semiconductor substrate top oxide layer predetermined thickness after accurate effectively control first etching process can be arranged, prevented that the oxygen in damage of etching process ionic medium body and spacious district from injecting.Through the etching of second etching process, when effectively removing oxide layer formation grid compensation isolated area pattern, reduce the damage of etching process effectively for Semiconductor substrate.Preferably; When adopting optical source wavelength is the endpoint detecting that the luminous interferometer of optics of 30nm to 100nm carries out first etching process; The predetermined thickness that can effectively control the first etching process rear oxidation layer is to 40 dust to 50 dusts; And time-controlled second etching process of arranging in pairs or groups; With in the etching process damage of Semiconductor substrate being reduced to below 30 dusts from the right scope of 60 Izods, and reduce effectively etching process for the damage of Semiconductor substrate, prevented that the oxygen in damage of etching process ionic medium body and spacious district from injecting.
Be merely the preferred embodiments of the present invention in sum, the present invention do not done any restriction.Any said those skilled in the art; In the scope that does not break away from technical scheme of the present invention; Technical scheme and technology contents to the present invention discloses are made any type of changes such as replacement or modification that are equal to; All belong to the content that does not break away from technical scheme of the present invention, still drop within protection scope of the present invention.
Claims (13)
1. a grid compensates the isolated area lithographic method, comprising:
Semiconductor substrate is provided, is formed with the oxide layer of grid structure, the said grid structure of covering and said Semiconductor substrate on the said Semiconductor substrate;
Carry out first etching process, the said oxide layer of the said first etching process etching interferes appearance up to optics and confirms etching terminal, and the said oxide layer that promptly is etched reaches predetermined thickness;
Carry out second etching process, said second etching process is removed the oxide layer in spacious district on said grid structure top and the Semiconductor substrate, keeps the oxide layer of said grid structure sidewall, forms grid compensation isolated area.
2. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
The light source that said optics interferes appearance is the utmost point low ultraviolet of wavelength 30nm to 100nm.
3. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
The predetermined thickness of said oxide layer is 40 dust to 50 dusts.
4. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
Said oxide layer material is silica or silicon oxynitride.
5. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
Said first etching process is an anisotropic etching, and leading etching direction is perpendicular to said Semiconductor substrate direction.
6. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
Said second etching process is an isotropic etching, and the etching direction is perpendicular to said Semiconductor substrate direction.
7. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
The parameter of said first etching process comprises: chamber pressure is 10mtorr to 30mtorr, and RF power is 400W to 700W, and the etching gas flow is 10sccm to 20sccm.
8. grid compensation isolated area lithographic method as claimed in claim 7 is characterized in that:
The etching gas of said first etching process comprises CHF
3, CH
2F
2, CH
3F, C
4F
8And C
5F
8In one or more combination.
9. grid compensation isolated area lithographic method as claimed in claim 8 is characterized in that:
The etching gas of said first etching process also comprises inert gas.
10. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
Said second etching process adopts timing controlled.
11. grid compensation isolated area lithographic method as claimed in claim 1 is characterized in that:
The parameter of said second etching process comprises: chamber pressure is 10mtorr to 30mtorr, and RF power is 200W to 400W, and the etching gas flow is 12sccm to 24sccm.
12. grid compensation isolated area lithographic method as claimed in claim 11 is characterized in that:
The etching gas of said second etching process comprises CHF
3, CH
2F
2, CH
3F, C
4F
8And C
5F
8In one or more combination.
13. grid compensation isolated area lithographic method as claimed in claim 12 is characterized in that:
The etching gas of said second etching process also comprises inert gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101381919A CN102637588A (en) | 2012-05-04 | 2012-05-04 | Grid electrode compensation isolation area etching method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101381919A CN102637588A (en) | 2012-05-04 | 2012-05-04 | Grid electrode compensation isolation area etching method |
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| CN102637588A true CN102637588A (en) | 2012-08-15 |
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ID=46621942
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| CN2012101381919A Pending CN102637588A (en) | 2012-05-04 | 2012-05-04 | Grid electrode compensation isolation area etching method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276417A (en) * | 2020-02-20 | 2020-06-12 | 上海华力集成电路制造有限公司 | Method for controlling shape of etching opening of contact hole |
| CN115097570A (en) * | 2022-08-22 | 2022-09-23 | 上海羲禾科技有限公司 | Waveguide etching method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153483A (en) * | 1998-11-16 | 2000-11-28 | United Microelectronics Corp. | Method for manufacturing MOS device |
| CN1848384A (en) * | 2005-12-02 | 2006-10-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon gate etching method |
| US20090042395A1 (en) * | 2007-07-13 | 2009-02-12 | Chien-Ling Chan | Spacer process for CMOS fabrication with bipolar transistor leakage prevention |
| CN100468677C (en) * | 2001-10-31 | 2009-03-11 | 兰姆研究有限公司 | Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring |
| CN101459066A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Gate, shallow slot isolation region forming method and flattening method for silicon base etching surface |
-
2012
- 2012-05-04 CN CN2012101381919A patent/CN102637588A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153483A (en) * | 1998-11-16 | 2000-11-28 | United Microelectronics Corp. | Method for manufacturing MOS device |
| CN100468677C (en) * | 2001-10-31 | 2009-03-11 | 兰姆研究有限公司 | Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring |
| CN1848384A (en) * | 2005-12-02 | 2006-10-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon gate etching method |
| US20090042395A1 (en) * | 2007-07-13 | 2009-02-12 | Chien-Ling Chan | Spacer process for CMOS fabrication with bipolar transistor leakage prevention |
| CN101459066A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Gate, shallow slot isolation region forming method and flattening method for silicon base etching surface |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276417A (en) * | 2020-02-20 | 2020-06-12 | 上海华力集成电路制造有限公司 | Method for controlling shape of etching opening of contact hole |
| CN111276417B (en) * | 2020-02-20 | 2022-08-09 | 上海华力集成电路制造有限公司 | Method for controlling shape of etching opening of contact hole |
| CN115097570A (en) * | 2022-08-22 | 2022-09-23 | 上海羲禾科技有限公司 | Waveguide etching method |
| CN115097570B (en) * | 2022-08-22 | 2023-04-07 | 上海羲禾科技有限公司 | Waveguide etching method |
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Application publication date: 20120815 |