CN102629573B - Thin film transistor liquid crystal display array substrate and manufacturing method thereof - Google Patents
Thin film transistor liquid crystal display array substrate and manufacturing method thereof Download PDFInfo
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- CN102629573B CN102629573B CN201110192507.8A CN201110192507A CN102629573B CN 102629573 B CN102629573 B CN 102629573B CN 201110192507 A CN201110192507 A CN 201110192507A CN 102629573 B CN102629573 B CN 102629573B
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Abstract
Disclosed in the invention are a thin film transistor liquid crystal display (TFT-LCD) array substrate and a manufacturing method thereof, thereby reducing an unqualified rate of a TFT-LCD array substrate. The manufacturing method comprises: respectively forming a gate line, an active layer, a thin film transistor (TFT) switch and a signal line on a substrate and forming buffer layers in intersection regions by utilizing a composition process for forming the active layer, wherein the intersection regions include a set region at at least one side of the signal line at the position of intersection with the gate line; and forming a pixel electrode on the substrate, wherein the signal line has been formed on the substrate.
Description
Technical field
The present invention relates to LCD Technology field, particularly a kind of thin-film transistor LCD device array substrate and manufacture method.
Background technology
In recent years, along with scientific and technical progress, digital to television starts in Stepping into daily life.(Thin Firm Transistor Liquid Crystal Display, TFT-LCD) is little with its volume, low in energy consumption, radiationless for Thin Film Transistor-LCD, and resolution advantages of higher becomes current leading products.
TFT-LCD is mainly by forming the array base palte of box and color membrane substrates, and wherein, the manufacture craft of TFT-LCD array base palte has determined its properties of product, rate of finished products and price.
At present, TFT-LCD array base palte is to complete by composition technique repeatedly, in composition technique, have respectively and comprise each time: mask, exposure, development, etching and the technique such as peel off, wherein, etching technics comprises dry etching and wet etching, so the number of times of composition technique is the standard of weighing the complicated and simple degree of making TFT-LCD array base palte, the number of times that reduces composition technique just means the reduction of cost of manufacture.Existing TFT-LCD array base palte, referring to Fig. 1, comprising: gate line 1, TFT switch 2, holding wire 3, pixel electrode 4.Generally by four composition techniques, complete, specifically comprise: on substrate, deposit grid metal, by the first composition technique, form gate line; On substrate, metal level is leaked in successive sedimentation gate insulator, semiconductor layer, doping semiconductor layer and source, by the second composition technique, forms active layer, holding wire, and TFT switch; Continue deposit passivation layer, by composition technique for the third time, form passivation layer and via hole; Deposit transparent conductive layer, forms pixel electrode by the 4th composition technique.Thereby formed TFT-LCD array base palte.
Because leak after metal level in successive sedimentation gate insulator, semiconductor layer, doping semiconductor layer and source on the substrate having formed gate line, by the second composition technique, form active layer, holding wire, and TFT switch, therefore, referring to Fig. 2 (Fig. 2 be in Fig. 1 for the second time the sectional view of A-A direction after composition technique), semiconductor layer, doping semiconductor layer between holding wire and gate line have all been etched, directly from gate insulator (SIN
x) source that transits to leaks metal level (SD).Like this, there is the slope of a steeper intersection region of holding wire and gate line, thereby, in follow-up composition technique, because the angle of gradient on slope is larger, other region of the photoresist Thickness Ratio covering is above thin, when carrying out wet etching, liquid easily occurs to bore to be carved, and makes the holding wire of intersection region occur broken string open circuit.
When this array base palte also comprises public electrode, as the public electrode 6 in Fig. 1, generally by the first composition technique, form gate line and public electrode simultaneously.Therefore, also there is the slope of a steeper intersection region of holding wire and public electrode wire, also easy in follow-up composition technique, and wet etching liquid occurs to bore to be carved, and makes the holding wire of this intersection region occur the open circuit that breaks.
As can be seen here, in the TFT-LCD array base palte that existing four composition techniques are made, holding wire, easily having breakpoint with gate line or public electrode wire intersection region, causes bad TFT-LCD array base palte.
Summary of the invention
The embodiment of the present invention provides a kind of TFT-LCD array base palte and manufacture method, in order to reduce the fraction defective of TFT-LCD array base palte.
The embodiment of the present invention provides a kind of manufacture method of thin-film transistor LCD device array substrate, comprising:
On substrate, form respectively gate line, active layer, thin-film transistor TFT switch, and holding wire, wherein, by forming the composition technique of described active layer, form resilient coating in intersection region, described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall;
On the substrate that has formed holding wire, form pixel electrode.
The embodiment of the present invention provides a kind of thin-film transistor LCD device array substrate, comprise: gate line, active layer, thin-film transistor TFT switch, holding wire, and pixel electrode, wherein, intersection region comprises: resilient coating, and described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall; Described resilient coating comprises: semiconductor layer, or, active layer.
In the embodiment of the present invention, by composition technique repeatedly, make TFT-LCD array base palte, wherein, by forming the composition technique of described active layer, in intersection region, form resilient coating, this intersection region comprises the setting regions with at least one side of the holding wire of gate line infall, like this, in the TFT-LCD array base palte of making, comprise with the setting regions of at least one side of the holding wire of gate line infall: resilient coating, in holding wire and the gate line zone of intersection, remain with semiconductor layer, or, active layer, thereby, in intersection region, form a two-stage step, from gate insulator, first transit to resilient coating, and then metal level is leaked in the source that transits to, reduced greatly the angle of gradient on slope in intersection region, in follow-up composition technique, this region can be coated with and spread thicker photoresist, while carrying out wet etching, reduced liquid the probability of carving has occurred to bore, reduced the probability that the holding wire of intersection region opens circuit, improved the yields of TFT-LCD array base palte.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of TFT-LCD array base palte in prior art;
Fig. 2 is the sectional view of A-A direction after composition technique for the second time in Fig. 1;
Fig. 3 makes the flow chart of TFT-LCD array base palte in the embodiment of the present invention;
Fig. 4 (a) is the schematic diagram of TFT-LCD array base palte in the embodiment of the present invention one;
Fig. 4 (b) is the sectional view of B-B direction after composition technique for the second time in Fig. 4 in the embodiment of the present invention (a);
Fig. 5 is the flow chart of making TFT-LCD array base palte holding wire and TFT switch in the embodiment of the present invention one;
Fig. 6 is the sectional view of TFT-LCD array base palte B-B direction after composition technique for the third time in the embodiment of the present invention two;
Fig. 7 makes the flow chart of TFT-LCD array base palte holding wire in the embodiment of the present invention two;
Fig. 8 (a) is the schematic diagram that the embodiment of the present invention comprises the TFT-LCD array base palte of public electrode;
Fig. 8 (b) is the sectional view of C-C direction after the middle formation of Fig. 8 in the embodiment of the present invention (a) holding wire composition technique;
Fig. 9 is the schematic diagram of double grid line TFT-LCD array base palte in the embodiment of the present invention.
Embodiment
In the embodiment of the present invention, while forming the active layer of TFT-LCD array base palte by composition technique, in intersection region, form resilient coating, this intersection region comprises the setting regions with at least one side of the holding wire of gate line infall, like this, between holding wire and gate line, retained semiconductor layer, or, semiconductor layer and doping semiconductor layer, thereby, in the intersection region of holding wire and gate line, have a two-stage step, from gate insulator, first transit to resilient coating, and then metal level is leaked in the source that transits to.Therefore, reduced greatly the angle of gradient on slope in intersection region, in follow-up composition technique, this region can be coated with and spread thicker photoresist, while carrying out wet etching, reduced liquid the probability of carving has occurred to bore, reduce the probability that the holding wire of intersection region opens circuit, improved the yields of TFT-LCD array base palte.
In the embodiment of the present invention, adopt composition technique to complete TFT-LCD array base palte, referring to Fig. 3, be specially:
Step 301: form respectively gate line on substrate, active layer, thin-film transistor TFT switch, and holding wire.Wherein, by forming the composition technique of active layer, form resilient coating in intersection region, this intersection region comprises the setting regions with at least one side of the holding wire of gate line infall.
In the embodiment of the present invention, can, by three times, four times, five times or more times composition technique formation array base palte, therefore,, can pass through twice or three composition techniques formation gate lines active layer, thin-film transistor TFT switch, and holding wire here.
Wherein, by twice composition technique, form gate line, active layer, thin-film transistor TFT switch, and holding wire comprises: by composition technique for the first time, on the substrate that has deposited grid metal levels, form gate line, and on the substrate that forms gate line, form active layer, holding wire, and TFT switch by composition technique for the second time.
Now, the composition technique that forms active layer is composition technique for the second time.Therefore, on the mask plate in the second composition technique, still adopt halftone (half-tone mask plate) technique, on this mask plate, not only comprised transmission region and light tight region, and, also comprised part transmission region.Wherein, light tight region generally comprises: the holding wire of design, the figure of TFT switch.And part transmission region comprises: the groove of TFT switch, and first masked areas corresponding with intersection region.Be that with existing technique difference the part transmission region on this mask plate comprises: the groove of TFT switch, and and first masked areas corresponding with intersection region, and intersection region comprises on array base palte the setting regions with at least one side of the holding wire of gate line infall.
In the embodiment of the present invention, also can form gate line by three composition techniques, thin-film transistor TFT switch, and holding wire comprises: by composition technique for the first time, on the substrate that has deposited grid metal levels, form gate line, and by the active layer of composition technique formation for the second time, and TFT raceway groove, and on the substrate that has formed TFT raceway groove, form holding wire by composition technique for the third time, and TFT source-drain electrode.
Now, the composition technique that forms active layer is still composition technique for the second time, on mask plate in the second composition technique, generally only include light tight region and transmission region, wherein, light tight region not only comprises: design holding wire, TFT source-drain electrode, but also comprise second masked areas corresponding with intersection region, be with existing technique difference, the light tight region of this mask plate also comprises: second masked areas corresponding with intersection region, and intersection region comprises on array base palte the setting regions with at least one side of the holding wire of gate line infall.
In the embodiment of the present invention, intersection region comprises: with the setting regions of holding wire one side of gate line infall, the probability that occurs broken string open circuit for further reducing the holding wire of intersection region, this intersection region comprises: with the setting regions of the holding wire both sides of gate line infall
The shape of setting regions comprises: square, and triangle, or circular arc.When general setting regions is square region, preferably, the first side of this square region overlaps with holding wire, the Second Edge of square region and apart 2～4um parallel with first side; The 3rd limit of square region is parallel with gate line respectively with the 4th limit, and be positioned at the both sides of gate line, the 4th limit and the 3rd limit are at a distance of 4～8um, along holding wire tangent plane direction to external expansion 2～4um, and along grid line tangent plane direction to external expansion 2～4um, thus obtained region is intersection region.Preferably, can select 3um.Can either guarantee to play like this effect of buffering, also can not produce harmful effect to pixel region.Certainly, if two side directions along stretching, guarantee non-intersectly with adjacent holding wire or non-intersect with adjacent pixel electrode, obtain region and can be intersection region.
After designing the mask plate of composition technique for the second time, can adopt the technique of prior art on substrate, forming respectively gate line, active layer, thin-film transistor TFT switch, and holding wire.
Step 302: form pixel electrode on the substrate that has formed holding wire.
Here, continue to form pixel electrode by composition technique.Can be by once, twice, three time or more times composition technique form the pixel electrode of array base palte, can adopt prior art to form the pixel electrode of array base palte.
If not only formed gate line, active layer, thin-film transistor TFT switch after in step 301 twice or three composition techniques, and holding wire, but also formed passivation layer and via hole, here, only need to adopt a composition technique just can form the pixel electrode of array base palte.
If only formed gate line after twice or three composition techniques in step 301, active layer, thin-film transistor TFT switch, and holding wire, can adopt twice, three time here or more times composition technique forms pixel electrode.
Wherein, adopt twice composition technique to form pixel electrode, comprising: forming holding wire, and deposit passivation layer on the substrate of TFT switch, and form passivation layer and form passivation layer via hole on the drain electrode of TFT switch by a composition technique.Wherein, the material of passivation layer comprises respectively: one or more in SiNx, SiOx and SiOxNy.
Then, on the substrate that has formed passivation layer, by the method for sputter or thermal evaporation, deposit transparent conductive layer, and form pixel electrode by composition technique again, makes this pixel electrode be connected with the drain electrode of TFT switch by via hole.
Or, can also adopt three composition technique to form the pixel electrode of TFT-LCD array base paltes, specifically comprise: by chemical gaseous phase depositing process, on substrate, form SiNx or SiOx or SiOxNy material, form passivation layer.After passivation layer forms, carry out composition technique one time, it is the photoetching process of via hole, comprise: by positive photoresist or negative photoresist by needed graph copying on substrate, method by dry etching is carried out etching by the substrate that completes via photo carving technology, the passivation layer at via hole place is etched away, expose the metal level below via hole, be connected with pixel electrode.The glass substrate that completes via etch technique is carried out to peeling off of photoresist, then carry out next step pixel electrode forming technology.
Pixel electrode forming technology is that pixel electrode composition technique comprises: adopt physical gas-phase deposite method evaporation transparent pixels electrode on the glass substrate that completes passivation layer via hole technique, transparent pixels electrode material has ITO or IZO.After transparent pixels electrode evaporation process completes, carry out the photoetching process of pixel electrode, by positive photoresist or negative photoresist by the needed graph copying of transparent pixels electrode on substrate.After the photoetching process of pixel electrode completes, by the method for wet etching, carry out the etching of transparent pixels electrode, by final needed pattern etching out.Complete after the etching technics of transparent pixels electrode, the photoresist remaining on substrate is peeled off, completed the forming technology of pixel electrode.
As from the foregoing, the embodiment of the present invention can by above-mentioned three times, four times, five times or repeatedly composition technique can form TFT-LCD array base palte.
Below in conjunction with Figure of description, the embodiment of the present invention is described in further detail.
Embodiment mono-, in the present embodiment, by four composition techniques, form TFT-LCD array base palte, comprise: by composition technique for the first time, on substrate, form gate line, wherein, the substrate of TFT-LCD array base palte is generally glass substrate, adopt the method for sputter or thermal evaporation, on this substrate, deposit one deck grid metal level, then, on grid metal level, smear after photoresist, the mask plate by thering is gate line figure to photoresist expose, development treatment by etching with the technique such as peel off and form gate line.Here, etching is wet etching, by liquid, the metal etch that does not have photoresist to cover is fallen.The material of grid metal level comprises: one or more in Al, Mo, Cu, MoW and Cr.
By composition technique for the second time, on the substrate that has formed gate line, form active layer, thin-film transistor TFT switch, and holding wire, wherein, part transmission region on mask plate in the second composition technique comprises: first masked areas corresponding with intersection region, and intersection region be on array base palte with the setting regions of at least one side of the holding wire of gate line infall.Now, form resilient coating in intersection region, resilient coating comprises semiconductor layer.
By composition technique for the third time, form passivation layer and form passivation layer via hole on the drain electrode of TFT switch.Wherein, the material of passivation layer comprises respectively: one or more in SiNx, SiOx and SiOxNy.
Finally, on the substrate that has formed passivation layer, by the method for sputter or thermal evaporation, deposit transparent conductive layer, and form pixel electrode by the 4th composition technique, makes this pixel electrode be connected with the drain electrode of TFT switch by via hole.
Form TFT-LCD array base palte as shown in Fig. 4 (a), this array base palte comprises: gate line 1, TFT switch 2, holding wire 3, pixel electrode 4, and the intersection region 5 of holding wire and gate line.This intersection region 5 comprises on this array base palte, the setting regions of the both sides of the holding wire intersecting with gate line.
Fig. 4 (b) is the sectional view of B-B direction after Fig. 4 (a) the second composition technique, wherein, comprising: glass substrate (Glass), grid line layer (G), gate insulator (SIN
x), semiconductor layer (a-Si), doping semiconductor layer (n+a-Si), and metal level (SD) is leaked in source.Below in conjunction with Fig. 4 (b), to forming active layer, holding wire by the second composition technique forming on the substrate of gate line in the embodiment of the present invention, and TFT switch is described in further detail, and detailed process, referring to Fig. 5, comprising:
Step 501: deposit successively gate insulation layer, active layer and source and leak metal level on the substrate that forms gate line.In the embodiment of the present invention, active layer comprises: semiconductor layer and doping semiconductor layer.
Here, gate insulator can adopt the monofilm of silicon nitride SiNx, silicon-base oxide SiOx, nitrogen oxidation silicon SiOxNy, also can use the composite membrane of above-mentioned material.Semiconductor layer adopts a-Si amorphous silicon membrane, and doping semiconductor layer adopts N+a-Si amorphous silicon membrane.The material that metal level is leaked in source comprises: one or more in Al, Mo, Cu, MoW and Cr.
Step 502: leak on metal level and smear photoresist in source.
Can adopt the mode of static gluing or dynamic gluing leaking on metal level and smearing photoresist in source.
Step 503: photoresist is exposed and development treatment by mask plate.
On mask plate, not only comprised the holding wire of design and the figure of TFT switch, and, on this mask plate, also comprised part transmission region.This mask plate has designed halftone protection zone.
Part transmission region not only comprises: the groove of TFT switch, also comprises: first masked areas corresponding with intersection region, this intersection region comprises on array base palte the setting regions with the both sides of the holding wire of gate line infall.
Therefore, expose and development treatment after, the substrate forming comprises the first area that retains the first thickness photoresist, and the second area that retains the second thickness photoresist, wherein, first area is corresponding with the light tight region on mask plate respectively, and second area is corresponding with the part transmission region on mask plate respectively.Can part printing opacity due to the part transparent area on mask plate, for example light transmittance is 40%, therefore, the photoresist of first area retains completely, and the part photoresist of second area is exposed, like this, the second thickness is less than the first thickness.
Step 504: first area on substrate and second area are etched away successively with source leakage metal level, doping semiconductor layer and semiconductor layer in exterior domain.
By wet etching, metal level etching is leaked to the source in exterior domain in first area and second area;
By dry etching, first area and second area are etched away with the active layer in exterior domain, be about to first area and second area and etch away successively with the doping semiconductor layer in exterior domain and semiconductor layer.
Step 505: photoresist is carried out to ashing, remove the photoresist of the second thickness.
Photoresist is carried out to ashing, the photoresist of setting thickness is removed.Here, setting thickness is the second thickness.The second thickness is less than the first thickness, and therefore, after ashing, first area still has photoresist protection, and photoresist on second area has been removed, exposes source and leaks metal level.Be intersection region, and the photoresist on TFT groove is removed.
Step 506: the doping semiconductor layer that the source of removing in the second area of photoresist is leaked in metal level and active layer etches away.
By wet etching, metal level is leaked in the source in second area and etch away, by dry etching, the doping semiconductor layer in second area is etched away.
After etching, in intersection region, and TFT groove still remains with semiconductor layer.
Step 507: photoresist remaining after ashing is peeled off, formed holding wire, and TFT switch.
Pass through said process, formed active layer, holding wire, and TFT switch, and on this array base palte, comprise semiconductor layer with the setting regions of the both sides of the holding wire of gate line infall, in the intersection region of holding wire and gate line, remain with semiconductor layer, between holding wire and gate line, formed two stage steps, from grid (G) and gate insulator (SIN
x) first transit to semiconductor layer (a-Si), and then the source that transits to leaks metal level (SD), as shown in Fig. 4 (b), therefore, reduced greatly the angle of gradient on slope in intersection region, reduced the probability that the holding wire of intersection region opens circuit.
In the present embodiment, part transmission region comprises: the groove of TFT switch, and the first masked areas corresponding to intersection region.Like this, the light transmittance of part transmission region is relevant with the gash depth of TFT switch, excessive too small all not all right, can exert an influence to the formation of the raceway groove of TFT switch.Generally, the light transmittance 30%-70% of part transmission region.Be preferably 40%.
Embodiment bis-, in the present embodiment, by five composition techniques, form TFT-LCD array base paltes, comprising: by composition technique for the first time, form gate line on substrate; Depositing semiconductor layers and doping semiconductor layer on the substrate that forms gate line, by the active layer of composition technique formation for the second time, and TFT raceway groove; By composition technique for the third time, on the substrate that has formed TFT raceway groove, form holding wire, and TFT source-drain electrode; By the 4th composition technique, form passivation layer and form passivation layer via hole on the drain electrode of TFT switch; Finally, by the 5th composition technique, form pixel electrode, this pixel electrode is connected with the drain electrode of TFT switch by via hole.Wherein, by the second composition technique, in intersection region, form resilient coating, resilient coating comprises active layer, comprises: semiconductor layer and doping semiconductor layer.
Form the outward appearance of TFT-LCD array base palte still as Fig. 4 (a) as shown in, but for the second time after composition technique the sectional view of B-B direction as shown in Figure 6, now, semiconductor layer (a-Si) and doping semiconductor layer (n+a-Si) composition step.Below in conjunction with Fig. 6, to forming active layer by the second composition technique in the embodiment of the present invention, and TFT raceway groove is described in further detail, and detailed process, referring to Fig. 7, comprising:
Step 701: deposit successively gate insulation layer, active layer and source and leak metal level on the substrate that forms gate line.
Step 702: leak on metal level and smear photoresist in source.
Step 703: photoresist is exposed and development treatment by mask plate.
Here, mask plate only includes light tight region and transmission region, comprises: the second masked areas corresponding with intersection region with light tight region on the difference mask plate of prior art.And intersection region comprises on array base palte the setting regions with the both sides of the holding wire of gate line infall.
Therefore, expose and development treatment after, on the substrate of formation, on intersection region, remain with photoresist.
Step 704: metal level is leaked in source in the region of photoresist, active layer etches away successively by not retaining on substrate.
Owing to remaining with photoresist on intersection region, therefore, intersection region still remains with doping semiconductor layer, and semiconductor layer.
Step 705: photoresist is peeled off, formed active layer, and TFT raceway groove.
By said process, on the array base palte of formation, comprise semiconductor layer and doping semiconductor layer with the setting regions of the both sides of the holding wire of gate line infall.In the intersection region of holding wire and gate line, remain with resilient coating, between holding wire and gate line, formed two stage steps, from grid (G) and gate insulator (SIN
x) first transit to resilient coating, and then transit to source leakage metal level (SD), as shown in Figure 6, resilient coating comprises: semiconductor layer and doping semiconductor layer.Therefore, reduce greatly the angle of gradient on slope in intersection region, reduced the probability that the holding wire of intersection region opens circuit.
Above-mentioned two embodiment have described respectively by four composition techniques and have formed TFT-LCD array base palte, and form TFT-LCD array base palte by five composition techniques, but the embodiment of the present invention is not limited to this, also can be by three times, six times, seven inferior composition techniques form TFT-LCD array base palte, no matter pass through composition technique several times and form TFT-LCD array base palte, in forming the composition technique of active layer, in intersection region, form resilient coating, this intersection region comprises the setting regions with at least one side of the holding wire of gate line infall.Concrete process is not just being described in detail.
On the TFT-LCD array base palte forming in the embodiment of the present invention, comprise with the setting regions of at least one side of the holding wire of gate line infall: resilient coating, thereby, in the intersection region of holding wire and gate line, there is a two-stage step, from gate insulator, first transit to resilient coating, and then metal level is leaked in the source that transits to.Therefore, reduced greatly the angle of gradient on slope in intersection region, in follow-up composition technique, this region can be coated with and spread thicker photoresist, while carrying out wet etching, reduced liquid the probability of carving has occurred to bore, reduce the probability that the holding wire of intersection region opens circuit, improved the yields of TFT-LCD array base palte.
In addition, in etching technics, static may produce punch-through effect to the metal wire of active graphical in intersection region, in the embodiment of the present invention one, due to when step 504 is carried out etching, on second area, there is photoresist, like this, the extra area that increases holding wire, when having accumulation of static electricity, static can concentrate on by the invalid metallic region under the protection of the photoresist of the second thickness in the process discharging, static discharges the high temperature or the electric arc that produce and only the metal of inactive area is impacted, and useful signal line metal level under the photoresist of the first thickness protection can not be subject to the impact of static.Therefore, even if there is static discharge in this region, also only can punctures the extra metal in second area increasing on holding wire, and can normal signal line metallic region not impacted, avoid electrostatic breakdown to cause bad array base palte.
Holding wire and gate line intersection region can form electric capacity, owing to finally leaking metal level and etched away removing source in the second area of photoresist, therefore, the structure of the holding wire forming does not change, the electric capacity of holding wire and gate line intersection region can not change, and can not bring extra load to liquid crystal display drive circuit.
By above-mentioned technique, not only can produce the TFT-LCD array base palte as shown in Fig. 4 (a), and, can also produce the TFT-LCD array base palte that comprises public electrode as shown in Fig. 8 (a), this TFT-LCD array base palte comprises: gate line 1, TFT switch 2, holding wire 3, pixel electrode 4, the intersection region 5 of holding wire and gate line, public electrode 6, and the intersection region 7 of holding wire and public electrode wire.
Wherein, can on substrate, form gate line 1 and public electrode 6 by composition technique for the first time simultaneously.Therefore, intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, or, setting regions with at least one side of the holding wire of public electrode wire infall, or, with the setting regions of at least one side of the holding wire of gate line infall and with the setting regions of at least one side of the holding wire of public electrode wire infall.
Like this, by forming the composition technique of active layer, in intersection region, form resilient coating.。
Form the technique detailed process of active layer as shown in above-mentioned steps 501-507 or step 701-705, wherein, intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall and with the setting regions of at least one side of the holding wire of public electrode wire infall.
Fig. 8 (b) is Fig. 8 (a) sectional view of C-C direction after composition technique for the second time, visible, on this array base palte, comprises semiconductor layer with the setting regions of the both sides of the holding wire of public electrode wire infall.At holding wire and public electrode wire intersection region, remain with resilient coating, here, resilient coating is semiconductor layer, between holding wire and public electrode, has formed two stage steps.Like this, from public electrode (C) and gate insulator (SIN
x) first transit to semiconductor layer (a-Si), and then metal level (SD) is leaked in the source that transits to.Reduce greatly the angle of gradient on slope in intersection region, reduced the probability that the holding wire of intersection region opens circuit.Certainly, in the embodiment of the present invention, resilient coating also can comprise: semiconductor layer and doping semiconductor layer, comprise active layer.
In the above-mentioned TFT-LCD array base palte that comprises public electrode, intersection region comprises the setting regions with the both sides of the holding wire of gate line infall simultaneously, and with the setting regions of the both sides of the holding wire of public electrode wire infall.Certainly, in another embodiment of the present invention, intersection region only includes an above-mentioned region.
The TFT-LCD array base palte that can also make double grid line by above-mentioned technique, referring to Fig. 9, comprising: gate line 1, TFT switch 2, holding wire 3, pixel electrode 4, and the intersection region 5 of holding wire and gate line.Wherein, this intersection region is corresponding with the setting regions of the holding wire figure both sides that intersect with gate line on the mask plate forming in the composition technique of holding wire.Concrete manufacturing process has just been not repeated.
In above-described embodiment, take the both sides of holding wire is described as example, certainly the embodiment of the present invention is not limited to this, intersection region can comprise: with the setting regions of a side of the holding wire of gate line infall, with the Huo Liangge region, a region in the setting regions of a side of the holding wire of public electrode wire infall.
Therefore,, in the TFT-LCD array base palte in the embodiment of the present invention, comprising: gate line, active layer, thin-film transistor TFT switch, holding wire, and pixel electrode, wherein, intersection region comprises resilient coating, and this intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, resilient coating comprises: semiconductor layer, or, active layer.Active layer comprises: semiconductor layer and doping semiconductor layer.
When array base palte also comprises: public electrode; This intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, or, setting regions with at least one side of the holding wire of public electrode wire infall, or, with the setting regions of at least one side of the holding wire of gate line infall and with the setting regions of at least one side of the holding wire of public electrode wire infall.
In above-described embodiment, the figure of setting regions is square, but the embodiment of the present invention is not limited to this, can also be triangle, or, circular arc.
In the embodiment of the present invention, by composition technique repeatedly, form TFT-LCD array base palte, wherein, in composition technique by formation active layer, in intersection region, form resilient coating, this intersection region comprises the setting regions with at least one side of the holding wire of gate line infall, and with the setting regions of at least one side of the holding wire of public electrode wire infall in one or two, like this, in the TFT-LCD array base palte forming, comprise resilient coating with the setting regions of at least one side of the holding wire of gate line infall, and/or, comprise resilient coating with the setting regions of at least one side of the holding wire of public electrode wire infall.Therefore, in the intersection region of holding wire and gate line and/or public electrode wire, remain with resilient coating, in intersection region, form a two-stage step, reduced greatly the angle of gradient on slope in intersection region, in follow-up composition technique, this region can be coated with and spread thicker photoresist, while carrying out wet etching, has reduced liquid the probability of carving occurs to bore, reduce the probability that the holding wire of intersection region opens circuit, improved the yields of TFT-LCD array base palte.
In addition, while adopting the etching for the first time of half tone (half-tone mask plate) technique, due to the extra area that increases holding wire, even if there is static discharge intersection region, also only can puncture the extra metal in second area increasing on holding wire, and can normal signal line metallic region not impacted, avoided electrostatic breakdown to cause bad array base palte.
Adopt the etching for the second time of half tone (half-tone mask plate) technique that the source leakage metal level in second area has been etched away, therefore, the structure of the holding wire forming does not change, and the electric capacity of intersection region can not change, and can not bring extra load to liquid crystal display drive circuit.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (11)
1. a manufacture method for thin-film transistor LCD device array substrate, is characterized in that, comprising:
On substrate, form respectively gate line, active layer, thin-film transistor TFT switch, and holding wire, wherein, by forming the composition technique of described active layer, form resilient coating in intersection region, described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, and described setting regions and adjacent holding wire non-intersect or non-intersect with adjacent pixel electrode;
On the substrate that has formed described holding wire, form pixel electrode.
2. manufacture method as claimed in claim 1, it is characterized in that, when forming public electrode on substrate, described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, or, with the setting regions of at least one side of the holding wire of public electrode wire infall, or, with the setting regions of at least one side of the holding wire of gate line infall and with the setting regions of at least one side of the holding wire of public electrode wire infall.
3. manufacture method as claimed in claim 1 or 2, is characterized in that, the described gate line that forms respectively on substrate, and active layer, thin-film transistor TFT switch, and holding wire comprises:
By composition technique for the first time, on the substrate that has deposited grid metal levels, form gate line, and on the substrate that forms gate line, form active layer by composition technique for the second time, holding wire, and TFT switch, wherein, the mask plate part transmission region of the described technique of composition for the second time comprises: the groove of TFT switch, first masked areas corresponding with described intersection region; Or,
By composition technique for the first time, on the substrate that has deposited grid metal levels, form gate line, and by the active layer of composition technique formation for the second time, and TFT raceway groove, and on the substrate that has formed TFT raceway groove, form holding wire by composition technique for the third time, and TFT source-drain electrode, wherein, the light tight region of mask plate of the described technique of composition for the second time comprises: second masked areas corresponding with described intersection region.
4. manufacture method as claimed in claim 3, is characterized in that, describedly by composition technique for the second time, on the substrate that forms gate line, forms active layer, holding wire, and TFT switch comprises:
On the substrate that forms gate line, deposit successively gate insulation layer, active layer and source and leak metal level;
In described source, leak on metal level and smear after photoresist, by mask plate, described photoresist is exposed and development treatment, the substrate forming comprises the first area that retains the first thickness photoresist, and the second area that retains the second thickness photoresist, wherein, described first area is corresponding with the light tight region on described mask plate respectively, light tight region on described mask plate comprises the figure that forms holding wire, TFT switch, and described second area is corresponding with the part transmission region on described mask plate respectively;
First area and second area on described substrate are etched away successively with source leakage metal level, active layer in exterior domain;
Described photoresist is carried out to ashing, remove the photoresist of the second thickness;
The doping semiconductor layer that the source of removing in the second area of photoresist is leaked in metal level and active layer etches away;
Photoresist remaining after ashing is peeled off, formed holding wire, and TFT switch.
5. manufacture method as claimed in claim 3, is characterized in that, described by the active layer of composition technique formation for the second time, and TFT raceway groove comprises:
On the substrate that forms gate line, deposit successively gate insulation layer, active layer and source and leak metal level;
In described source, leak on metal level and smear after photoresist, by mask plate, described photoresist is exposed and development treatment, the described intersection region on the substrate of formation retains photoresist;
By not retaining on described substrate, metal level is leaked in source in the region of photoresist, active layer etches away successively;
The photoresist of reservation is peeled off, formed active layer, and TFT raceway groove.
6. manufacture method as claimed in claim 3, is characterized in that, the light transmittance of described part transmission region is between 30-70%.
7. manufacture method as claimed in claim 1 or 2, is characterized in that, the shape of described setting regions comprises: square, and triangle, or circular arc.
8. manufacture method as claimed in claim 7, is characterized in that, when described setting regions is square region, the first side of described square region overlaps with described holding wire, and the Second Edge of described square region is parallel with first side and at a distance of 2～4um;
The 3rd limit of described square region is parallel with described gate line respectively with the 4th limit, and is positioned at the both sides of described gate line, and the 4th limit and the 3rd limit are at a distance of 4～8um.
9. a thin-film transistor LCD device array substrate, comprising: gate line, and active layer, thin-film transistor TFT switch, holding wire, and pixel electrode, is characterized in that, intersection region comprises: resilient coating, wherein,
Described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall;
Described resilient coating comprises: semiconductor layer, or, active layer; Described active layer comprises: semiconductor layer and doping semiconductor layer.
10. array base palte as claimed in claim 9, is characterized in that, described array base palte also comprises: public electrode;
Described intersection region comprises: with the setting regions of at least one side of the holding wire of gate line infall, or, setting regions with at least one side of the holding wire of public electrode wire infall, or, with the setting regions of at least one side of the holding wire of gate line infall and with the setting regions of at least one side of the holding wire of public electrode wire infall.
11. array base paltes as claimed in claim 9, is characterized in that, adopt the method described in arbitrary claim in claim 1-7 to make.
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| CN103809341B (en) * | 2014-02-17 | 2016-04-27 | 北京京东方光电科技有限公司 | Array base palte and display device |
| CN104503178A (en) * | 2014-12-31 | 2015-04-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN104766868B (en) * | 2015-03-24 | 2018-03-27 | 深圳市华星光电技术有限公司 | Array base palte and display panel |
| CN104849930B (en) * | 2015-05-29 | 2017-10-13 | 合肥鑫晟光电科技有限公司 | Array base palte and preparation method thereof and display device |
| CN105633102B (en) * | 2016-04-05 | 2018-11-09 | 京东方科技集团股份有限公司 | Array substrate, thin film transistor (TFT), the production method of display device, display device |
| CN105702687A (en) * | 2016-04-13 | 2016-06-22 | 武汉华星光电技术有限公司 | TFT (Thin Film Transistor) substrate and manufacturing method thereof |
| CN108417583B (en) * | 2018-03-09 | 2021-10-29 | 惠科股份有限公司 | Array substrate and manufacturing method thereof |
| CN110989221B (en) * | 2019-12-20 | 2022-09-06 | 京东方科技集团股份有限公司 | Display substrate, preparation method and repair method thereof and display device |
| CN114280866B (en) * | 2021-12-27 | 2023-03-28 | 苏州华星光电技术有限公司 | Liquid crystal display panel |
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