CN102624273A - Current limiting control method and device for inverter - Google Patents
Current limiting control method and device for inverter Download PDFInfo
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- CN102624273A CN102624273A CN2012101283850A CN201210128385A CN102624273A CN 102624273 A CN102624273 A CN 102624273A CN 2012101283850 A CN2012101283850 A CN 2012101283850A CN 201210128385 A CN201210128385 A CN 201210128385A CN 102624273 A CN102624273 A CN 102624273A
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Abstract
The embodiment of the invention relates to a current limiting control method and a current limiting control device for an inverter. The method comprises the following steps of: when a cycle-by-cycle current limiting enabling signal is valid, turning off an external switching tube of the inverter; turning off an internal switching tube of the inverter; when the cycle-by-cycle current limiting enabling signal is invalid, forcibly conducting the internal switching tube of the inverter for a first delay time; recovering the normal driving logic of the internal switching tube; and recovering the normal driving logic of the external switching tube after a second delay time. According to the current limiting control method and the current limiting control device for the inverter according to the embodiment of the invention, the conduction of the external switching tube is limited within a set fixed time period, so that the short circuit condition of a bus of the inverter within 'dead' time is avoided, and the reliability of a circuit is effectively improved.
Description
Technical field
The embodiment of the invention relates to the wave limiting field, relates in particular to a kind of inverter Current limited Control method and apparatus.
Background technology
Wave limiting is the measure of Switching Power Supply a kind of protection switch pipe commonly used, and impulse waveform detects one by one, surpasses the over-current phenomenon avoidance of setting current value as finding in a pulse period, to have, and just starts current-limiting protection.To be applied as example in the inverter; System's testing circuit detects the electric current that flows through main power inverting switching tube in real time; At shock load or generation output short-circuit, when detecting electric current greater than setting threshold, the comparison circuit that is used for comparison produces wave limiting and enables (protection) signal; System blocks main power inverting switching tube driving pulse immediately and protects the inverse switch pipe; When the electric current that flows through main power inverting switching tube drops to setting threshold when following, main power inverting switching tube driving pulse is blocked in cancellation again, main power inverting switching tube by controller by concrete control method control.The tradition current-limiting method advances current limliting and drives the logical order close and be: close outer switching tube earlier, close interior switching tube again; When withdrawing from the current limliting logic state, go out current limliting and drive the logical order open and be: switching tube in the first positive opening, switching tube and outer switching tube in recovering again.
Yet this most widely used method especially when withdrawing from the current limliting logic state, if can not guarantee during enough " dead band ", can cause the situation of inverter busbar short-circuit to take place when wave limiting is protected.
Summary of the invention
The purpose of the embodiment of the invention is to propose a kind of inverter Current limited Control method and apparatus, is intended to solve when withdrawing from the current limliting logic state, because of can not guaranteeing during enough " dead band ", and causes the situation of inverter busbar short-circuit.
For realizing above-mentioned purpose, the embodiment of the invention provides a kind of inverter Current limited Control method, and said method comprises: when the wave limiting enable signal is effective, close the outer switching tube of inverter; Close the interior switching tube of said inverter; When the wave limiting enable signal was invalid, the interior switching tube of said inverter was forced conducting first delay time; Recover said interior switching tube driven logic; Through recovering said outer switching tube driven logic behind second delay time.
In addition, the embodiment of the invention also provides a kind of inverter current limiting control apparatus, and said device comprises: first closing unit is used for when the wave limiting enable signal is effective, closing the outer switching tube of inverter; Second closing unit is used to close the interior switching tube of said inverter; Force onunit, be used for when the wave limiting enable signal is invalid, force interior switching tube first delay time of the said inverter of conducting; First recovery unit is used to recover said interior switching tube driven logic; Second recovery unit is used for through recovering said outer switching tube driven logic behind second delay time.
The inverter Current limited Control method and apparatus that the embodiment of the invention proposes passes through switching tube conducting outside the restriction in the set time section that is provided with, thereby guarantees during " dead band ", the situation of inverter busbar short-circuit can not occur, has effectively improved the reliability of circuit.
Description of drawings
Fig. 1 is the system block diagram of the inverter Current limited Control method of the embodiment of the invention;
Fig. 2 is the three-level inverter main circuit sketch map of embodiment of the invention inverter Current limited Control method;
Fig. 3 is the flow chart of the inverter Current limited Control method of the embodiment of the invention;
Fig. 4 is the sequential chart of the inverter Current limited Control method of the embodiment of the invention;
Fig. 5 is one of the current limliting situation that withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention;
Fig. 6 is two of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention;
Fig. 7 is three of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention;
Fig. 8 is four of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention;
Fig. 9 is the inverter current limiting control apparatus sketch map of the embodiment of the invention.
Embodiment
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Fig. 1 is the system block diagram of the inverter Current limited Control method of the embodiment of the invention; As shown in Figure 1; The input signal of wave limiting control circuit comprises EN positive-negative half-cycle switching signal; The SPWM drive signal in the two-way band dead band of sending by controller 1, OC wave limiting enable signal, and the SPWM drive signal in the two-way band dead band of controller 1 being sent by controller 2 again four tunnel drive signal Q1PWM, Q2PWM, Q3PWM, the Q4PWM that are divided into according to the tri-level inversion logic.
Fig. 2 is the three-level inverter main circuit sketch map of embodiment of the invention inverter Current limited Control method, and as shown in Figure 2, the three-level inverter of the embodiment of the invention mainly comprises: two dc partial voltage electric capacity, first capacitor C 1, second capacitor C 2; Two clamping diode the 5th diode D5, the 6th diode D6; Four switching tube first switching tube Q1, second switch pipe Q2, the 3rd switching tube Q3, the 4th switching tube Q4, wherein second switch pipe Q2 and the 3rd switching tube Q3 are two interior switching tubes, the first switching tube Q1 and the 4th switching tube Q4 are two outer switching tubes; Four the fly-wheel diode first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4 and LC filters.Said first electric capacity, second electric capacity, first element, second element, element, the series connection of quaternary part; Said first element is by said first diode and the parallel connection of said first switching tube; Said second element is by said second diode and the parallel connection of said second switch pipe; Said element is by said the 3rd diode and the parallel connection of said the 3rd switching tube, and said quaternary part is by said the 4th diode and the parallel connection of said the 4th switching tube; The tie point of said first electric capacity and said second electric capacity is a first node; The tie point of said first element and said second element is a Section Point; Said second element and said three-element tie point are the 3rd node, and the tie point of said element and said quaternary part is the 4th node; Said the 5th diode is between said first node and said Section Point; Said the 6th diode is between said first node and said the 4th node; Said first node ground connection, said the 3rd node also connects said LC filter, and said LC filter comprises the filter inductance L and the filter capacitor C of series connection; Said filter capacitor is used for ground connection, with said first node equipotential.Two dc partial voltage electric capacity, first capacitor C 1, second capacitor C 2 provide two identical direct voltages for circuit, and two clamping diode the 5th diode D5, the 6th diode D6 are used for when two interior switching tubes (second switch pipe Q2, the 3rd switching tube Q3) conducting simultaneously the level pincers in zero potential.Four the fly-wheel diode first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4 are used for controlling the conducting of the first switching tube Q1, second switch pipe Q2, the 3rd switching tube Q3, the 4th switching tube Q4 respectively or closing according to drive signal.
The three-level inverter of the embodiment of the invention; After by controller 2 the SPWM signal in two-way band dead band being become four tunnel drive signals; Four tunnel drive signals are transferred to switching tube Q1, Q2, Q3, Q4 respectively; The first diode D1 controls the conducting of outer switching tube Q1 according to drive signal Q1PWM or closes; The second diode D2 controls the conducting of interior switching tube Q2 according to drive signal Q2PWM or closes, and the 3rd diode D3 controls the conducting of interior switching tube Q3 according to drive signal Q3PWM or closes, and the 4th diode D4 controls the conducting of outer switching tube Q4 according to drive signal Q4PWM or closes.
Fig. 3 is the flow chart of the inverter Current limited Control method of the embodiment of the invention, and Fig. 4 is the sequential chart of the inverter Current limited Control method of the embodiment of the invention, and like Fig. 3, shown in Figure 4, the inverter Current limited Control method of the embodiment of the invention specifically comprises the steps:
Step 101: when the wave limiting enable signal is effective, close the outer switching tube of inverter;
Concrete, before the t1, four switching tubes are in the driven logic state.Testing circuit detects impulse waveform one by one; T1 constantly, when testing circuit detects the electric current during greater than pre-set threshold that flows through main power inverting switching tube, OC signal upset saltus step is a high level; This moment, the wave limiting enable signal was effective, and system gets into the current limliting logic state.Delay time to t2 constantly, the time interval of t1 to t2 can be set, 1us for example, the time interval of t1 to t2 is depended on system design, is mainly used in to confirm whether the OC signal is that external interference produces.After the non-external interference of definite OC signal produces, switching tube outside t2 closes constantly (Q1, Q4), and delay time to the t3 moment; If confirming the OC signal is that external interference produces, then OC signal upset saltus step is detected for the low level continued.
Step 102: the interior switching tube of closing inverter;
Concrete, in the step 101 t2 closes constantly outside switching tube (Q1, Q4), and delay time to the t3 moment; The time interval of t2 to t3 can be set; For example 2us after the time-delay end, closes interior switching tube (Q2, Q3) at t3 constantly; The time interval of t2 to t3 is depended on system design, and switching tube Q2 and Q3 can not take place than the situation of outer switching tube Q1 and Q4 shutoff earlier because of the drive signal transmission delay in requiring to guarantee.
Step 103: when the wave limiting enable signal was invalid, the interior switching tube of inverter was forced conducting first delay time;
Concrete; At t4 constantly; When testing circuit detects the electric current during less than pre-set threshold that flows through main power inverting switching tube, it is that saltus step is a wave limiting enable signal disarmed state that the wave limiting enable signal disappears, and OC signal upset saltus step is a low level; At t4 constantly, open simultaneously in switching tube Q2 and Q3 and delay time to the t5 moment.T4 to t5 constantly between, pipe Q2 all exports high level with Q3 in two, manages Q2 in promptly forcing to make and Q3 all is in conducting state.The time interval of t4 to t5 can be set, 2us for example, the time interval of t4 to t5 is relevant with selected power tube type, and the junction capacitance of two outer switching tubes can both be full of in the interbody spacer at this moment.
Need to prove that the interior switching tube with inverter in the embodiment of the invention is forced conducting to be meant two interior switching tubes of inverter are all opened to be in conducting state.Difference is with the driven logic to force conducting: as shown in Figure 4, and be example with the positive half period, at t1 before the moment; Inside and outside switching tube is under the driven logic state, and Q2 normal open, Q4 are normally closed, and Q1 and Q3 press SPWM complementation conducting; Promptly when the driven logic, interior switching tube Q2 is a conducting state always, but interior switching tube Q3 is alternating conducting or closes; Switching tube Q3 closes a period of time after conducting a period of time promptly, and then closes after the conducting again, goes round and begins again.Switching tube forces conducting to be meant that interior switching tube Q2, Q3 all are in conducting state always in taking, and interior switching tube Q3 no longer replaces the property conducting or closes, until t5 constantly.
Step 104: switching tube driven logic in recovering;
Concrete, in the step 103 t4 opens constantly in pipe Q2 and Q3 and delay time to t5 constantly, after time-delay finishes, at t5 constantly, the interior switching tube driven logic of recovery.Promptly if at positive half period, t5 constantly after, the conducting or close under the effect of drive signal of interior switching tube Q2 normal open, interior switching tube Q3; If at negative half-cycle, t5 constantly after, interior switching tube Q3 is normally closed, interior switching tube Q2 conducting or close under the effect of drive signal;
Step 105: through recovering outer switching tube driven logic behind second delay time.
Concrete, in the step 104 in t5 recovers constantly switching tube driven logic, and delay time to the t6 moment.After time-delay finishes, at t6 constantly, recover two outer switching tubes (Q1, Q4) driven logic.Be t6 constantly after, interior switching tube Q2, Q3 and outer switching tube Q1, Q4 all are in the driven logic state.If at positive half period, t6 constantly after, interior switching tube Q2 normal open, outer switching tube Q4 is normally closed, interior switching tube Q3 and outer switching tube Q1 complementation conducting; If at negative half-cycle, after the moment, interior switching tube Q3 is normally closed at t6, outer switching tube Q1 normal open, interior switching tube Q2 and the complementary conducting of outer switching tube Q4.
The time interval of t5 to t6 can be set, 2us for example, this time interval also is known as " dead band " time period, to prevent switching tube Q1, Q2 and Q3 conducting simultaneously or switching tube Q2, Q3 and Q4 conducting simultaneously, causes the busbar short-circuit of inverter.In order to guarantee " dead band " time period between the t5 to t6, switching tube is in closed condition outside in the time interval of t5 to t6, must making.Therefore switching tube is forbidden conducting outside t6 is before the moment.
As shown in Figure 4 again; If recovered outer tube driven logic constantly at t6; If switching tube Q1 pulsewidth output high level (being dash area among Fig. 4) outside t6 is before the moment; And switching tube Q2 does not close fully in the time period of t5 to t6, then can cause switching tube Q1, Q2 and Q3 conducting simultaneously, thereby causes the busbar short-circuit of inverter.Thereby in order to guarantee " dead band " time period between the t5 to t6, switching tube conducting outside t6 forbade constantly.
Need to prove, in the process that withdraws from current limliting after step 3, be not that all situation all need force to limit outer switching tube in t5 to t6 not conducting in the time interval, is example with positive half cycle, and which situation following mask body discussion has when withdrawing from current limliting.
During positive half cycle, Q2 normal open, Q4 are normally closed, and Q1 and Q3 press SPWM complementation conducting, and guarantee its " dead band ".In withdrawing from the process of current limliting, mainly contain following several kinds of situation:
Fig. 5 is one of the current limliting situation that withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention; As shown in Figure 5, in withdrawing from the process of current limliting, be positioned at constantly as t5 between " dead band " of Q1 → Q3; PWM1 put the high moment be t6 constantly after; T6 constantly outer switching tube do not have conducting, so Q1, Q2 and Q3 while conducting can not appear in t5 to t6 in this time period, cause the situation of busbar short-circuit.
Fig. 6 is two of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention; As shown in Figure 6, in withdrawing from the process of current limliting, t5 is positioned at the interval of Q3 conducting constantly; PWM1 put the high moment be t6 constantly after; Switching tube does not have conducting outside t6 is before the moment, and Q1, Q2 and Q3 conducting simultaneously can not appear in t5 to t6 in this time period, causes the situation of busbar short-circuit.
Fig. 7 is three of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention; As shown in Figure 7, in withdrawing from the process of current limliting, t5 is positioned between " dead band " of Q3 → Q1 constantly; PWM1 put the high moment be t6 constantly before; If recovered outer tube driven logic constantly at t6, then t6 constantly outer switching tube Q1 will export high level, t5 puts the high period to PWM1 and is not enough to guarantee t5 to t6 " dead band " between Q1PWM and the Q3PWM in this time period at this moment; Promptly in Fig. 7, Q1, Q2 and Q3 conducting simultaneously may occur in the zone of dash area, cause the situation of busbar short-circuit.In such cases; In order to guarantee t5 to t6 " dead band " between Q1PWM and the Q3PWM in the time period; Need to force the outer switching tube Q1 of restriction not export high level constantly at t6; Be dash area among Fig. 7, make outer switching tube Q1, thereby guarantee that the phenomenon that can not occur Q1, Q2 and Q3 conducting simultaneously at t5 to t6 in the time period takes place at t5 to the t6 state that still keeps shut in the time period.After the moment, outer switching tube recovers the normal logic that drives at t6, and promptly t6 just allows outer switching tube Q1 output high level constantly later on.
Fig. 8 is for four of the current limliting situation that the withdraws from sketch map of the inverter Current limited Control method of the embodiment of the invention, and is as shown in Figure 8, in withdrawing from the process of current limliting; Be positioned at the interval of Q1 conducting constantly as t5; Do not have " dead band " between Q1PWM and the Q3PWM at t5 to t6 in this time period this moment, promptly in Fig. 8, can occur Q1, Q2 and Q3 while conducting in the zone of dash area, causes the situation of busbar short-circuit; Therefore in such cases; In order to guarantee t5 to t6 " dead band " between Q1PWM and the Q3PWM in this time period, need to force the outer switching tube Q1 of restriction t5 to t6 in the time period not export high level, i.e. dash area among Fig. 8; Make outer switching tube Q1 at t5 to the t6 state that still keeps shut in the time period, thereby guarantee that the phenomenon that can not occur Q1, Q2 and Q3 conducting simultaneously at t5 to t6 in the time period takes place.After the moment, outer switching tube recovers the normal logic that drives at t6, and promptly t6 just allows outer switching tube Q1 output high level constantly later on.
Can find out from several kinds of situation that withdraw from current limliting of the invention described above embodiment inverter Current limited Control method; If outer switching tube recovered the driven logic at t6 constantly then may cause the situation of busbar short-circuit, for example three of the current limliting situation that withdraws from of the inverter Current limited Control method of the embodiment of the invention and four.Therefore the inverter Current limited Control method of the embodiment of the invention is passed through switching tube conducting outside the restriction in the set time section that is provided with, thereby guarantees during " dead band ", the situation of inverter busbar short-circuit can not occur, has effectively improved the reliability of circuit.
The embodiment of the invention also provides a kind of inverter current limiting control apparatus; Fig. 9 is the inverter current limiting control apparatus sketch map of the embodiment of the invention; As shown in Figure 9, the inverter current limiting control apparatus of the embodiment of the invention comprises: first closing unit 91, second closing unit 92, force onunit 93, first recovery unit 94, preset unit 95, second recovery unit 96.
Referring to Fig. 3, shown in Figure 4, the inverter current limiting control apparatus that the embodiment of the invention proposes, t1 are constantly in the lump; When testing circuit detected overcurrent, OC signal upset saltus step was a high level, delayed time to the t2 moment; After the non-external interference of definite OC signal produces; First closing unit is closed two outer switching tubes of inverter, and delays time to the t3 moment, and the time interval of t2 to t3 is 2us; At t3 constantly, second closing unit is closed two interior switching tubes of inverter, gets into the current limliting logic state; T4 is that saltus step is wave limiting enable signal when invalid when the wave limiting enable signal disappears constantly, and OC signal upset saltus step is a low level, forces two the interior switching tube conductings of onunit with inverter, and delay time to t5 constantly; At t5 constantly, switching tube driven logic in first recovery unit recovers; Be set to " dead band " time period of t6 between the moment t5 moment, switching tube conducting outside t6 limited constantly, thus prevent that said interior switching tube and outer switching tube from causing the busbar short-circuit of said inverter in the synchronization conducting; Preset unit is provided with said outer switching tube in advance and recovers the driven logical time; Second recovery unit is switching tube driven logic outside t6 recovers constantly.
The professional should further recognize; The unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein; Can realize with electronic hardware, computer software or the combination of the two; For the interchangeability of hardware and software clearly is described, the composition and the step of each example described prevailingly according to function in above-mentioned explanation.These functions still are that software mode is carried out with hardware actually, depend on the application-specific and the design constraint of technical scheme.The professional and technical personnel can use distinct methods to realize described function to each certain applications, but this realization should not thought and exceeds scope of the present invention.
The software module that the method for describing in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to carry out, perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
Above-described embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely embodiment of the present invention; And be not used in qualification protection scope of the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. inverter Current limited Control method is characterized in that said method comprises:
When the wave limiting enable signal is effective, close the outer switching tube of inverter;
Close the interior switching tube of said inverter;
When the wave limiting enable signal was invalid, the interior switching tube of said inverter was forced conducting first delay time;
Recover said interior switching tube driven logic;
Through recovering said outer switching tube driven logic behind second delay time.
2. inverter Current limited Control method according to claim 1 is characterized in that, it is 2us that the interior switching tube of said inverter is forced conducting first delay time.
3. inverter Current limited Control method according to claim 1 is characterized in that, said is to recover said outer switching tube driven logic behind the 2us through second delay time.
4. inverter Current limited Control method according to claim 1 is characterized in that, also comprises before the said outer switching tube driven logic of said recovery, said outer switching tube is set in advance recovers the driven logical time.
5. an inverter current limiting control apparatus is characterized in that, said device comprises:
First closing unit is used for when the wave limiting enable signal is effective, closing the outer switching tube of inverter;
Second closing unit is used to close the interior switching tube of said inverter;
Force onunit, be used for when the wave limiting enable signal is invalid, force interior switching tube first delay time of the said inverter of conducting;
First recovery unit is used to recover said interior switching tube driven logic;
Second recovery unit is used for through recovering said outer switching tube driven logic behind second delay time.
6. inverter current limiting control apparatus according to claim 5 is characterized in that, said device also comprises: preset unit is used for being provided with in advance said outer switching tube and recovers the driven logical time.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102868291A (en) * | 2012-09-19 | 2013-01-09 | 华为技术有限公司 | Diode neutral point clamped three-level inverter current limiting control method and related circuit thereof |
| CN104993681A (en) * | 2015-06-26 | 2015-10-21 | 深圳科士达科技股份有限公司 | Cycle-by-cycle current limiting method |
| WO2015158050A1 (en) * | 2014-04-17 | 2015-10-22 | 成都麦隆电气有限公司 | Cycle-by-cycle current limiting method and apparatus with short pulse suppression function |
| CN106230292A (en) * | 2016-08-17 | 2016-12-14 | 阳光电源股份有限公司 | The pwm pulse of a kind of three-level inverter puts wave method and controller |
| US9906120B2 (en) | 2014-07-25 | 2018-02-27 | Huawei Technologies Co., Ltd. | Overcurrent protection system and method for inverter circuit |
| CN109873556A (en) * | 2017-12-01 | 2019-06-11 | 维谛技术有限公司 | A kind of Current limited Control method and apparatus of three-level inverter |
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| CN101588124A (en) * | 2008-05-23 | 2009-11-25 | 力博特公司 | Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter |
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| CN101588124A (en) * | 2008-05-23 | 2009-11-25 | 力博特公司 | Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868291A (en) * | 2012-09-19 | 2013-01-09 | 华为技术有限公司 | Diode neutral point clamped three-level inverter current limiting control method and related circuit thereof |
| CN102868291B (en) * | 2012-09-19 | 2015-08-19 | 华为技术有限公司 | Diode neutral point clamp type three-level inverter Current limited Control method and interlock circuit |
| US9531185B2 (en) | 2012-09-19 | 2016-12-27 | Huawei Technologies Co., Ltd. | Current limiting control method for diode neutral-point-clamped three-level inverter and related circuit |
| WO2015158050A1 (en) * | 2014-04-17 | 2015-10-22 | 成都麦隆电气有限公司 | Cycle-by-cycle current limiting method and apparatus with short pulse suppression function |
| US9906120B2 (en) | 2014-07-25 | 2018-02-27 | Huawei Technologies Co., Ltd. | Overcurrent protection system and method for inverter circuit |
| CN104993681A (en) * | 2015-06-26 | 2015-10-21 | 深圳科士达科技股份有限公司 | Cycle-by-cycle current limiting method |
| CN106230292A (en) * | 2016-08-17 | 2016-12-14 | 阳光电源股份有限公司 | The pwm pulse of a kind of three-level inverter puts wave method and controller |
| CN106230292B (en) * | 2016-08-17 | 2019-02-01 | 阳光电源股份有限公司 | A kind of pwm pulse of three-level inverter puts wave method and controller |
| CN109873556A (en) * | 2017-12-01 | 2019-06-11 | 维谛技术有限公司 | A kind of Current limited Control method and apparatus of three-level inverter |
| US10594208B2 (en) | 2017-12-01 | 2020-03-17 | Vertiv Tech Co., Ltd. | Current limiting control method and device for three-level inverter |
| CN109873556B (en) * | 2017-12-01 | 2020-03-17 | 维谛技术有限公司 | Current-limiting control method and device of three-level inverter |
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