CN102623058A - Erasing voltage generation circuit and method of nonvolatile memory - Google Patents
Erasing voltage generation circuit and method of nonvolatile memory Download PDFInfo
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Abstract
The application discloses erasing voltage generation circuit and method of a nonvolatile memory. The erasing voltage generation circuit of the nonvolatile memory comprises an analog-digital conversion unit, a logic control unit, a voltage control unit and a voltage generation unit, wherein the analog-digital conversion unit is used for monitoring supply voltage and converting the supply voltage into a corresponding logic control signal according to preset rules; the logic control unit is used for acquiring the variation difference of the supply voltage when the logic control signal changes and generating an erasing voltage control signal according to the difference; the voltage control unit is used for outputting a corresponding controlled voltage value according to the erasing voltage control signal; and according to the controlled voltage value, the voltage generation unit is used for outputting the final word line voltage and the P-well voltage, which are required during erosion. According to the application, the problem of un-erased PWELL-STRESS of the nonvolatile memory unit can be reduced and even avoided, and the erased threshold voltage of the nonvolatile memory unit is surely distributed within the expectant range.
Description
Technical field
The application relates to the semiconductor memory technologies field, and the erasing voltage that particularly relates to a kind of nonvolatile memory produces circuit, a kind of nonvolatile memory, and, a kind of erasing voltage production method of nonvolatile memory.
Background technology
Along with developing rapidly and widespread use of various electronic installations and embedded system; Like computing machine, personal digital assistant, mobile phone, digital camera etc.; Need a kind of can repeatedly the programming in a large number, capacity is big, reads and writes, wipes quick and easy, simple; Peripheral components is few, the memory device of cheap non-volatile (under powering-off state, still can keep institute's data information stored).Nonvolatile semiconductor memory member arises at the historic moment under this background demand.A nonvolatile memory also is a metal-oxide-semiconductor usually, has a source electrode (source), a drain electrode (drain), and a grid (gate) also has a floating grid (floating gate) in addition.It is thus clear that its structure is slightly different with general metal-oxide-semiconductor, many floating grids, this floating grid insulated body isolates from other parts.
(Flash Memory) is example with flash memory; It is a kind of nonvolatile memory of based semiconductor; Have and still can keep internal information, online functional characteristics such as erasable after system's power down, flash memory injects mechanism through thermoelectron to be realized device programming, adopts tunnel effect (Fower-Nordheim tunneling; FN mechanism) realize wiping, flash memory to wipe with a sector (sector) or several sector be that unit carries out.Tunnel effect is meant; On grid, add a higher negative voltage, on PWELL (P trap, P substrate), add a higher positive voltage; So just make and have a very strong electric field between floating grid and the PWELL; This electric field can enable band and change, and then to the electronics on the floating grid path that arrives PWELL is provided, thereby accomplishes the erase operation to cell (storage unit).
Between erasing period; The word-line of the non-volatile memory cells that preparation is wiped (word line) voltage be a negative pressure (as-8V); (way of cell is PWELL voltage among the flash, at first does a dark N trap, does a P trap again in dark N trap the inside; PWELL voltage promptly is applied to the voltage on this P trap, and last cell is made in this P trap) and source voltage connect together malleation (as+8V); And the word-line voltage of the non-volatile memory cells that is not wiped free of is supply voltage, and PWELL voltage and source voltage connect malleation equally.When chip operation, the scope that supply voltage allow to change is bigger, the nonvolatile memory of 1.8V for example, and it is 1.4V to 2.5V that supply voltage allows variation range.Like this, the word-line voltage of the non-volatile memory cells that preparation is wiped and PWELL voltage all are to confirm voltage, can not have problems; But for the non-volatile memory cells that is not wiped free of, because with mains voltage variations, will there be the PWELL-STRESS problem in word-line.
Particularly, the PWELL-STRESS problem is meant and since among the flash cell to wipe with sector be that unit carries out, a plurality of sector have constituted a big physics block (piece), they are made in the same P trap.Like this when some sector are wiped; Be applied to the P trap voltage on this sector, equally also can be applied on other the sector, and this condition can produce more weak erasure effect to the cell in other sector; Finally possibly change user's storing value, therefore must avoid.
In the lower nonvolatile memory of supply voltage, for example, be in the product of 1.8V at supply voltage; Variation along with supply voltage; The non-volatile memory cells that is not wiped free of not only can meet with the PWELL-STRESS problem, and supply voltage is low more, and the voltage difference between PWELL and the word-line is big more; The influence of PWELL-STRESS is also remarkable more, thereby possibly cause the threshold voltage of these memory cells to change.
Therefore; Need the urgent technical matters that solves of those skilled in the art to be exactly at present: the erasing voltage generation mechanism that how can propose a kind of nonvolatile memory with innovating; In order to the PWELL-STRESS problem of the non-volatile memory cells that weakens even avoid not being wiped free of, and the threshold voltage of the non-volatile memory cells that guarantees to be wiped free of can be distributed in the desired extent.
Summary of the invention
The application's technical matters to be solved provides a kind of circuit and method of erasing voltage generation of nonvolatile memory; And a kind of nonvolatile memory; In order to the PWELL-STRESS problem of the non-volatile memory cells that weakens even avoid not being wiped free of, and the threshold voltage of the non-volatile memory cells that guarantees to be wiped free of can be distributed in the desired extent.
In order to solve the problems of the technologies described above, the erasing voltage that the application embodiment discloses a kind of nonvolatile memory produces circuit, comprising:
AD conversion unit is used to monitor supply voltage, and converts said supply voltage into corresponding logic control signal by preset rules;
Logic control element is used for when said logic control signal changes, and obtains the variation difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit is used for according to said erasing voltage adjustment signal, the corresponding adjustment of output magnitude of voltage;
Voltage generating unit, the final word line voltage and the P trap voltage of needs when being used for according to said adjustment magnitude of voltage output erase operation.
Preferably, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
Preferably, said erasing voltage adjustment signal comprises reference voltage and multiple parameter, and said voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, is used for generating corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Voltage output subelement is used to export said adjustment magnitude of voltage.
Preferably, said adjustment magnitude of voltage is positive voltage value or negative value, and said voltage generating unit comprises:
First regulates subelement; Be used for when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Second regulates subelement; Be used for when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
Preferably, said AD conversion unit is an analog to digital converter.
The application embodiment also discloses a kind of nonvolatile memory, comprises in the said nonvolatile memory that the erasing voltage that links to each other with storage unit produces circuit, and said erasing voltage produces circuit and comprises:
AD conversion unit is used to monitor supply voltage, and converts said supply voltage into corresponding logic control signal by preset rules;
Logic control element is used for when said logic control signal changes, and obtains the variation difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit is used for according to said erasing voltage adjustment signal, the corresponding adjustment of output magnitude of voltage;
Voltage generating unit, the final word line voltage and the P trap voltage of needs when being used for according to said adjustment magnitude of voltage output erase operation.
Preferably, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
Preferably, said erasing voltage adjustment signal comprises reference voltage and multiple parameter, and said voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, is used for generating corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Voltage output subelement is used to export said adjustment magnitude of voltage.
Preferably, said adjustment magnitude of voltage is positive voltage value or negative value, and said voltage generating unit comprises:
First regulates subelement; Be used for when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Second regulates subelement; Be used for when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
The application embodiment also discloses a kind of erasing voltage production method of nonvolatile memory, comprising:
Monitor supply voltage, and convert said supply voltage into corresponding logic control signal by preset rules;
When said logic control signal changes, obtain the variation difference of supply voltage, and generate erasing voltage adjustment signal according to this difference;
According to the corresponding adjustment of said erasing voltage adjustment signal output magnitude of voltage;
The final word line voltage and the P trap voltage of needs when exporting erase operation according to said adjustment magnitude of voltage.
Preferably, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
Preferably, said voltage adjustment signal comprises reference voltage and multiple parameter, and said step according to the corresponding adjustment of erasing voltage adjustment signal output magnitude of voltage comprises:
Generate corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Export said adjustment magnitude of voltage.
Preferably, said adjustment magnitude of voltage is positive voltage value or negative value, said during according to adjustment magnitude of voltage output erase operation the final word line voltage of needs and the step of P trap voltage comprise:
When said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
When said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
Compared with prior art, the application has the following advantages:
The application regulates the word-line voltage and the PWELL voltage of the non-volatile memory cells that is not wiped free of according to supply voltage; Make when mains voltage variations; PWELL voltage between erasing period also changes accordingly; And the change direction of PWELL voltage and supply voltage is consistent, and is constant with the difference of guaranteeing both, and the PWELL-STRESS of the non-volatile memory cells that is not wiped free of is weakened.Simultaneously between erasing period; The word-line voltage and the PWELL voltage of the non-volatile memory cells that is wiped free of also need be done corresponding adjusting; Its change direction is consistent with the direction of supply voltage; Difference to guarantee PWELL voltage and word-line voltage is constant, and the threshold voltage that is wiped free of memory cell like this can be distributed in the desired extent.
Moreover; In the higher nonvolatile memory of supply voltage; Such as being in the nonvolatile memory chip of 3.3V at supply voltage, chip internal has a regulator (voltage adjuster), can produce a lower slightly burning voltage (about 2.0V) according to supply voltage; This magnitude of voltage substantially constant; The fluctuation with supply voltage does not change, and this voltage is added on the word-line of not selected non-volatile memory cells between erasing period, therefore possibly not have serious PWELL-STRESS problem at the higher nonvolatile memory product of supply voltage.Yet; In the lower nonvolatile memory of supply voltage, such as, be in 1.8V even the lower nonvolatile memory chip at supply voltage; The integrated regulator of chip internal produces the burning voltage complicated technology realization of 2V, and cost is improved greatly.Adopt the application embodiment; Can be so that the word line voltage of storage unit and P trap voltage be all followed the variation of supply voltage; And the voltage difference between them remains unchanged basically; Thereby make the threshold voltage distribution be wiped free of memory cell in desired extent, and weaken even the PWELL-STRESS problem of the non-volatile memory cells avoiding not being wiped free of.
Description of drawings
Fig. 1 is the structured flowchart that the erasing voltage of a kind of nonvolatile memory of the application produces circuit embodiments;
Fig. 2 is the synoptic diagram of realization examples of circuits of a kind of A/D converter of the application;
Fig. 3 is the flow chart of steps of erasing voltage production method embodiment of a kind of nonvolatile memory of the application.
Embodiment
For above-mentioned purpose, the feature and advantage that make the application can be more obviously understandable, the application is done further detailed explanation below in conjunction with accompanying drawing and embodiment.
At present, there is the problem of PWELL-STRESS in the erase operation of flash memory, when promptly some sectors of flash memory being wiped, need add negative pressure to grid, and source electrode and P trap are added certain malleation.The electric field that added voltage forms has caused a potential barrier, and it provides a path by floating grid arrival P trap for the electronics in the floating grid, thereby changes the logic state of storage unit (cell), realizes wiping.
Owing to generally include a plurality of sectors (sector) in the storage block (block); Yet the malleation that the P trap adds can be added on all cell in the storage block; In this case; Added voltage can produce interference for the cell in other sector of not doing erase operation, thereby influences data stability and reliability among the cell.Prevent when target sector is carried out erase operation,, improve data stability and reliability in the storage unit not doing the interference that other sectors produced of wiping in the same storage block.
For example; At supply voltage is in the nonvolatile memory of 1.8V, and along with the variation of supply voltage, the storage unit that is not wiped free of can meet with the PWELL-STRESS problem; And supply voltage is low more; Voltage difference between PWELL and the word-line is big more, and the influence of PWELL-STRESS is also remarkable more, thereby possibly cause the threshold voltage of these memory cells to change.
Therefore; For overcoming the influence of PWELL-STRESS; The inventor herein has proposed a kind of brand-new solution thinking: word-line voltage and the PWELL voltage of promptly regulating the non-volatile memory cells that is not wiped free of according to supply voltage; Make that when mains voltage variations the PWELL voltage between erasing period also changes accordingly, and the change direction of PWELL voltage and supply voltage is consistent; Difference to guarantee both is constant, and the PWELL-STRESS of the non-volatile memory cells that is not wiped free of is weakened.Simultaneously between erasing period; The word-line voltage and the PWELL voltage of the non-volatile memory cells that is wiped free of also need be done corresponding adjusting; Its change direction is consistent with the direction of supply voltage; Difference to guarantee PWELL voltage and word-line voltage is constant, and the threshold voltage that is wiped free of memory cell like this can be distributed in the desired extent.
With reference to figure 1, the erasing voltage that shows a kind of nonvolatile memory of the application produces the structured flowchart of circuit embodiments, specifically can comprise like lower unit:
Voltage-adjusting unit 103 is used for according to said erasing voltage adjustment signal, the corresponding adjustment of output magnitude of voltage;
In concrete the realization, said AD conversion unit 101 can be well known that for an A/D converter (ADC), and A/D converter is to be the digital signal of an output with an input analog signal conversion.In the application embodiment, said A/D converter can link to each other with the voltage offset electric circuit (not shown), and input is the supply voltage as simulating signal, and output is the logic control signal as digital signal.In practical application, said A/D converter according to different supply voltage values, produces the output of logical controlling signal with the variation of continuous monitoring supply voltage VDD, and in fact these logic control signals have represented different supply voltage states.
Mould/number conversion generally will be through over-sampling, maintenance, quantification and 4 processes of encoding.In side circuit, some process merges carries out, and like sampling and maintenance, quantizes and be coded in the transfer process to realize simultaneously.Quantification is that the simulating signal range is divided into many discrete magnitudes, and the magnitude under definite input signal.Coding is that each magnitude is distributed unique numerical code, and confirms and the corresponding code of input signal.Prevailing code system is a scale-of-two, and it has a n power magnitude (n is a figure place) of 2, can number one by one successively.
Analog-to-digital method is a lot, divides from transfer principle to be divided into direct method and indirect method two big classes.Direct method is directly voltage transitions to be become digital quantity.It compares with tested voltage from a high position with a cover reference voltage of digital-to-analogue network output by turn repeatedly, reaches or near balance up to the two.Steering logic can realize the control of dichotomous search, and its comparative approach is weighed as balance.Make the most significant digit Dn-1=1 of binary system number earlier, after analog to digital conversion, obtain the half the aanalogvoltage VS of a whole range, compare, if Vin＞VS then keeps this position with input voltage vin; If Vin＜Vs, then Dn-1=0.Making next bit Dn-2=1 then, compare with Vin after analog to digital conversion with the result of last time, repeat this process, up to making D0=1, compare with Vin again, still is that Vin＜VS determines whether keeping this position by Vin＞VS.After process compared for n time, the state of n bit register was the data after the conversion.
What reference was shown in Figure 2 is a kind of synoptic diagram of A/D converter; Collect the input voltage IN of comparer through power supply potential-divider network (resistance R 0, R1, R2, R3, R4 only are shown); Compare through comparer I0, I1, I2 respectively from high-order n and reference voltage V REF; Obtain output signal OUT, in output logic, carry out mould/number conversion control, obtain final digital signal according to this output signal OUT.
It is understandable that; In the application embodiment; Said preset rules promptly refers to the supply voltage at least two numerical value intervals and the one-to-one relationship of at least two Different Logic control signals, in reality, can confirm through the precision that the A/D converter conversion is set.The precision of A/D converter conversion, how much the figure place of the digital signal of usefulness output representes usually.With 2bit is example, and corresponding relation can be as shown in the table:
| Supply voltage | Logic control signal VO < 1:0 > |
| vdd＜1.6V | 00 |
| 1.6V＜vdd＜1.8V | 01 |
| 1.8V＜vdd＜2.0 |
10 |
| 2.0V＜vdd | 11 |
In practical application; Performances such as the precision of said A/D converter, speed can be confirmed according to the system design index by those skilled in the art; For example, those skilled in the art can adopt the ADC of indirect method, and this kind ADC is not directly changed into numeral with voltage; But at first convert a certain intermediate quantity to, convert numeral to by intermediate quantity again.Commonly used have two kinds on voltage-time interval (V/T) type and voltage-frequency (V/F) type, and wherein the dual slope method (claiming the biproduct point-score again) in voltage-time interval type is used comparatively generally; Perhaps, those skilled in the art can adopt other accuracy A DC, and as 8,16,128 etc., the application need not this to limit.
In concrete the realization, along with the development of large scale integrated circuit technology, the analog to digital converter volume is reduced into a template, an integrated circuit gradually, therefore can't too much take the area of storer, and cost is also lower.
When nonvolatile memory carries out erase operation; If supply voltage VDD is unstable; For example between 1.4V to 2.3V, change; In order to overcome PWELL_STRESS, and reduce the cell threshold voltage distribution, need the word-line voltage of cell and PWELL voltage to do corresponding adjustment; To guarantee the difference constant (relevant) between PWELL voltage and the supply voltage VDD, guarantee that simultaneously the difference between PWELL voltage and the word-line voltage is constant (relevant with the threshold distribution of cell) with PWELL_STRESS.Therefore, when carrying out erase operation, change, then trigger logic control element 102 if AD conversion unit monitors supply voltage VDD.In concrete the realization; Said logic control element 102 can be designed as a digital control circuit; It receives the logic control signal of AD conversion unit 101 outputs; And when said logic control signal changes, obtain the variation difference of supply voltage, and generate erasing voltage adjustment signal according to this difference; For example; Difference when inferior supply voltage that monitors and the supply voltage that monitored last time; And according to this difference generation erasing voltage adjustment signal; These erasing voltage adjustment signals will be adjusted the generation and the output of magnitude of voltage by voltage-adjusting unit 103 usefulness, and these adjustment magnitudes of voltage have relation one to one with corresponding supply voltage.The final word line voltage and the P trap voltage of needs when voltage generating unit 104 will be adjusted magnitude of voltage output erase operation according to these.
In a kind of preferred embodiment of the application, said erasing voltage adjustment signal can comprise reference voltage and multiple parameter, and said voltage-adjusting unit 103 can comprise following subelement:
Magnitude of voltage generates subelement, is used for generating corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Voltage output subelement is used to export said adjustment magnitude of voltage.
Use present embodiment; Said voltage generating unit 104 can be a charge pump circuit; Charge pump; Be a kind of utilize so-called " fast " (flying) or " pumping " electric capacity (but not inductance or transformer) come the DC-DC (transducer) of energy storage. they can make input voltage raise or reduce, and also can be used to produce negative voltage.Its inner FET switch arrays are controlled the charging and the discharge of flying capacitor in a certain way, thereby make input voltage with certain factor (0.5,2 or 3 etc.) multiplication or reduce, thereby obtain needed output voltage.
In concrete the realization, the adjustment magnitude of voltage can be produced by negative-feedback circuit.This negative-feedback circuit comprises output voltage detecting circuit and comparator circuit; Wherein, Output voltage detecting circuit; Be used for constantly detecting the variation of charge pump output voltage, and the output voltage values and the reference voltage that detect are compared through comparator circuit, the work that the output signal of comparer is then controlled charge pump circuit whether.
The output voltage values of charge pump is the integral multiple of reference voltage normally, and for example, if reference voltage is 1.2V, then output voltage is (1.2*N) V, and N is an integer.This shows that the control module among the application embodiment through logic control signal, makes negative-feedback circuit select different reference voltages and different integral multiples, can determine to produce which kind of magnitude of voltage under different supply voltage VDD.
Certainly; The application's control module also is not limited to a certain specific implementation; As long as institute's target that will reach be the digital signal of employing AD conversion unit as input control signal, and then select corresponding reference voltage and integer multiple, reach this function and get final product.
In concrete the realization, said adjustment magnitude of voltage is positive voltage value or negative value, and in this case, said voltage generating unit 104 can comprise following subelement:
First regulates subelement; Be used for when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Second regulates subelement; Be used for when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
For example, when supply voltage was 1.8V, PWELL voltage was 8V, and word-line voltage is-9V; When supply voltage became 1.6V, PWELL voltage reduced 0.2V (being 7.8V) accordingly, and word-line voltage also reduces 0.2V (promptly-9.2V).The PWELL voltage under the both of these case and the difference of supply voltage all are 6.2V, and by contrast, PWELL_STRESS can not worsen; The difference of PWELL voltage and word-line voltage all is 17V simultaneously, and the variation range of this difference is narrow more, and the threshold distribution of cell also can be concentrated more.
During concrete the application; In the higher nonvolatile memory of supply voltage; Such as being in the nonvolatile memory chip of 3.3V at supply voltage, chip internal has a regulator (voltage adjuster), can produce a lower slightly burning voltage (about 2.0V) according to supply voltage; This magnitude of voltage substantially constant; The fluctuation with supply voltage does not change, and this voltage is added on the word-line of not selected non-volatile memory cells between erasing period, therefore possibly not have serious PWELL-STRESS problem at the higher nonvolatile memory product of supply voltage.Yet; In the lower nonvolatile memory of supply voltage, such as, be in 1.8V even the lower nonvolatile memory chip at supply voltage; The integrated regulator of chip internal produces the burning voltage complicated technology realization of 2V, and cost is improved greatly.Adopt the application embodiment; Can be so that the word line voltage of storage unit and P trap voltage be all followed the variation of supply voltage; And the voltage difference between them remains unchanged basically; Thereby make the threshold voltage distribution be wiped free of memory cell in desired extent, and weaken even the PWELL-STRESS problem of the non-volatile memory cells avoiding not being wiped free of.Therefore the application is particularly useful for the nonvolatile memory under the low supply voltage.
The erasing voltage that the application proposed produces circuit and can be integrated in very simply in the nonvolatile memory; Be that the application has also proposed a kind of nonvolatile memory, in this nonvolatile memory, comprise that the erasing voltage that links to each other with storage unit produces circuit; And; Said erasing voltage produces circuit can comprise unit shown in Figure 1, gets final product with reference to the relevant portion in the preceding text about the relevant introduction of each unit, and the application does not give unnecessary details at this.
With reference to figure 3, show the flow chart of steps of erasing voltage production method embodiment of a kind of nonvolatile memory of the application, specifically can comprise the steps:
In concrete the realization, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules can be the supply voltage at least two numerical value intervals and the one-to-one relationship of at least two Different Logic control signals.
In a kind of preferred embodiment of the application, said voltage adjustment signal comprises reference voltage and multiple parameter, and said step according to the corresponding adjustment of erasing voltage adjustment signal output magnitude of voltage comprises following substep:
Generate corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Export said adjustment magnitude of voltage.
As the concrete a kind of example used of the application embodiment; Said adjustment magnitude of voltage is positive voltage value or negative value; In this case, saidly specifically can comprise following substep according to the final word line voltage of output needs during erase operation and the step of P trap voltage:
Substep S1, when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Substep S2, when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
In concrete the application, said adjustment magnitude of voltage is identical with the variation difference of supply voltage.And the application is particularly useful for the nonvolatile memory of low supply voltage.
Need to prove; For aforesaid method embodiment, for simple description, so it all is expressed as a series of combination of actions; But those skilled in the art should know; The application does not receive the restriction of described sequence of movement, because according to the application, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the application is necessary.
For method embodiment, because it is similar basically with embodiment of circuit shown in Figure 1, so description is fairly simple, relevant part gets final product referring to the part explanation of previous embodiment.
At last; Also need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
More than the erasing voltage of a kind of nonvolatile memory that the application provided is produced circuit; A kind of nonvolatile memory; And; A kind of erasing voltage production method of nonvolatile memory has carried out detailed introduction, has used concrete example among this paper the application's principle and embodiment are set forth, and the explanation of above embodiment just is used to help to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to the application's thought, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as the restriction to the application.
Claims (13)
1. the erasing voltage of a nonvolatile memory produces circuit, it is characterized in that, comprising:
AD conversion unit is used to monitor supply voltage, and converts said supply voltage into corresponding logic control signal by preset rules;
Logic control element is used for when said logic control signal changes, and obtains the variation difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit is used for according to said erasing voltage adjustment signal, the corresponding adjustment of output magnitude of voltage;
Voltage generating unit, the final word line voltage and the P trap voltage of needs when being used for according to said adjustment magnitude of voltage output erase operation.
2. circuit as claimed in claim 1 is characterized in that, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
3. circuit as claimed in claim 2 is characterized in that, said erasing voltage adjustment signal comprises reference voltage and multiple parameter, and said voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, is used for generating corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Voltage output subelement is used to export said adjustment magnitude of voltage.
4. like claim 1,2 or 3 described circuit, it is characterized in that said adjustment magnitude of voltage is positive voltage value or negative value, said voltage generating unit comprises:
First regulates subelement; Be used for when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Second regulates subelement; Be used for when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
5. circuit as claimed in claim 4 is characterized in that, said AD conversion unit is an analog to digital converter.
6. a nonvolatile memory is characterized in that, comprises in the said nonvolatile memory that the erasing voltage that links to each other with storage unit produces circuit, and said erasing voltage produces circuit and comprises:
AD conversion unit is used to monitor supply voltage, and converts said supply voltage into corresponding logic control signal by preset rules;
Logic control element is used for when said logic control signal changes, and obtains the variation difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit is used for according to said erasing voltage adjustment signal, the corresponding adjustment of output magnitude of voltage;
Voltage generating unit, the final word line voltage and the P trap voltage of needs when being used for according to said adjustment magnitude of voltage output erase operation.
7. nonvolatile memory as claimed in claim 6 is characterized in that, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
8. nonvolatile memory as claimed in claim 7 is characterized in that, said erasing voltage adjustment signal comprises reference voltage and multiple parameter, and said voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, is used for generating corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Voltage output subelement is used to export said adjustment magnitude of voltage.
9. like claim 6,7 or 8 described nonvolatile memorys, it is characterized in that said adjustment magnitude of voltage is positive voltage value or negative value, said voltage generating unit comprises:
First regulates subelement; Be used for when said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
Second regulates subelement; Be used for when said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage, according to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
10. the erasing voltage production method of a nonvolatile memory is characterized in that, comprising:
Monitor supply voltage, and convert said supply voltage into corresponding logic control signal by preset rules;
When said logic control signal changes, obtain the variation difference of supply voltage, and generate erasing voltage adjustment signal according to this difference;
According to the corresponding adjustment of said erasing voltage adjustment signal output magnitude of voltage;
The final word line voltage and the P trap voltage of needs when exporting erase operation according to said adjustment magnitude of voltage.
11. method as claimed in claim 10 is characterized in that, said supply voltage is a simulating signal, and said logic control signal is a digital signal; Said preset rules is the one-to-one relationship of the interval supply voltage of at least two numerical value and at least two Different Logic control signals.
12. method as claimed in claim 11 is characterized in that, said voltage adjustment signal comprises reference voltage and multiple parameter, and said step according to the corresponding adjustment of erasing voltage adjustment signal output magnitude of voltage comprises:
Generate corresponding adjustment magnitude of voltage according to said reference voltage and multiple parameter;
Export said adjustment magnitude of voltage.
13., it is characterized in that said adjustment magnitude of voltage is positive voltage value or negative value like claim 10,11 or 12 described methods, said during according to adjustment magnitude of voltage output erase operation the final word line voltage of needs and the step of P trap voltage comprise:
When said adjustment magnitude of voltage is positive voltage value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage increase storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output;
When said adjustment magnitude of voltage is negative value; On the basis of initial word line voltage and P trap voltage; According to the word line voltage and the P trap voltage of said adjustment magnitude of voltage minimizing storage unit, final word line voltage that needs when generating erase operation and P trap voltage and output.
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| CN102937935A (en) * | 2012-09-04 | 2013-02-20 | 邹粤林 | Solid state storage system, controller and method for prolonging service life of flash memory chips |
| CN103839586A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for regulating erasing voltage of nonvolatile memory |
| CN104572324A (en) * | 2013-10-11 | 2015-04-29 | 光宝科技股份有限公司 | Solid-state storage device and control method thereof |
| CN117407927A (en) * | 2023-12-15 | 2024-01-16 | 山东万里红信息技术有限公司 | Hard disk data destruction method, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102937935A (en) * | 2012-09-04 | 2013-02-20 | 邹粤林 | Solid state storage system, controller and method for prolonging service life of flash memory chips |
| CN104572324A (en) * | 2013-10-11 | 2015-04-29 | 光宝科技股份有限公司 | Solid-state storage device and control method thereof |
| CN103839586A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for regulating erasing voltage of nonvolatile memory |
| CN103839586B (en) * | 2014-03-17 | 2017-04-05 | 上海华虹宏力半导体制造有限公司 | The method of adjustment of nonvolatile memory erasing voltage |
| CN117407927A (en) * | 2023-12-15 | 2024-01-16 | 山东万里红信息技术有限公司 | Hard disk data destruction method, computer equipment and storage medium |
| CN117407927B (en) * | 2023-12-15 | 2024-03-22 | 山东万里红信息技术有限公司 | Hard disk data destruction method, computer equipment and storage medium |
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