CN102622329B - 多核计算机中的远程核操作 - Google Patents
多核计算机中的远程核操作 Download PDFInfo
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- CN102622329B CN102622329B CN201210030338.2A CN201210030338A CN102622329B CN 102622329 B CN102622329 B CN 102622329B CN 201210030338 A CN201210030338 A CN 201210030338A CN 102622329 B CN102622329 B CN 102622329B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Mathematical Physics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/025,446 US9471532B2 (en) | 2011-02-11 | 2011-02-11 | Remote core operations in a multi-core computer |
US13/025,446 | 2011-02-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102622329A CN102622329A (zh) | 2012-08-01 |
CN102622329B true CN102622329B (zh) | 2015-12-02 |
Family
ID=46562253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210030338.2A Active CN102622329B (zh) | 2011-02-11 | 2012-02-10 | 多核计算机中的远程核操作 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9471532B2 (zh) |
EP (1) | EP2673717A4 (zh) |
CN (1) | CN102622329B (zh) |
HK (1) | HK1174116A1 (zh) |
TW (1) | TWI473013B (zh) |
WO (1) | WO2012109631A2 (zh) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
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US9596222B2 (en) | 2011-08-02 | 2017-03-14 | Cavium, Inc. | Method and apparatus encoding a rule for a lookup request in a processor |
GB2495959A (en) | 2011-10-26 | 2013-05-01 | Imagination Tech Ltd | Multi-threaded memory access processor |
US9373182B2 (en) * | 2012-08-17 | 2016-06-21 | Intel Corporation | Memory sharing via a unified memory architecture |
US9582287B2 (en) * | 2012-09-27 | 2017-02-28 | Intel Corporation | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions |
US20140101405A1 (en) * | 2012-10-05 | 2014-04-10 | Advanced Micro Devices, Inc. | Reducing cold tlb misses in a heterogeneous computing system |
CN103853620B (zh) * | 2012-11-30 | 2017-06-09 | 华为技术有限公司 | 一种众核处理器进程间相互通信的方法、装置及系统 |
US9026681B2 (en) | 2013-08-08 | 2015-05-05 | Qualcomm Incorporated | Flexible hardware module assignment for enhanced performance |
US9411745B2 (en) * | 2013-10-04 | 2016-08-09 | Qualcomm Incorporated | Multi-core heterogeneous system translation lookaside buffer coherency |
US9396089B2 (en) | 2014-05-30 | 2016-07-19 | Apple Inc. | Activity tracing diagnostic systems and methods |
US9348645B2 (en) * | 2014-05-30 | 2016-05-24 | Apple Inc. | Method and apparatus for inter process priority donation |
US9600442B2 (en) * | 2014-07-18 | 2017-03-21 | Intel Corporation | No-locality hint vector memory access processors, methods, systems, and instructions |
US9424173B2 (en) | 2014-10-23 | 2016-08-23 | GlobalFoundries, Inc. | Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory |
US9740617B2 (en) * | 2014-12-23 | 2017-08-22 | Intel Corporation | Hardware apparatuses and methods to control cache line coherence |
FR3061327B1 (fr) * | 2016-12-26 | 2019-05-31 | Thales | Procede de controle d'un processeur multi-coeurs et calculateur associe |
CN107038125B (zh) * | 2017-04-25 | 2020-11-24 | 上海兆芯集成电路有限公司 | 具有加速预取请求的独立流水线的处理器高速缓存 |
US11314865B2 (en) * | 2017-08-01 | 2022-04-26 | The Trustees Of Princeton University | Pluggable trust architecture |
US10824584B1 (en) * | 2018-04-03 | 2020-11-03 | Xilinx, Inc. | Device with data processing engine array that enables partial reconfiguration |
CN110413210B (zh) * | 2018-04-28 | 2023-05-30 | 伊姆西Ip控股有限责任公司 | 用于处理数据的方法、设备和计算机程序产品 |
CN108614460B (zh) * | 2018-06-20 | 2020-11-06 | 东莞市李群自动化技术有限公司 | 分布式多节点控制系统及方法 |
CN109117291A (zh) * | 2018-08-27 | 2019-01-01 | 惠州Tcl移动通信有限公司 | 基于多核处理器的数据调度处理方法、装置和计算机设备 |
US10860487B2 (en) * | 2019-04-17 | 2020-12-08 | Chengdu Haiguang Integrated Circuit Design Co. Ltd. | Multi-core processing device and method of transferring data between cores thereof |
CN113138711B (zh) * | 2020-01-20 | 2023-11-17 | 北京希姆计算科技有限公司 | 一种存储管理装置及芯片 |
CN113515483A (zh) * | 2020-04-10 | 2021-10-19 | 华为技术有限公司 | 一种数据传输方法及装置 |
CN112000608B (zh) * | 2020-09-02 | 2021-10-01 | 展讯通信(上海)有限公司 | 系统级芯片及其中核间通信的方法、智能穿戴设备 |
US11954034B2 (en) * | 2022-03-28 | 2024-04-09 | Woven By Toyota, Inc. | Cache coherency protocol for encoding a cache line with a domain shared state |
CN115658569B (zh) * | 2022-12-08 | 2023-04-14 | 井芯微电子技术(天津)有限公司 | Amp多核处理器间中断与共享存储方法、系统及设备 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101510191A (zh) * | 2009-03-26 | 2009-08-19 | 浙江大学 | 具备缓存窗口的多核体系架构及其实现方法 |
CN101477511B (zh) * | 2008-12-31 | 2010-08-25 | 杭州华三通信技术有限公司 | 一种实现多操作系统共享存储介质的方法和装置 |
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US4488231A (en) * | 1980-09-29 | 1984-12-11 | Honeywell Information Systems Inc. | Communication multiplexer having dual microprocessors |
US5123094A (en) | 1990-01-26 | 1992-06-16 | Apple Computer, Inc. | Interprocessor communications includes second CPU designating memory locations assigned to first CPU and writing their addresses into registers |
US6148375A (en) | 1998-02-13 | 2000-11-14 | International Business Machines Corporation | Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes |
US6754788B2 (en) | 2001-03-15 | 2004-06-22 | International Business Machines Corporation | Apparatus, method and computer program product for privatizing operating system data |
US7263598B2 (en) | 2002-12-12 | 2007-08-28 | Jack Robert Ambuel | Deterministic real time hierarchical distributed computing system |
WO2004107180A1 (ja) | 2003-05-30 | 2004-12-09 | Fujitsu Limited | マルチプロセッサシステム |
US7711901B2 (en) | 2004-02-13 | 2010-05-04 | Intel Corporation | Method, system, and apparatus for an hierarchical cache line replacement |
US8275951B2 (en) * | 2004-06-10 | 2012-09-25 | Hewlett-Packard Development Company, L.P. | Local bitmaps for an array of redundant storage devices |
US7577794B2 (en) | 2004-10-08 | 2009-08-18 | International Business Machines Corporation | Low latency coherency protocol for a multi-chip multiprocessor system |
JP2006127217A (ja) * | 2004-10-29 | 2006-05-18 | Hitachi Ltd | 計算機システムおよび計算機システムの制御方法 |
EP1710703A1 (fr) | 2005-04-04 | 2006-10-11 | Stmicroelectronics Sa | Cohérence de cache dans un système multiprocesseurs à mémoire partagée |
GB2442984B (en) | 2006-10-17 | 2011-04-06 | Advanced Risc Mach Ltd | Handling of write access requests to shared memory in a data processing apparatus |
US7937532B2 (en) | 2007-03-30 | 2011-05-03 | Intel Corporation | Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine |
CN101430651B (zh) | 2007-11-05 | 2012-01-11 | 中兴通讯股份有限公司 | 一种异构多核体系中外设的访问方法 |
WO2009065313A1 (fr) | 2007-11-20 | 2009-05-28 | Hangzhou H3C Technologies Co., Ltd. | Procédé et équipement à processeur multicœurs pour la mise en œuvre de plusieurs fonctions de traitement de services |
-
2011
- 2011-02-11 US US13/025,446 patent/US9471532B2/en active Active
-
2012
- 2012-01-11 TW TW101101125A patent/TWI473013B/zh not_active IP Right Cessation
- 2012-02-10 CN CN201210030338.2A patent/CN102622329B/zh active Active
- 2012-02-11 EP EP12744863.7A patent/EP2673717A4/en not_active Ceased
- 2012-02-11 WO PCT/US2012/024776 patent/WO2012109631A2/en active Application Filing
-
2013
- 2013-01-24 HK HK13101090.2A patent/HK1174116A1/zh unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101477511B (zh) * | 2008-12-31 | 2010-08-25 | 杭州华三通信技术有限公司 | 一种实现多操作系统共享存储介质的方法和装置 |
CN101510191A (zh) * | 2009-03-26 | 2009-08-19 | 浙江大学 | 具备缓存窗口的多核体系架构及其实现方法 |
Also Published As
Publication number | Publication date |
---|---|
HK1174116A1 (zh) | 2013-05-31 |
EP2673717A4 (en) | 2018-01-10 |
US9471532B2 (en) | 2016-10-18 |
WO2012109631A3 (en) | 2012-10-18 |
US20120210071A1 (en) | 2012-08-16 |
WO2012109631A2 (en) | 2012-08-16 |
TW201234264A (en) | 2012-08-16 |
EP2673717A2 (en) | 2013-12-18 |
TWI473013B (zh) | 2015-02-11 |
CN102622329A (zh) | 2012-08-01 |
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