CN102622320B - Interrupt control method for Feiteng server - Google Patents
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- CN102622320B CN102622320B CN201210040518.9A CN201210040518A CN102622320B CN 102622320 B CN102622320 B CN 102622320B CN 201210040518 A CN201210040518 A CN 201210040518A CN 102622320 B CN102622320 B CN 102622320B
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Abstract
The invention discloses an interrupt control method for a Feiteng server. The method comprises the following steps: initialization is performed; a hardware interrupt source generates corresponding types of interrupt signals through a hardware control logic component of a south bridge CS5536, outputs a public interrupt trigger signal through a router of an interrupt controller 8259A of the south bridge CS5536 and modifies corresponding interrupt bits in an internal register of the interrupt controller 8259A, and the public interrupt trigger signal is mapped by a bridge chip to be converted into interrupt messages and transmitted to a PCIE bus; and a Feiteng processor acquires the interrupt messages from the PCIE bus, enters an interrupt state, invokes a public interrupt receptance function and reads the internal register of the interrupt controller 8259A to acquire the interrupt bits so as to determine the hardware interrupt source and treat interrupts. The method provided by the invention can enable the Feiteng processor to receive interrupt messages of equipment CS5536 in a real-time manner and to respond and treat various interrupts accurately and in a real-time manner.
Description
Technical field
The present invention relates to operating system interrupt techniques field, relate in particular to the interrupt control method for the server of soaring.
Background technology
The server of soaring adopts the two-way processor of soaring, and each processor is comprised of 64 rigid line journeys of 8 core, and processor frequencies is 800MHz～1GHz, by point-to-point high speed exchange chip, provides 6 PCIE2.0 bus slots, and the highest IO frequency of single channel can reach 5Gbps.
The server of soaring has adopted the south bridge CS5536 of pci bus standard, the hardware interface steering logics such as USB controller, IDE Magnetic Disk Controller, Audio Controller, RTC real-time clock and keyboard and mouse PS/2 interface controller that south bridge CS5536 chip internal is integrated.The 8259A of monolithic comprises 8 interrupting input pins, 1 interrupt output pin, 1 acknowledge interrupt pin, cascade pin and other control pins.By cascade pin, a plurality of 8259A can be together in series in the mode of " MS master-slave " configuration, and then expand hardware interrupts number.Typical 8259A application mode exists two kinds: a kind of is to adopt independently 8259A chip to control interrupting, and peripherals interrupts directly input 8259A, then the interrupt output pin by 8259A passes to processor and interrupts processing; Another kind is the application that is integrated in 8259A in south bridge CS5536, by this interruptable controller, directly process the device interrupt of supporting in CS5536 chip, the design of this integrated form is generally only used on the processor platform of X86 series, has X86 architecture dependence.On X86 platform, 8259A sends look-at-me with the out-band method of processor interface string line CIS to processor.CIS serial data format is as shown in Figure 1: CIS provides the serial data format of 20, comprises 2 start, 16 data[0 ... 15], and 2 stop.Wherein, data[7] be the interrupt bit of 8259A.X 86 processor system can receive and resolve CIS, obtains interrupt bit, and processor pipeline is interrupted.8259A provides software interruption securing mechanism.Do not needing under the prerequisite of software intervention, X 86 processor directly 0 pair of interruption of reading address is confirmed, and the software interruption number of automatic acquisition interrupt source, then jumps to the corresponding processing function that interrupts of operation in interrupt vector address.
The server of soaring is UltraSPARC(tradition SPARC architecture) architecture, neither provide CIS band outer string line, can not automatically to address 0, confirm, more can not directly jump in corresponding interrupt vector address.Therefore need provide a kind of new interruption processing method to can realize the interruption processing of soaring in server with being integrated in 8259A in south bridge CS5536.
Summary of the invention
Technical matters to be solved by this invention is: the problem existing for prior art, the invention provides a kind of real-time, accurate and effective interrupt control method for the server of soaring.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
An interrupt control method for the server of soaring, comprises the following steps:
(1) initialization: in operating system nucleus start-up course, the interrupt bit to the hardware control logic parts assigned interrupt controller 8259A in south bridge CS5536, and interruption route is set;
(2) down trigger: hardware interrupts source produces the look-at-me of respective type by the hardware control logic parts in south bridge CS5536; In the internal register of interruptable controller 8259A, revise corresponding interrupt bit, look-at-me is output as a common interrupt trigger pip by the interruptable controller 8259A route in south bridge CS5536, and described common interrupt trigger pip becomes interrupt message message and reaches PCIE bus through bridging chip Mapping and Converting;
(3) interrupt response: the processor of soaring obtains described interrupt message message from PCIE bus, enters interruption status and calls a common interrupt response function; The internal register that described common interrupt response function reads described interruptable controller 8259A obtains interrupt bit, according to described interrupt bit, determines hardware interrupts source, and notifies the processor of soaring to call corresponding interruption and process function handling interrupt.
As a further improvement on the present invention:
General purpose I/O port GPIO12 that described look-at-me outputs to south bridge CS5536 by the interruptable controller 8259A route in south bridge CS5536 is upper, by edge-triggered mode, is output as a common interrupt trigger pip.
Described interrupt message message comprises Assert_INTx and the Deasser_INTx of PCIE bus specification definition, described Assert_INTx is that interrupt level signal converts effective status to from disarmed state, and described Deasser_INTx is that interrupt level signal converts disarmed state to from effective status.
The initialization flow process of described step comprises the following steps:
(1) the IO address of the processor access GPIO that soars is set;
(2) interrupt bit of shielding interruptable controller 8259A except inner cascade is interrupted;
(3) by all interruption routing functions that the setting of relevant MSR register is deenergized;
(4) function of all parts by GPIO12 that the access of GPIO plot is deenergized;
(5) enable the function setting of the parts that the need of GPIO12 use;
(6) according to hardware, connect or arrange, by relevant MSR register route interrupt source being set to corresponding 8259A interrupt pin, so that interruption route to be set;
(7) initialization interruptable controller 8259A.
The parts that the need of described GPIO12 are used specifically refer to: on GPIO12, draw position, flip bit, AUX1 output to select position and output enable position.
Described initialization interruptable controller 8259A is specially: ICW1～ICW4 is carried out to initialization one by one, interrupt number and the ID of down trigger pattern, the corresponding IR0 of master/slave 8259A is set.
Compared with prior art, the invention has the advantages that:
Interrupt control method for the server of soaring of the present invention, the processor of soaring can receive the interrupt message message in hardware interrupts source in real time, has realized each functional part of processor platform south bridge CS5536 of soaring mutual with the interruption of the processor of soaring.By to interrupting the modification of triggering mode, the processor that makes to soar can receive the interrupt message message of CS5536 equipment in real time; By the modification of interruption acknowledge and ways of distribution, can make CS5536 relevant device controller drive accurately real-time response and process various interruptions.Can meet and allly in CS5536 take the requirement that down trigger is basic device controller, the confirmation of interrupting according to the interruption status of each controller in CS5536 on public shared interrupt source basis, distribution and response are processed.
Accompanying drawing explanation
Fig. 1 is CIS serial data format schematic diagram.
Fig. 2 is the main-process stream schematic diagram of the embodiment of the present invention 1.
Fig. 3 is the structural representation of DIVIL_LBAR_GPIO register; Wherein, BASE_ADDR is IO base address; LBAR_EN is local BAR register access enable bit; IO_MASK is masked bits; RSVD is for retaining position.
Fig. 4 is the structural representation that interrupts initialization command word register; Wherein the TRIGGER in ICW1 is trigger mode, 0-edge-triggered, 1-level triggers; RSVD is for retaining position; A in ICW2 is 8259 benchmark interrupt vectors; RSVD is for retaining position; In ICW3 corresponding to Master, be used for depositing the interrupt number of 8259A cascade, and in ICW3 corresponding to SLAVE, be used for depositing No. ID of SLAVE.For Master and SLAVE, ICW3 register format is all the same, can operate the ICW3 of Master by access IO port 0x21, and access IO port 0xA1 can operate the ICW3 of SLAVE.AUTO_EOI in ICW4 is End of Interrupt tupe.
Fig. 5 is the hardware wired logic schematic diagram of the embodiment of the present invention 1.
Fig. 6 is the local PCIE bus structure schematic diagram of the server of soaring of the embodiment of the present invention 1.
Fig. 7 is the connection diagram of the CS5536 interruptable controller of the embodiment of the present invention 1.
Fig. 8 is the hardware based interruption initialization of the kernel level of the embodiment of the present invention 1 schematic flow sheet.
Fig. 9 is the hardware based interrupt response schematic flow sheet of the kernel level of the embodiment of the present invention 1.
Figure 10 is the initialization schematic flow sheet of the interruption that produces of the USB OHCI of the embodiment of the present invention 2.
Figure 11 is the structural representation that the test of the embodiment of the present invention 3 drives.
Figure 12 is the workflow schematic diagram that the interrupt test in the embodiment of the present invention 3 drives.
Figure 13 is the workflow schematic diagram of the application module in the embodiment of the present invention 3.
Embodiment
Below with reference to Figure of description and specific embodiment, the present invention is described in further detail.
embodiment 1:
As shown in Figure 2, the hardware based interruption of the kernel level of take is example, describes the interrupt control method for the server of soaring of the present invention in detail.
The server of soaring has adopted the south bridge CS5536 of pci bus standard, the hardware interface steering logics such as USB controller, IDE Magnetic Disk Controller, Audio Controller, RTC real-time clock and keyboard and mouse PS/2 interface controller that chip internal is integrated.South bridge CS5536 is connected in PCIE bus by bridging chip PLX8112.These internal hardware controller logic look-at-mes are all carried out route by the 8259A interruptable controller of CS5536 inside, bridging chip PLX8112 is responsible for the look-at-me of level form to convert to the look-at-me of PCIE2.0 bus message form, and passes to processor chips.Before the method for the present embodiment starts, first the hardware of the server of soaring is done to following connection and setting:
As shown in Figure 5, by two 8259A interruptable controllers by MS master-slave cascade, can provide 15 can receive interruption signal interrupt pin.The INTR#(interrupt request pin of main 8259A) output is directly connected to the 12nd general purpose I/O interface of GPIO12() upper (output of main 8259A is logically routed in the AUX1 input of GPIO12), the interrupt output of GPIO12 is connected to the PCI_INTA#(interrupt pin of PCIE-PCI bridge chip) on.GPIO12 can be configured to output port or input port.Output port comprises that selector switch (is used for selecting the way of output, connects OutputVal and can make software Dynamic Generation output signal; AUX1 and AUX2 are two interface channels), output enable parts (enabling output module), turning part (trigging signal) and pull down switch (dragging down level).(interrupt procedure of the present invention is mainly used output port).
After hardware connection and setting complete, interrupt controlling:
(1) initialization.As shown in Figure 8, initialization comprises the following steps:
A. the initialization of bridge window.
Before carrying out the initialization of GPIO12, need to specify the IO address of GPIO, this address is comprised of IO plot and the GPIO register plot of CS5536.As shown in Figure 6, the South Bridge chip of the present embodiment is connected to after three PCIE-PCIE bridges and a PCIE-PCI bridge, in order to allow the processor of soaring can have access to the IO address of GPIO, the IO address of GPIO need to be mapped in the IO window ranges of these four bridges, by the IO BASE(IO base address to these four bridge configuration spaces, be positioned at bridge configuration space 0x1C place) and IO LIMIT(IO window ranges, be positioned at bridge configuration space 0x1D place) carry out address realm setting and meet the demands.
The IO address of GPIO is set; MSR register DIVIL_LBAR_GPIO (0x8000000C) is set (to be present in south bridge CS5536, structure is as shown in Figure 3), [8:15] of this DIVIL_LBAR_GPIO register is set as the IO plot (the present embodiment is set to 0x5c00-0x5cff) that GPIO is corresponding; [32] enable to open (being set to 1), allow the access of LBAR, [44:47] arranges the mask (the present embodiment is set to 0xf) of IO, determines the IO address realm of GPIO according to the plot of IO and IO mask.
B. shield the interrupt bit (except inner cascade interruption) of interruptable controller 8259A.In the present embodiment, it is the main 8259A of 0x21(that IO plot is added to side-play amount)/0xa1(is from 8259A) position shield the setting of interrupt bit, by each position 1.
C. interruption routing function deenergizes.
First all kinds of interrupt source can shine upon by a MAM() controller, then according to register configuration, be routed to the programmable interrupt controller of XPIC(expansion), finally link again on the interrupting input pin of 8259A, by the interruption route of deenergizing all to relevant MSR register setting.
As shown in Figure 7, interrupt source is divided into four classes: PRIMARY interrupt source, LPC interrupt source, Y interrupt source and Z interrupt source.Four types has 15 interrupting input pins, and Y class and Z class interrupt source need to be 0～15 to IGX(X by MSR register PIC_YSEL_LOW/HIGH and PIC_ZSEL_LOW/HIGH routing configuration) Zhong mono-tunnel, then from 8259A, input.Now needing that these are interrupted to route all deenergizes.Interrupt bit and the mapping of hardware interrupts source and route also realize by configuring relevant MSR register.
D. the deenergize setting of all parts of GPIO12.GPIO12 module has comprised the correlation function parts of controlling GPIO12.As: selector switch, upset, output input enable the functional part such as to draw with up/down, by all component functions of GPIO12 that the access of GPIO plot is deenergized.
E. enable the setting of GPIO12.Open GPIO12 on draw position, flip bit, AUX1 output to select position and output enable position, complete the initialization of GPIO12.
F. enable to interrupt routing function.According to the rules, route interrupt source arrives corresponding 8259A interrupt pin, as: RTC(real-time clock) interrupt being routed on No. 8 pins of cascade 8259A, this pin is used for receiving the look-at-me that RTC produces.By relevant MSR register is arranged to all interruption routes.
G. initialization interruptable controller 8259A.As shown in Figure 4, to ICW1～ICW4(initialization command word) carry out one by one initialization, comprise the relevant informations such as the interrupt number of down trigger pattern, the corresponding IR0 of master/slave 8259A and ID.It is 0x11 that master/slave ICW1 is set, and down trigger pattern adopts edge-triggered; It is 0x0 that main ICW2 is set, and represents that interrupt vector reference number is 0, and arranging is 0X8 from ICW2, represents that interrupt vector reference number is 8; It is 0x4 that main ICW3 is set, and from ICW3, is that 0x2(ICW3 is for being fixedly installed); It is 0x1 that master/slave ICW4 is set, and adopts 8086/8088 pattern etc.
(2) down trigger.
As shown in Figure 5, in triggering, hardware interrupts source (external unit) have no progeny, device controller in south bridge produces look-at-me and gives interruptable controller 8259A, 8259A receives after look-at-me, by IRR(interrupt request register) position 1 that register is corresponding, indicate that interrupt request arrives; Look-at-me is exported by the INTR# of 8259A, arrives GPIO12 and passes on the PCI_INTA# pin of PCI-PCIE bridge, thereby reaching PCIE bus.
From software view, because the equipment in CS5536 is all virtual logical device, system does not think that when initialization these logical device are real PCI equipment, can not carry out to these logical device initialization and the configuration in PCI space, logical device drives and will obtain less than relevant PCI information like this, particularly with interrupting relevant configuration, as the value of INTERRUPT LINE in pci configuration space, to cause interrupting handling failure, so before down trigger, need to first fictionalize the PCI space of CS5536 logical device, as shown in Fig. 2 flow process.When down trigger, produce self-trappingly, first call common interrupt and process function, this common process function is used for obtaining interrupt vector number and calls CS5536 logical device interrupts and process function, processes function complete corresponding interruption and process by logical device interrupts.
(3) interrupt response.
As shown in Figure 9, soar processor from PCIE bus receives this interrupt message message, produce self-trapping, call common interrupt response function, this function obtains interrupt number and interrupt descriptors first address corresponding to interrupt number, and the interruption processing function that traversal is registered in interrupt descriptors interrupts processing.According to hardware, connect up, the all internal logic device interrupt of CS5536 send to by interrupting shared mode the processor of soaring, so an interrupt number correspondence the interruption of the different internal logic equipment of all CS5536, simultaneously also function is processed in corresponding different interruption, in order to distinguish contacting of this shared interrupt number and the different internal units of CS5536, when traversal interrupts processing function, in interruption, process the value that first reads IRR register in function beginning and be used for judging that interrupting whether triggering this interrupts processing function, if the corresponding interrupt bit of IRR is 1, show that this interrupts effectively, interrupt the corresponding position of shielding, carry out subsequent interrupt processing, wait to interrupt finishing dealing with, cancel this interrupt mask, exit and interrupt processing function, if the position that IRR is corresponding is not 1, show that this interruption is invalid, directly exit this and interrupt processing function continuation traversal, until traveled through.
embodiment 2:
Take the open host controller interface of USB OHCI(USB) interruption that produces is example, further illustrates the present invention for the interrupt control method of the server of soaring.Concrete steps are as follows:
This interface driver is supported the USB device of low speed, as: USB mouse or USB keyboard.
The present embodiment and embodiment 1 are based on same FT server, and hardware configuration is identical.
(1) as shown in figure 10, the USB OHCI initialization procedure of soaring in multiple-core server platform is as follows:
USB OHCI is an integrated function logic equipment interface of CS5536, in USB OHCI initialization procedure, first creates the device tree node of OHCI, and follow-up USB OHCI drives directly this nodal information of access; Then carry out the roughly the same interruption initialization of embodiment 1; Because USB OHCI is used PCI MEM space, then need to obtain the plot of OHCI MEM, enable the access of MEM simultaneously, and carry out MEM division, do not conflicted with other in the MEM space of distributing to USB OHCI; Then according to the method for interrupt response in embodiment 1, OHCI interrupt response function is rewritten; Virtual OHCI configuration space also loads OHCI device drives.And then complete the initialized process of whole USB OHCI.
(2) down trigger.
By on USB mouse and USB keyboard access south bridge USB HOST control unit interface.When sliding mouse or while knocking keyboard, electric signal is converted into look-at-me and the input pin by 8259A in CS5536 imports into, the AUX1 passage to GPIO12 with high level output, carries out with low level, from GPIO12, exporting after the processing such as level upset again, reaches PCIE bus.
(3) interrupt response.
Soar processor from PCIE bus receives this interrupt message message, by common interrupt response function, call interrupt response function corresponding to this USB device, this function reads interrupt request and the irr register (interrupt status register) of 8259A, relevant bits in the IRR register of this interval scale mouse or keyboard interrupt request is set up that (when triggering USB device event, hardware arranges irr relevant bits automatically.) and then the interruption of calling mouse or keyboard process function and complete subsequent interrupt and process.
embodiment 3:
The interruption of employing based on software simulation CS5536 internal unit, verifies the interrupt control method for the server of soaring of the present invention, and concrete steps are as follows:
As shown in figure 11, for simulation realizes the present invention, design an interrupt test and driven, mainly comprised three modules: interrupt initialization module, soft triggering interrupt module and soft triggering interrupt handling routine Registering modules.
Adopt above-mentioned interrupt test to drive the interrupt control method realizing, comprise the following steps:
(1) initialization, the initialization procedure of the present embodiment and embodiment 1 and embodiment 2 are basic identical, difference is only: initialized time point is different, embodiment 1 and embodiment 2 complete relevant interruption initialization unloading phase of system kernel, and the initialization of the present embodiment has been placed in interrupt test driving.
(2) down trigger.
As shown in figure 12, after initialization, add soft triggering interrupt module, it produces and stops down trigger by the 0th of DIVIL_SOFT_IRQ (soft down trigger register) of south bridge MSR register is set.This module is registered in ioctl (IO controll block) simultaneously, when upper layer application, sends after the ioctl order of down trigger like this, directly call the triggering simulation that this module is carried out software interruption.
(3) registration and the response interrupted.
As shown in figure 13, register corresponding interruption process function by request_irq (interrupting registration) interface, in interruption, processing function entrance place carries out the judgement of IRR register interrupts position, makes interrupt handling routine only process one's own interrupt request.That is, in software simulation triggers one, have no progeny, it is called that this interrupts processing function, judge whether the corresponding position of IRR register is 1, and if 1, proceed this and interrupt processing, otherwise exit processing.
In the present embodiment, having designed a upper application module coordinates test to drive use together, this application module is positioned at application layer (driving is positioned at inner nuclear layer), be mainly used to produce the order that triggers interruption, the driving of test is passed in order by ioctl interface, driving can produce soft interruption by triggering 8259A after receiving this order, and then allows the interruption of registration process function response.As shown in figure 13, the realization flow of upper application module is as follows:
A. opening interrupt test drives for obtaining the driving descriptor that driver module is corresponding.When test can generate corresponding device drives node (as testdriver) during drive load under/dev catalogue, this node i.e. device drives descriptor for this reason, by open (/dev/driver ..) function, can be completed and be obtained.
B. by ioctl passage, to this driver module, transmit and trigger the order of interrupting.When driver module receives order meeting, call the soft triggering interrupt module of previous registration and send out interruption, it is called that function is processed in the interruption of registration simultaneously, now can go the IRR register that reads 8259A (after down trigger, hardware arranges irr relevant bits automatically), if the corresponding set of position of this register, represent that the interrupt request triggering arrives, and then respond this interrupt request.
C. discharge opened driving descriptor, be finished.
In above-mentioned steps, by upper application module and interrupt test, drive, simulated the situation that adopts interrupt control method of the present invention to realize soft interruption.
To sum up, the present invention is the interrupt control method for the server of soaring, and the interruption that on the server that can guarantee to soar, CS5536 internal hardware controller logic triggers is promptly and accurately responded, and CS5536 equipment is normally worked.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention is also not only confined to above-described embodiment, and all technical schemes belonging under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.
Claims (5)
1. for an interrupt control method for the server of soaring, it is characterized in that comprising the following steps:
(1) initialization: in operating system nucleus start-up course, the interrupt bit to the hardware control logic parts assigned interrupt controller 8259A in south bridge CS5536, and interruption route is set;
(2) down trigger: hardware interrupts source produces the look-at-me of respective type by the hardware control logic parts in south bridge CS5536; In the internal register of interruptable controller 8259A, revise corresponding interrupt bit, look-at-me is output as a common interrupt trigger pip by the interruptable controller 8259A route in south bridge CS5536, and described common interrupt trigger pip becomes interrupt message message and reaches PCIE bus through bridging chip Mapping and Converting;
(3) interrupt response: the processor of soaring obtains described interrupt message message from PCIE bus, enters interruption status and calls a common interrupt response function; The internal register that described common interrupt response function reads described interruptable controller 8259A obtains interrupt bit, according to described interrupt bit, determines hardware interrupts source, and notifies the processor of soaring to call corresponding interruption and process function handling interrupt;
Initialization flow process in described step (1) comprises the following steps:
(1.1) the IO address of the processor access GPIO that soars is set;
(1.2) interrupt bit of shielding interruptable controller 8259A except inner cascade is interrupted;
(1.3) by all interruption routing functions that the setting of relevant MSR register is deenergized;
(1.4) function of all parts by GPIO12 that the access of GPIO plot is deenergized;
(1.5) enable the function setting of the parts that the need of GPIO12 use;
(1.6) according to hardware, connect or arrange, by relevant MSR register route interrupt source being set to corresponding interruptable controller 8259A interrupt pin, so that interruption route to be set;
(1.7) initialization interruptable controller 8259A.
2. the interrupt control method for the server of soaring according to claim 1, it is characterized in that, general purpose I/O port GPIO12 that described look-at-me outputs to south bridge CS5536 by the interruptable controller 8259A route in south bridge CS5536 is upper, by edge-triggered mode, is output as a common interrupt trigger pip.
3. the interrupt control method for the server of soaring according to claim 1, it is characterized in that, described interrupt message message comprises Assert_INTx and the Deasser_INTx of PCIE bus specification definition, described Assert_INTx is that interrupt level signal converts effective status to from disarmed state, and described Deasser_INTx is that interrupt level signal converts disarmed state to from effective status.
4. the interrupt control method for the server of soaring according to claim 1, is characterized in that, the parts that the need of described GPIO12 are used specifically refer to: on GPIO12, draw position, flip bit, AUX1 output to select position and output enable position.
5. the interrupt control method for the server of soaring according to claim 1, it is characterized in that, described initialization interruptable controller 8259A is specially: ICW1～ICW4 is carried out to initialization one by one, interrupt number and the ID of the corresponding IR0 of master/slave interruptable controller 8259A that down trigger pattern is set, configures with " MS master-slave ".
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| CN107861763B (en) * | 2017-12-01 | 2022-03-11 | 麒麟软件有限公司 | Interrupt routing environment recovery method for dormancy process of Feiteng processor |
| CN108628782B (en) * | 2018-03-27 | 2024-03-15 | 天津麒麟信息技术有限公司 | Implementation method of interrupt switching mechanism based on Feiteng platform |
| CN109343854B (en) * | 2018-09-18 | 2021-09-03 | 武汉精立电子技术有限公司 | Intelligent automatic compiling method and system based on zynq system |
| CN111897632B (en) * | 2019-05-05 | 2023-10-20 | 兆易创新科技集团股份有限公司 | Interrupt processing method and device, electronic equipment and storage medium |
| CN112711559B (en) | 2021-01-15 | 2023-06-13 | 飞腾信息技术有限公司 | Serial interrupt method, serial interrupt device, serial interrupt processing method and processor |
| CN114253694B (en) * | 2022-02-25 | 2022-06-24 | 杭州雄迈集成电路技术股份有限公司 | Asynchronous processing method and device based on neural network accelerator |
| CN116069694B (en) * | 2023-03-07 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Interrupt processing method, device, server, electronic equipment and storage medium |
| CN116521324B (en) * | 2023-06-30 | 2024-04-12 | 深圳中安辰鸿技术有限公司 | Interrupt virtualization processing method and device and electronic equipment |
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