CN102610579B - The board structure manufactured for semiconductor device and manufacture method thereof - Google Patents
The board structure manufactured for semiconductor device and manufacture method thereof Download PDFInfo
- Publication number
- CN102610579B CN102610579B CN201110025831.0A CN201110025831A CN102610579B CN 102610579 B CN102610579 B CN 102610579B CN 201110025831 A CN201110025831 A CN 201110025831A CN 102610579 B CN102610579 B CN 102610579B
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- groove
- flexible material
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 239000000758 substrate Substances 0.000 claims abstract description 322
- 239000000463 material Substances 0.000 claims abstract description 104
- -1 polypropylene Polymers 0.000 claims description 27
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229920000642 polymer Polymers 0.000 claims description 16
- 239000002202 Polyethylene glycol Substances 0.000 claims description 15
- 229920001223 polyethylene glycol Polymers 0.000 claims description 15
- 229920002101 Chitin Polymers 0.000 claims description 12
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 12
- JVTAAEKCZFNVCJ-UHFFFAOYSA-N lactic acid Chemical compound CC(O)C(O)=O JVTAAEKCZFNVCJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000002086 nanomaterial Substances 0.000 claims description 12
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 12
- 229920005479 Lucite® Polymers 0.000 claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 238000005452 bending Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 7
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 claims description 6
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 6
- FHVDTGUDJYJELY-UHFFFAOYSA-N 6-{[2-carboxy-4,5-dihydroxy-6-(phosphanyloxy)oxan-3-yl]oxy}-4,5-dihydroxy-3-phosphanyloxane-2-carboxylic acid Chemical compound O1C(C(O)=O)C(P)C(O)C(O)C1OC1C(C(O)=O)OC(OP)C(O)C1O FHVDTGUDJYJELY-UHFFFAOYSA-N 0.000 claims description 6
- 239000004925 Acrylic resin Substances 0.000 claims description 6
- 229920000178 Acrylic resin Polymers 0.000 claims description 6
- 102000008186 Collagen Human genes 0.000 claims description 6
- 108010035532 Collagen Proteins 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000004952 Polyamide Substances 0.000 claims description 6
- 239000004743 Polypropylene Substances 0.000 claims description 6
- 239000004372 Polyvinyl alcohol Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 6
- 229940072056 alginate Drugs 0.000 claims description 6
- 229920000615 alginic acid Polymers 0.000 claims description 6
- 235000010443 alginic acid Nutrition 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229920001436 collagen Polymers 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 239000000835 fiber Substances 0.000 claims description 6
- 229920002313 fluoropolymer Polymers 0.000 claims description 6
- 239000004811 fluoropolymer Substances 0.000 claims description 6
- 239000000017 hydrogel Substances 0.000 claims description 6
- 239000004310 lactic acid Substances 0.000 claims description 6
- 235000014655 lactic acid Nutrition 0.000 claims description 6
- 239000002071 nanotube Substances 0.000 claims description 6
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 6
- 229920002647 polyamide Polymers 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000004626 polylactic acid Substances 0.000 claims description 6
- 229920000098 polyolefin Polymers 0.000 claims description 6
- 229920001155 polypropylene Polymers 0.000 claims description 6
- 229920001296 polysiloxane Polymers 0.000 claims description 6
- 229920002635 polyurethane Polymers 0.000 claims description 6
- 239000004814 polyurethane Substances 0.000 claims description 6
- 229920002451 polyvinyl alcohol Polymers 0.000 claims description 6
- 239000000741 silica gel Substances 0.000 claims description 6
- 229910002027 silica gel Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 5
- 229920005372 Plexiglas® Polymers 0.000 claims description 5
- 229920003171 Poly (ethylene oxide) Polymers 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910021389 graphene Inorganic materials 0.000 claims description 5
- 229920000747 poly(lactic acid) Polymers 0.000 claims description 5
- 229920000036 polyvinylpyrrolidone Polymers 0.000 claims description 5
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 claims description 5
- 239000001267 polyvinylpyrrolidone Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 150000002596 lactones Chemical class 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229920001610 polycaprolactone Polymers 0.000 claims description 3
- 239000004632 polycaprolactone Substances 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000002322 conducting polymer Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 150000002576 ketones Chemical class 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 229920006316 polyvinylpyrrolidine Polymers 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000003754 machining Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 87
- 230000008569 process Effects 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000000875 corresponding effect Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N SnO2 Inorganic materials O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920005570 flexible polymer Polymers 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- DFGMFVYRMVYRRA-UHFFFAOYSA-N [O].CC Chemical compound [O].CC DFGMFVYRMVYRRA-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000003367 polycyclic group Chemical group 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/035281—Shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Abstract
The present invention proposes a kind of board structure and manufacture method thereof.This board structure includes: base plate array, described base plate array includes arranging multiple substrates at grade according to predetermined direction, each described substrate has first surface and second surface on the other side, and described base plate array is arranged in the plane parallel with described substrate first surface；Multiple substrates, it connects described adjacent substrate, and described substrate is vertical with the upstanding sidewall of connected substrate；Flexible material layer, described flexible material layer be positioned at least part of described substrate surface and or at least partly on substrate surface.The present invention by forming flexible material layer on the surface of described substrate, during stretching vertical base plate array formation planar substrates array, even if rupturing owing to described substrate fragility is excessive, adjacent substrate can also be connected by flexible material layer, realize relatively easily multiple vertical substrates are drawn into planar substrates array status, improve working (machining) efficiency and the yield rate of device architecture.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly to a kind of increase surface area, for partly leading
The board structure of body device manufacture and manufacture method thereof.
Background technology
In recent years, along with developing rapidly of semiconductor industry, semiconductor device constantly towards small size,
High circuit closeness, quickly, low power consumption direction develop, integrated circuit has entered the skill of submicron order
The art stage.Therefore, in order to adapt to the needs of small size, high integration, it is currently suggested both sides
Requirement, is on the one hand that the diameter of requirement wafer is gradually increased, by 2005, and diameter 300mm silicon
Sheet became main product, it is contemplated that by 2012, will begin to use diameter 450mm (18in) silicon chip,
The speed that the diameter of wafer about increased 1.5 times with every 9 years constantly increases, and develops to large area.
On the other hand it is also proposed a kind of requirement, i.e. wish on the basis of not increasing existing wafer size
Increase surface area utilization rate, thus improve its machinable surface area.
In process for fabricating semiconductor device, conventional material such as SiO2, SiN etc. have bigger crisp
Property, when making the device such as membrane structures such as solaodes, it is easily caused when bending or stretch
SiO2, the Materials Fracture such as SiN so that the device architecture being connected separated, cause the device of entirety
Destructurized or make yield rate, production efficiency reduce during device fabrication.
Summary of the invention
The purpose of the present invention is intended at least solve above-mentioned technological deficiency, particularly thin to comprising bigger fragility
Membrane structure carries out stretching the problem easily making membrane structure fracture and cause the device architecture disconnection being connected.
For reaching above-mentioned purpose, the invention provides a kind of board structure, it is characterised in that including:
Base plate array, described base plate array includes according to predetermined direction arrangement at grade multiple
Substrate, each described substrate has first surface and second surface on the other side, described base plate array
It is arranged in the plane parallel with described substrate first surface；
Multiple substrates, it connects described adjacent substrate；
Flexible material layer, described flexible material layer be positioned at least part of described substrate surface and or at least portion
Divide on substrate surface.
According to one aspect of the invention, described substrate is vertical with the upstanding sidewall of connected substrate.
According to one aspect of the invention, the material of described substrate includes: insulant, metal, partly lead
Body material, polymer or a combination thereof.
According to one aspect of the invention, described flexible material layer includes metal, polymer, nano material
Or a combination thereof.
According to one aspect of the invention, described metal includes: gold, aluminum, silver, copper, titanium or a combination thereof.
According to one aspect of the invention, described polymer includes: silica gel, polypropylene, lucite,
Acrylic resin, acrylic acid, PMMA, Polycast, lucite, plexiglas, poly-right
Dimethylbenzene, epoxy resin, Merlon, silicone, polyurethane, polyamide, fluoropolymer,
Polyolefin, collagen, chitin, chitin, alginate fiber, polyvinylpyrrolidone, poly-second two
Alcohol, polyethylene glycol oxide, poly(ethylene oxide), polyvinyl alcohol, Polyethylene Glycol lactic acid, polylactic acid, poly-oneself
Lactone, polyamino acid, hydrogel, polydimethylsiloxane (PDMS) or a combination thereof；And
Described nano material includes nanotube, Graphene or a combination thereof.
According to one aspect of the invention, the thickness of described flexible material layer is 0.1～100 μm, is preferably
1～30 μm.
According to one aspect of the invention, described board structure also includes at least at the first of described substrate
The boundary layer that surface and/or second surface are formed.
According to one aspect of the invention, described baseplate material includes: single crystalline Si, monocrystalline Ge, monocrystalline
SiGe, polycrystalline Si, polycrystalline Ge, polycrystal SiGe, amorphous Si, amorphous Ge, amorphous SiGe, III-V
Or II-VI group compound semiconductor or a combination thereof.
According to one aspect of the invention, the thickness of described substrate is less than the 1/3 of described substrate thickness, described
The thickness of substrate is the distance between substrate first surface and second surface.
According to one aspect of the invention, described substrate has first surface and second surface corresponding thereto,
Described flexible material layer is positioned on first surface and the second surface of described substrate.
According to one aspect of the invention, at least part of material of described substrate is identical with the material of substrate.
In addition present invention also offers the manufacture method of a kind of board structure for semiconductor device, its
It is characterised by, comprises the steps:
A) providing substrate, described substrate includes first surface and the second surface relative with first surface；
B) first surface and second surface to described substrate are patterned；
C) at least two the first groove is formed from the first surface of described substrate；And from described substrate
Second surface forms at least one second groove, and the most each described second groove is positioned at adjacent two
Between described first groove, thus form at least two substrate and the vertical base of at least one substrate composition
Plate array；
D) vertical base plate array at least part of substrate surface and or at least part of shape on substrate surface
Become flexible material layer；
E) stretch described vertical base plate array and form planar substrates array.
According to one aspect of the invention, described step c) and d) between or after step e)
Form device on the substrate.
According to one aspect of the invention, at least part of material of described substrate is identical with described backing material.
According to one aspect of the invention, the flexible material layer in described step d) by spraying, CVD,
The technique of PVD, ALD, evaporation, spin coating or a combination thereof is formed.
According to one aspect of the invention, described flexible material layer includes metal, polymer, nano material
Or a combination thereof.
According to one aspect of the invention, described metal includes: gold, aluminum, silver, copper, titanium or a combination thereof.
According to one aspect of the invention, described polymer includes: silica gel, polypropylene, lucite,
Acrylic resin, acrylic acid, PMMA, Polycast, lucite, plexiglas, poly-right
Dimethylbenzene, epoxy resin, Merlon, silicone, polyurethane, polyamide, fluoropolymer,
Polyolefin, collagen, chitin, chitin, alginate fiber, polyvinylpyrrolidone, poly-second two
Alcohol, polyethylene glycol oxide, poly(ethylene oxide), polyvinyl alcohol, Polyethylene Glycol lactic acid, polylactic acid, poly-oneself
Lactone, polyamino acid, hydrogel, polydimethylsiloxane (PDMS) or a combination thereof；And
Described nano material includes nanotube, Graphene or a combination thereof.
According to one aspect of the invention, the thickness of described flexible material layer is 0.1～100 μm, is preferably
1～30 μm.
According to one aspect of the invention, in described step e), stretching step includes: along described predetermined direction
Stretch described vertical base plate array, so that the substrate connected between adjacent substrate bends to arc, described base
Plate has first surface and a second surface on the other side, and the first surface of described substrate and the second table
Face is vertical with the upstanding sidewall of arc substrate, and the first surface of the plurality of substrate and second surface are respectively
In two planes being parallel to each other.
According to one aspect of the invention, in described step e), the temperature of stretching step operation is 0 DEG C～300
℃。
According to one aspect of the invention, in described step e), the temperature of stretching step operation is 10 DEG C～90
℃。
According to one aspect of the invention, in described step e), adjacent described bent substrate bending direction
On the contrary, substrate is bent to form arcuate groove.
According to one aspect of the invention, there is in the arcuate groove that described bent substrate is formed described flexible material
Material.
According to one aspect of the invention, also include removing described flexible material after wherein said step e)
Step.
According to one aspect of the invention, also include at described step a): described substrate upper surface and
Lower surface forms substrate layer.
According to one aspect of the invention, wherein described step c) and d) between or in described step
D) also comprise the steps: from substrate, separate vertical base plate array between and e).
According to one aspect of the invention, the material of described substrate includes: insulating barrier, metal level, polymerization
Thing, semi-conducting material and combinations thereof.
According to one aspect of the invention, wherein said step c) middle formation the first groove and the second groove
Step includes: etches multiple first grooves from the first surface of described substrate, and stops at described second
On the substrate layer on surface；And etch multiple second grooves from the second surface of described substrate, and stop
On the substrate layer of described first surface.
According to one aspect of the invention, wherein step b) including:
The substrate layer of described first surface is formed the photoresist with multiple opening；
Etch described substrate layer, to remove the substrate layer of multiple opening parts of described first surface；
Remove described photoresist；
The substrate layer of described second surface is formed the photoresist with multiple opening；
Etch described substrate layer, to remove the substrate layer of multiple opening parts of second surface；
Remove described photoresist.
According to one aspect of the invention, step c) wherein forms described first groove and the second groove
Method includes dry etching, wet etching or a combination thereof.
According to one aspect of the invention, wherein step c) also include at least at described first groove and/or
The sidewall of the second groove forms the step of boundary layer.
According to one aspect of the invention, the degree of depth of one of the first groove and the second groove described at least a part of which
At least above being spaced sum between described substrate thickness and adjacent substrate.
According to one aspect of the invention, the thickness of wherein said substrate is less than the 1/3 of described substrate thickness.
The present invention efficiently utilizes the thickness of substrate, on the premise of not increasing whole wafer size,
Improve the machinable surface area of wafer or the utilization rate of surface area.By the surface shape at described substrate
Become flexible material layer, form, stretching vertical base plate array, the planar substrates array mistake that multiple substrate is connected
Cheng Zhong, even if rupturing owing to described substrate fragility is excessive, adjacent substrate can also be by flexibility
Material layer is connected, and realizes relatively easily multiple substrates are drawn into the plane being distributed in approximately the same plane
Array status, improves working (machining) efficiency and the yield rate of device architecture.
Aspect and advantage that the present invention adds will be given in following description part, and part will be from following
Description in become obvious, or recognized by the practice of the present invention.
Accompanying drawing explanation
Present invention aspect that is above-mentioned and/or that add and advantage are from retouching embodiment below in conjunction with the accompanying drawings
Will be apparent from easy to understand in stating, wherein:
Fig. 1 is the flow chart of the manufacture method of the board structure according to the embodiment of the present invention；
Fig. 2 is the plan view of the stage of initial manufacture of the board structure according to the embodiment of the present invention
Fig. 3-14 be each fabrication stage of the board structure according to the embodiment of the present invention along in Fig. 2
The profile of shown A-A ' hatching line；
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, its
In the most same or similar label represent same or similar element or there is same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining this
Bright, and be not construed as limiting the claims.Following disclosure provides many different embodiments
Or example is used for realizing the different structure of the present invention.In order to simplify disclosure of the invention, hereinafter to spy
Parts and the setting of usual practice are described.Certainly, they are the most merely illustrative, and are not intended to
Limit the present invention.Additionally, the present invention can in different examples repeat reference numerals and/or letter.This
Plant and repeat to be for purposes of simplicity and clarity, itself do not indicate discussed various embodiment and/or set
Relation between putting.Additionally, the various specific technique that the invention provides and the example of material, but
It is those of ordinary skill in the art it can be appreciated that the property of can be applicable to of other techniques and/or other materials
Use.It addition, fisrt feature described below second feature it " on " structure can include
First and second features are formed as the embodiment directly contacted, it is also possible to include that other feature is formed at
Embodiment between first and second features, such first and second features are not likely to be directly contact.
The present invention efficiently utilizes the thickness of substrate, on the premise of not increasing whole wafer size,
Improve the machinable surface area of wafer or the utilization rate of surface area.By the surface shape at described substrate
Become flexible material layer, during the vertical base plate array of stretching forms the array that multiple substrate is connected, i.e.
Making to rupture owing to described substrate fragility is excessive, adjacent substrate can also pass through flexible material layer phase
Even, realize relatively easily multiple substrates are drawn into the array status being distributed in approximately the same plane, carry
The working (machining) efficiency of high device architecture and yield rate.
The present invention provides one board structure as shown in fig. 13 that, including: base plate array, described
Base plate array includes arranging multiple substrates 150 at grade according to predetermined direction, each described
Substrate 150 has first surface 150-1 and second surface 150-2 on the other side, described base plate array
It is arranged in the plane parallel with described substrate first surface；Multiple substrates 120, it connects described phase
Adjacent substrate 150, described substrate 150 is vertical with the upstanding sidewall of connected substrate 120；Substrate
120 have first surface and second surface corresponding thereto, and the first surface of substrate is to bend in Figure 13
The concave surface of the arc of substrate, the second surface of substrate is the convex surface of arc；Flexible material layer
180, described flexible material layer 180 be positioned at described substrate 120 first surface and or at least part of substrate
On 150 surfaces；Described flexible material layer 180 can also be positioned at the first surface and second of substrate 120
On surface, to increase intensity and the tensile property of substrate.The material of described substrate 120 includes: insulation
Material, metal, semi-conducting material, polymer or a combination thereof.Described flexible material layer 180 includes gold
Genus, polymer, nano material or a combination thereof.Wherein metal includes: gold, aluminum, silver, copper, titanium or
A combination thereof；Polymer includes: silica gel, polypropylene, lucite, acrylic resin, acrylic acid,
PMMA, Polycast, lucite, plexiglas, Parylene, epoxy resin, poly-
Carbonic ester, silicone, polyurethane, polyamide, fluoropolymer, polyolefin, collagen, chitin,
Chitin, alginate fiber, polyvinylpyrrolidone, Polyethylene Glycol, polyethylene glycol oxide, polycyclic oxygen
Ethane, polyvinyl alcohol, Polyethylene Glycol lactic acid, polylactic acid, polycaprolactone, polyamino acid, hydrogel,
Polydimethylsiloxane (PDMS) or a combination thereof；And described nano material includes nanotube, graphite
Alkene or a combination thereof.
The thickness of described flexible material layer 180 is 0.1～100 μm, preferably 1～30 μm.Described base
Plate structure also includes at least at the first surface 150-1 and/or second surface 150-2 of described substrate 150
The boundary layer 160 formed.The material of described substrate includes: single crystalline Si, monocrystalline Ge, single crystalline Si Ge,
Polycrystalline Si, polycrystalline Ge, polycrystal SiGe, amorphous Si, amorphous Ge, amorphous SiGe, III-V or II-VI
Compound semiconductor or a combination thereof.The thickness of described substrate is less than the 1/3 of described substrate thickness, described
The thickness of substrate is the distance between substrate first surface and second surface.In oneainstance, substrate
At least part of material of 120 can be identical with the material of substrate 150, is the most all silicon.
Fig. 1 shows the flow process of the method for the board structure shown in formation Figure 13 of the embodiment of the present invention
Figure, comprises the following steps:
Step S101, with reference to Fig. 2, it is provided that wafer or substrate 101, in one embodiment of the present of invention
In, described substrate 101 is Semiconductor substrate, for example, one of silicon, germanium and compound semiconductor
Or a combination thereof, include but not limited to single crystalline Si, monocrystalline Ge, single crystalline Si Ge, especially, surface 101-1,
The crystal face of 101-2 be 110} or 112}, described substrate 101 can also is that polycrystalline Si, polycrystalline Ge,
Polycrystal SiGe, amorphous Si, amorphous Ge, amorphous SiGe, III-V or II-VI group compound semiconductor
Or a combination thereof or a combination thereof.In other embodiments, this substrate can be generated in several ways, such as
Deposit, epitaxial growth etc., described substrate can have n-type doping configuration or p-type doping configuration.Its
In, the thickness of this substrate can be 0.1-2mm, certainly the invention is not restricted to this.Described substrate includes
One surface 101-1 and second surface 101-2 corresponding thereto, with reference to Fig. 3.
Especially, the first and second surfaces of described substrate form substrate layer 100, described substrate
Layer 100 can have one or more layers structure, can configure the material that each layer is used as required
And thickness, for example, it is possible to include the insulating barrier covering described substrate upper and lower surface, as etch mask
Layer and it needs to according to different lithographic methods or the type of corrosive liquid and the degree of depth etc. of institute's etching structure
Design requirement, reasonably selects the material of substrate layer and the thickness of substrate layer in step S101.Example
As, when using wet etching, substrate layer 100 is preferably SiO2, SiN or a combination thereof, with reaction from
When son etching forms structure, substrate layer material can be SiO2, SiN or a combination thereof, it is also possible to be
The flexible polymers such as parylene (Parylene), certainly, substrate layer 100 can also as required
It is metal, semi-conducting material, other insulant and combinations thereof.
Step S102, as figures 2-6, first surface 101-1 and the second surface to described substrate
101-2 is patterned.Specifically, first surface and second surface at described substrate form substrate layer
After 100, the first surface 101-1 of described substrate 101 is formed there are the multiple of predetermined space configuration
The photoresist 110 of opening, exposes substrate layer 100, as shown in Figure 3 in the opening；Preferably, right
In the case of substrate is monocrystal material, the crystal orientation perpendicular with the length direction of described opening is<111>
Direction.With photoresist 110 as mask, etch described substrate layer 100, to exposing the of described substrate
One surface 101-1, described substrate layer 100 is formed multiple first opening 121 and multiple graphically
After substrate 120, as shown in Figure 4；Remove described photoresist 110, then, at described second surface
The upper photoresist 130 forming multiple openings with predetermined space configuration of 101-2, as shown in Figure 5；With
Photoresist 130 is mask, the described substrate layer 100 on etched substrate second surface, described to exposing
The second surface 101-2 of substrate, forms multiple second opening 123 and figure on described substrate layer 100
Substrate 120 after shape, as shown in Figure 6, finally removes the photoresist 130 on second surface.As
A preferred embodiment of the present invention, the interval between adjacent first opening 121 and adjacent second opening
Spacing between 123 is equal, and is staggered between the first opening 121 and the second opening 123.
The step of certain above-described formation composition is only example, and those skilled in the art can pass through
Many methods known in the field obtain the substrate of the composition described in the present embodiment, and these all can be answered
Use in the present embodiment, without deviating from protection scope of the present invention.Such as, above-mentioned on the substrate 101
Two surfaces form photoresist at twice and carry out the step of photoetching and can also be combined into a step, i.e.
Simultaneously form photoresist on both surfaces, be patterned, photoetching and removal photoresist simultaneously.
Then, in step s 103, as it is shown in fig. 7, with substrate 120 as mask, from first surface
First opening 121 of 101-1 and second opening 123 of second surface 101-2 etch described substrate, shape
Become at least two the first groove 125 and at least one second groove 126.Described first groove 125 He
Described second groove 126 opening direction is contrary.Sidewall at this first groove 125 calls substrate
First surface, the second groove 126 is referred to as the second surface of substrate.It is alternatively possible to etching all or
The described substrate of part 101, such as, can etch the first surface 101-1 of described substrate and stop at described
On the substrate layer 120 of second surface, and etch the second surface 101-2 of described substrate and stop at institute
State on the substrate layer 120 of first surface 101-1.Can certainly only etch a part of backing material,
The bottom of the i.e. first groove and the second groove does not arrive the substrate layer of substrate second surface and first surface
120.Described first groove 125 and the substrate 101 being adjacent between the second groove 126 form substrate
150, the width of described substrate 150 is suitable with the thickness of substrate 101, about 0.1-2mm；Substrate
The thickness of 150 is the distance between adjacent trenches 125 and 126, about 5-120 μm.Described
One groove and the second groove can have equal or not etc. a interval, especially, and can be with described in composition
Substrate, so that described first groove and the second groove are substantially parallel, these can need according to design
Arrange.The most each described second groove 126 between two adjacent described first grooves 125,
Described substrate to be divided at least two substrate 150 and at least one substrate 120.Described substrate 150
Being limited by the sidewall of the first groove 125 and the second groove 126, described substrate 120 connects adjacent
Two described substrates 150.Fig. 7 is the profile in A-A ' direction in substrate schematic diagram shown in Fig. 2.As
Shown in Fig. 7, the basic structure formed includes multiple substrate 150 being vertically arranged, referred to herein as
For vertical base plate array.
It should be known that can also be in step S102 if being formed without substrate layer 100 in step S101
In directly as mask, substrate is performed etching with photoresist, do not etch wear lining by controlling etching depth
The end, can also obtain the present invention vertical base plate array structure, it is achieved the purpose of the present invention.If do not etched
Wear substrate, then the part conduct between the substrate of bottom portion of groove that etching is formed to the another side of substrate
Heretofore described substrate, and the substrate portions between adjacent grooves is as heretofore described base
Plate.In this case, substrate and substrate are all a part for substrate, their material and substrate phase
With.
Preferably, the thickness of substrate 100 is less than the 1/3 of described substrate thickness, and the thickness of described substrate is
Distance between substrate first surface and second surface, or for belong to same substrate, adjacent two ditches
The distance between surface corresponding to the sidewall of groove.
Preferably, the degree of depth of one of described first groove 125 and the second groove 126 is more than substrate thickness
And it is spaced (i.e. first groove 125 or the width of the second groove 126) sum between adjacent substrate, this
Sample just can effectively utilize the thickness of substrate increases effective surface area, the area increased and groove
Depth-to-width ratio be correlated with, depth-to-width ratio is the biggest, and the area increased is the biggest.In one case, it is assumed that substrate
Thickness the most identical and with institute fluted width equal, the width of substrate the most identical and with all grooves
Deep equality, if the depth-to-width ratio of groove is n, then the active surface face of the board structure of the present invention
Long-pending be about original substrate surface area n/2 times.When the depth-to-width ratio of groove is 10 or above, effectively
Area increase is clearly.This needs the device of large-scale semiconductor material for manufacturing solaode etc.
Manufacturing cost can be effectively reduced for part.
According to the material character of described substrate, those skilled in the art can select suitable lithographic method
Forming described first groove 125 and the second groove 126, these are all without departing from protection scope of the present invention.
It is for instance possible to use anisotropic etching, such as reactive ion etching (RIE), deep reactive ion are carved
The erosion methods such as dry etching or wet etching and combinations thereof such as (DRIE) form described first groove and the
Two grooves.Especially, when described substrate comprises monocrystal material, such as single crystalline Si, monocrystalline Ge, list
When brilliant SiGe or a combination thereof, wet etching can be used, for example with potassium hydroxide (KOH), four
Ammonium hydroxide (TMAH) or ethylenediamine-catechol (EDP) equal solvent corrode,
The crystal face of described first surface and second surface be 110} or in the case of 112}, first formed
The crystal face on the surface corresponding to groove and its sidewall of the second groove is { 111}.First groove 125 and second
Distance (i.e. the distance of Semiconductor substrate 101 horizontal direction) between groove 126 determines substrate junction
The thickness of structure 150, thus this method photoetching controls the thickness of board structure 150.
Especially, in step s 103, described first groove 125 and second shown in Fig. 7 is being formed
After groove 126, device architecture can be formed on the first groove 125 sidewall.Such as, at least in institute
The sidewall (i.e. the first surface of substrate) stating the first groove 125 forms boundary layer 160, such as Fig. 8 institute
Show.Described boundary layer 160 can be multiple structure, in one embodiment of the invention, described boundary
Surface layer 160 can be multiple structure, including the first semiconductor layer 160-1 and the first electrode layer 160-2,
Described first semiconductor layer has the doping type different from described substrate, is i.e. doped to when described substrate
During p-type, described first semiconductor doping is N-shaped, when described substrate is doped to N-shaped, and described
Semi-conductor layer is doped to p-type.Described first semiconductor layer 160-1 can be spread by dopant ion
Or the method for deposition is formed, then can also be diffused further, in this embodiment, described first
Semiconductor layer 160-1 can be amorphous silicon a-Si, polysilicon poly-Si, monocrystal silicon or a combination thereof.
Especially, it is also possible to cover whole first groove 125 and form described boundary layer 160.
After forming the first semiconductor layer 160-1, it is formed on the first electrode layer 160-2.As this
A bright preferred embodiment, deposits transparent conductive oxide TCO (Transparent Conductive
Oxide) to form the first electrode layer 160-2.As a preferred embodiment of the present invention, when deposit,
Temperature controls below 550 DEG C.As a preferred embodiment of the present invention, TCO is SnO2With
ZnO, in other embodiment, TCO can also be In2O3、ITO、CdO、Cd2SnO4、FTO、
AZO or a combination thereof.
Same, it is also possible to after forming the board structure shown in Fig. 7, in the side of the second groove 126
Wall forms device architecture.Such as, at least sidewall (i.e. the second of substrate of described second groove 126
Surface) form another boundary layer 170, as shown in Figure 9.Described boundary layer 170 can be one layer
Or multiple structure.In one embodiment of the invention, described boundary layer 170 is multiple structure, bag
Include the second semiconductor layer 170-1 and the second electrode lay 170-2, the institute with doping type identical with substrate
State the method that the second semiconductor layer 170-1 can be spread by dopant ion or deposit to be formed, then
Can also be diffused further, in this embodiment, described second semiconductor layer 170-1 can be with right and wrong
Crystalline silicon a-Si, polysilicon poly-Si, monocrystal silicon or a combination thereof.Especially, it is also possible to cover whole
Individual second groove 126 forms described boundary layer 170.
Formed after the second semiconductor layer 170-1, be formed on the second electrode lay 170-2, equally,
The second electrode lay 170-2 can be formed by any conductive material, and such as metal material, as the present invention
A preferred embodiment, deposit transparent conductive oxide TCO (Transparent Conductive
Oxide) to form the second electrode lay 170-2.As a preferred embodiment of the present invention, when deposit,
Temperature controls below 550 DEG C.As a preferred embodiment of the present invention, TCO is SnO2With
ZnO, in other embodiment, TCO can also be In2O3、ITO、CdO、Cd2SnO4、FTO、
AZO or a combination thereof.
In step S104, cut described substrate 101, under being cut from substrate by vertical base plate array
Come.The substrate 120 of substrate is formed flexible material layer 180, stretches described substrate 101 and form base
Plate array, specifically as shown in Figure 10～14.
First, the edge of substrate wafer is cut away with laser beam or other cutting tool, as shown in Figure 10.
Figure 11 is the sectional view cutting away the vertical base plate array after edge wafer of the embodiment of the present invention.
After cutting substrate 101, divide on the first surface of described substrate and the substrate of second surface
Not Xing Cheng flexible material layer 180, as shown in figure 12.Described flexible material layer can pass through spraying, CVD,
The processes such as PVD, ALD, evaporation, spin coating or a combination thereof are formed.Described flexible material layer thickness
Being 1～30 μm, its material can be metal, polymer, nano material or a combination thereof, wherein metal
Including: gold, aluminum, silver, copper, titanium or a combination thereof；Polymer can be silica gel, polypropylene, organic
Glass, acrylic resin, acrylic acid, PMMA, Polycast, lucite, plexiglas,
Parylene, epoxy resin, Merlon, silicone, polyurethane, polyamide, fluoropolymer
Thing, polyolefin, collagen, chitin, chitin, alginate fiber, polyvinylpyrrolidone, poly-
Ethylene glycol, polyethylene glycol oxide, poly(ethylene oxide), polyvinyl alcohol, Polyethylene Glycol lactic acid, polylactic acid,
Polycaprolactone, polyamino acid, hydrogel, polydimethylsiloxane (PDMS) or a combination thereof；And
Described nano material includes nanotube, Graphene or a combination thereof.Selected flexible material needs have
Suitable flexibility, ductility and adhesive force.By controlling the parameter of spraying coating process, flexibility can be controlled
The pattern of material layer so that flexible material layer 180 is formed at first surface and second table of described substrate
On face, even if having partially flexible material to enter groove also can realize the purpose of the present invention.Preferably, soft
Ditch notch do not closed by property material.In another embodiment, flexible material can enter groove and cover
Substrate and substrate intersection (as shown in figure 12) even can cover the whole surface of substrate, as long as not
Affect operation substrate stretching flattened in subsequent technique.Covering substrate and the one of substrate intersection
Individual advantage is can to avoid substrate is stretched substrate in flattening process punishing in this boundary with substrate follow-up
From.
In another embodiment, flexible material can at least partly covering groove lower surface be (namely
The second surface of substrate).The relative first surface of substrate and second surface are all covered by flexible material layer
One advantage of lid is can to reduce, follow-up, substrate stretches the possibility that substrate in flattening process ruptures
Property.
The step of above-mentioned cutting substrate and the step covering flexible material layer the most first can be covered with exchanging order
Lid flexible material layer carries out cutting away the edge of substrate wafer again.
Then, whole board structure is smoothly stretched from vertical base plate array two ends so that the first groove
Pull open with the second groove, form the base plate array of plane, as shown in figure 13, flat for formed after stretching
The schematic diagram of face base plate array.The plurality of substrate 150 overturns 90 °, and substrate 120 bends to arc,
Connect adjacent substrate, the substrate that the plurality of substrate is vertical, adjacent with the upstanding sidewall of arc substrate
The bending curvature of 120 is contrary.The operation temperature stretching described substrate is 0 DEG C～300 DEG C, preferably 10
DEG C～90 DEG C, in this temperature range, described flexible material layer 180 softens, and along with substrate 120
Bending, be filled in substrate bending after formed arcuate groove in.Without flexible material layer, work as base
Sheet 120 material is SiO2, the fragility such as SiN bigger material time, drawing process is susceptible to fracture,
Vertical base plate array was ruptured before being drawn into planar substrates array at substrate, and substrate number is relatively
Less and substrate size the least in the case of, add the difficulty of stretching.Flexible material layer is used to connect phase
Adjacent substrate avoids the problem causing base plate array to disconnect due to substrate tension failure, stretched
Multiple substrates can be drawn into the planar substrates array being connected at grade, improve by Cheng Zhong
The efficiency of element manufacturing and yield rate.
It addition, when using the flexible polymers such as Parylene as substrate 120, Parylene
Having pliability Deng polymeric material itself, not easy fracture in drawing process, in conjunction with described flexible material
The bed of material 180, can increase the suppleness of substrate further, is drawn into by multiple substrates same flat simultaneously
The planar substrates array being connected on face, equally improves efficiency and the yield rate of element manufacturing.
Subsequently, device is carried out following process.The most mentioned above at the first groove and the second groove
Side formed device operation can vertical base plate array is stretched as a planar substrates array it
Rear execution.Alternatively, after forming planar substrates array, flexible material layer 180 can be corroded
Fall, in order to separate each substrate, as shown in figure 14.The substrate of each separation constitutes independent device
190.Remove flexible material layer 180 can utilize known in quasiconductor and micro mechanical system processing technique field
Technology carry out.
Below the method according to the invention defines the structure that multiple substrate is connected.Described substrate junction
Structure efficiently utilizes the thickness of substrate, on the premise of not increasing whole wafer size, it is thus achieved that more
The surface area of machinable wafer, improves the utilization rate of wafer.And, by described substrate
Surface forms flexible material layer, forms, stretching vertical base plate array, the planar substrates that multiple substrate is connected
During array, even if rupturing owing to described substrate fragility is excessive, adjacent substrate can also lead to
Cross flexible material layer to be connected, easier realize being drawn into multiple substrates being distributed in approximately the same plane
Planar substrates array status, otherwise due to substrate fracture, adjacent substrate separated, for even
A few substrate together, it is difficult to separated or be drawn into co-planar arrangement.Therefore the present invention
Method improve working (machining) efficiency and the yield rate of device architecture.
Although being described in detail about example embodiment and advantage thereof, it should be understood that without departing from the present invention's
In the case of spiritual and defined in the appended claims protection domain, these embodiments can be carried out various change
Change, substitutions and modifications.For other examples, those of ordinary skill in the art is it should be readily appreciated that keeping
While in scope, the order of processing step can change.
Additionally, the range of application of the present invention is not limited to the technique of specific embodiment described in description, machine
Structure, manufacture, material composition, means, method and step.From the disclosure, as this area
Those of ordinary skill will readily appreciate that, for the technique having existed at present or will having developed later,
Mechanism, manufacture, material composition, means, method or step, wherein they execution are right with what the present invention described
Answer function that embodiment is substantially the same or the result that acquisition is substantially the same, they can be entered according to the present invention
Row application.Therefore, claims of the present invention be intended to by these technique, mechanism, manufacture, material composition,
Means, method or step are included in its protection domain.
Claims (37)
1. the manufacture method of board structure for semiconductor device, it is characterised in that include as
Lower step:
A) providing substrate, described substrate includes first surface and the second surface relative with first surface；
B) first surface and second surface to described substrate are patterned；
C) at least two the first groove is formed from the first surface of described substrate；And from described substrate
Second surface forms at least one second groove, and the most each described second groove is positioned at adjacent two
Between described first groove, thus form at least two substrate and the vertical base of at least one substrate composition
Plate array；
D) at least part of substrate surface of vertical base plate array, flexible material layer, flexible material are formed
The layer adjacent substrate of connection avoids and causes base plate array to disconnect due to substrate tension failure；
E) stretch described vertical base plate array and form planar substrates array.
Method the most according to claim 1, wherein described step c) and d) between or
Device is formed on the substrate after step e).
Method the most according to claim 1, at least part of material of wherein said substrate is with described
Backing material is identical.
Method the most according to claim 1, the flexible material layer in wherein said step d) leads to
The technique crossing spraying, CVD, PVD, ALD, evaporation, spin coating or a combination thereof is formed.
5. according to the method described in claim 1 or 3, wherein said flexible material layer include metal,
Polymer, nano material or a combination thereof.
Method the most according to claim 5, wherein said metal includes: gold, aluminum, silver, copper,
Titanium or a combination thereof.
Method the most according to claim 5, wherein said polymer includes: silica gel, polypropylene,
Lucite, acrylic resin, acrylic acid, PMMA, lucite, plexiglas, poly-
Xylol, epoxy resin, Merlon, silicone, polyurethane, polyamide, fluoropolymer,
Polyolefin, collagen, chitin, chitin, alginate fiber, polyvinylpyrrolidone, poly-second two
Alcohol, polyethylene glycol oxide, poly(ethylene oxide), polyvinyl alcohol, Polyethylene Glycol lactic acid, polylactic acid, poly-oneself
Lactone, polyamino acid, hydrogel, polydimethylsiloxane (PDMS) or a combination thereof and
Described nano material includes nanotube, Graphene or a combination thereof.
8., according to the method described in claim 1 or 7, the thickness of wherein said flexible material layer is
0.1～100 μm.
9., according to the method described in claim 1 or 7, the thickness of wherein said flexible material layer is
1～30 μm.
Method the most according to claim 1, in wherein said step e), stretching step includes:
Described vertical base plate array is stretched, so that the substrate connected between adjacent substrate bends to arc along predetermined direction
Shape, described substrate has first surface and second surface on the other side, and the first table of described substrate
Face is vertical with the upstanding sidewall of arc substrate with second surface, the first surface of the plurality of substrate and
Two surfaces are respectively in two planes being parallel to each other.
11. according to the method described in claim 1 or 10, stretching step in wherein said step e)
The temperature of operation is 0 DEG C～300 DEG C.
12. according to the method described in claim 1 or 10, stretching step in wherein said step e)
The temperature of operation is 10 DEG C～90 DEG C.
13. methods according to claim 10, in wherein said step e), adjacent bending
Substrate bending direction is contrary, and substrate is bent to form arcuate groove.
14. methods according to claim 13, have in the arcuate groove that described bent substrate is formed
Described flexible material layer.
15. also include according to after the method described in claim 1 or 13, wherein said step e)
Remove the step of described flexible material layer.
16. methods according to claim 1, also include at described step a): at described substrate
First surface and second surface formed substrate layer.
17. methods according to claim 1, wherein described step c) and d) between or
Described step d) and e) between also comprise the steps: from substrate, separate vertical base plate array
Out.
18. include according to the method described in claim 1 or 16, the material of described substrate: insulating barrier,
Metal level, polymer, semi-conducting material and combinations thereof.
19. methods according to claim 16, form the first groove in wherein said step c)
Include with the step of the second groove: etch multiple first grooves from the first surface of described substrate, and stop
Only on the substrate layer of described second surface；And etch multiple second from the second surface of described substrate
Groove, and stop on the substrate layer of described first surface.
20. methods according to claim 16, wherein step b) including:
The substrate layer of described first surface is formed the photoresist with multiple opening；
Etch described substrate layer, to remove the substrate layer of multiple opening parts of described first surface；
Remove described photoresist；
The substrate layer of described second surface is formed the photoresist with multiple opening；
Etch described substrate layer, to remove the substrate layer of multiple opening parts of second surface；
Remove described photoresist.
21. methods according to claim 19, wherein form described first groove in step c)
Dry etching, wet etching or a combination thereof is included with the method for the second groove.
22. methods according to claim 1, wherein step c) also includes at least described first
The sidewall of groove and/or the second groove forms the step of boundary layer.
23. methods according to claim 19, one of wherein said first groove and the second groove
The degree of depth more than between described substrate thickness and adjacent substrate be spaced sum.
24. are less than institute according to the method described in claim 19 or 23, the thickness of wherein said substrate
State the 1/3 of substrate thickness.
The board structure that any one method that 25. 1 kinds utilize in claim 1-24 manufactures, it is special
Levy and be, including:
Base plate array, described base plate array includes according to predetermined direction arrangement at grade multiple
Substrate, each described substrate has first surface and second surface on the other side, described base plate array
It is arranged in the plane parallel with described substrate first surface；
Multiple substrates, it connects adjacent described substrate；
Flexible material layer, described flexible material layer is positioned at least part of described substrate surface, flexible material
The bed of material adjacent substrate of connection avoids and causes base plate array to disconnect due to substrate tension failure.
26. board structures according to claim 25, wherein said substrate and connected base
The upstanding sidewall of sheet is vertical.
27. board structures according to claim 25, the material of wherein said substrate includes: absolutely
Edge material, metal, semi-conducting material, polymer or a combination thereof.
28. board structures according to claim 25, wherein said flexible material layer include metal,
Polymer, nano material or a combination thereof.
29. board structures according to claim 28, wherein said metal includes: gold, aluminum,
Silver, copper, titanium or a combination thereof.
30. board structures according to claim 28, wherein said polymer includes: silica gel,
Polypropylene, lucite, acrylic resin, acrylic acid, PMMA, lucite, resin
Glass, Parylene, epoxy resin, Merlon, silicone, polyurethane, polyamide, contain
Fluoropolymer, polyolefin, collagen, chitin, chitin, alginate fiber, polyvinylpyrrolidine
Ketone, Polyethylene Glycol, polyethylene glycol oxide, poly(ethylene oxide), polyvinyl alcohol, Polyethylene Glycol lactic acid, poly-
Lactic acid, polycaprolactone, polyamino acid, hydrogel, polydimethylsiloxane (PDMS) or a combination thereof；
And
Described nano material includes nanotube, Graphene or a combination thereof.
31. according to the board structure described in claim 25,27 or 30, wherein said flexible material
The thickness of layer is 0.1～100 μm.
32. according to the board structure described in claim 25,27 or 30, wherein said flexible material
The thickness of layer is 1～30 μm.
33. board structures according to claim 25, also include at least at the first of described substrate
The boundary layer that surface and/or second surface are formed.
34. board structures according to claim 25, wherein said baseplate material includes: monocrystalline
Si, monocrystalline Ge, single crystalline Si Ge, polycrystalline Si, polycrystalline Ge, polycrystal SiGe, amorphous Si, amorphous
Ge, amorphous SiGe, III-V or II-VI group compound semiconductor or a combination thereof.
35. board structures according to claim 25, the thickness of wherein said substrate is less than described
The 1/3 of substrate thickness, the thickness of described substrate is the distance between substrate first surface and second surface.
36. board structures according to claim 25, wherein said substrate have first surface and
Second surface corresponding thereto, described flexible material layer is positioned at first surface and second table of described substrate
On face.
37. board structures according to claim 25, at least part of material of wherein said substrate with
The material of substrate is identical.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110025831.0A CN102610579B (en) | 2011-01-24 | 2011-01-24 | The board structure manufactured for semiconductor device and manufacture method thereof |
| PCT/CN2012/070534 WO2012100703A1 (en) | 2011-01-24 | 2012-01-18 | Substrate structure for semiconductor device manufacturing and method for manufacturing same |
| US13/355,946 US8754503B2 (en) | 2011-01-24 | 2012-01-23 | Substrate strip plate structure for semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110025831.0A CN102610579B (en) | 2011-01-24 | 2011-01-24 | The board structure manufactured for semiconductor device and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102610579A CN102610579A (en) | 2012-07-25 |
| CN102610579B true CN102610579B (en) | 2016-08-31 |
Family
ID=46527861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110025831.0A Expired - Fee Related CN102610579B (en) | 2011-01-24 | 2011-01-24 | The board structure manufactured for semiconductor device and manufacture method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102610579B (en) |
| WO (1) | WO2012100703A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579407A (en) * | 2012-07-26 | 2014-02-12 | 聚日（苏州）科技有限公司 | Solar cell and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201038172Y (en) * | 2007-04-29 | 2008-03-19 | 厦门冠宇科技有限公司 | Flexible solar cell assembly connection style |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4261169B2 (en) * | 2002-12-03 | 2009-04-30 | 株式会社カネカ | Translucent thin film solar cell and method for producing translucent thin film solar cell module |
| JP2009182002A (en) * | 2008-01-29 | 2009-08-13 | Kyocera Corp | Substrate connection structure, and electronic equipment |
| US20100012353A1 (en) * | 2008-07-18 | 2010-01-21 | Erel Milshtein | Elongated semiconductor devices, methods of making same, and systems for making same |
| EP2421026A4 (en) * | 2009-04-15 | 2017-11-29 | Huilong Zhu | Substrate structure for semiconductor device fabrication and method for fabricating the same |
-
2011
- 2011-01-24 CN CN201110025831.0A patent/CN102610579B/en not_active Expired - Fee Related
-
2012
- 2012-01-18 WO PCT/CN2012/070534 patent/WO2012100703A1/en active Application Filing
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201038172Y (en) * | 2007-04-29 | 2008-03-19 | 厦门冠宇科技有限公司 | Flexible solar cell assembly connection style |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012100703A1 (en) | 2012-08-02 |
| CN102610579A (en) | 2012-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10405118B2 (en) | Semiconductor devices having a membrane layer with smooth stress-relieving corrugations and methods of fabrication thereof | |
| US8742545B2 (en) | Substrate strip plate structure for semiconductor device and method of manufacturing the same | |
| US8759951B2 (en) | Method for manufacturing semiconductor device, and semiconductor device | |
| US8963268B2 (en) | Free-standing two-sided devices | |
| EP2296182A2 (en) | Solar cell and method for manufacturing the same | |
| WO2009108173A2 (en) | Methods for formation of substrate elements | |
| JP2004260170A (en) | Crystalline silicon die array and method for assembling crystalline silicon thin film on substrate | |
| US20110186879A1 (en) | Multifunctional tape | |
| US20060251995A1 (en) | Method for the production of an anti-reflecting surface on optical integrated circuits | |
| US9343602B2 (en) | Solar cell unit and method for manufacturing the same | |
| US8748321B2 (en) | Method for epitaxial devices | |
| US9716141B2 (en) | Applications for nanopillar structures | |
| CN102610579B (en) | The board structure manufactured for semiconductor device and manufacture method thereof | |
| CN101976657B (en) | Substrate structure for semiconductor device fabrication and method for fabricating same | |
| US8754503B2 (en) | Substrate strip plate structure for semiconductor device and method for manufacturing the same | |
| US20150175409A1 (en) | Method for fabricating multi-trench structure | |
| US7981772B2 (en) | Methods of fabricating nanostructures | |
| CN108463431A (en) | Method for manufacturing multilayer MEMS component and corresponding multilayer MEMS component | |
| CN110620033B (en) | Method for manufacturing metal nanowire or sheet and nanowire or sheet | |
| US7867805B2 (en) | Structure replication through ultra thin layer transfer | |
| CN101997026B (en) | Substrate structure processed by a substrate and manufacturing method thereof | |
| CN110136594B (en) | Display panel | |
| KR101653106B1 (en) | Solar cell and method for manufacturing the same | |
| CN110112151B (en) | TFT array manufacturing method and TFT device structure to be transferred | |
| US7224035B1 (en) | Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160831 Termination date: 20200124 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |