CN102610507A - Method for reducing gate-induced drain leakage of semiconductor device, and manufacturing method of MOS (metal oxide semiconductor) device - Google Patents

Method for reducing gate-induced drain leakage of semiconductor device, and manufacturing method of MOS (metal oxide semiconductor) device Download PDF

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Publication number
CN102610507A
CN102610507A CN201210081515XA CN201210081515A CN102610507A CN 102610507 A CN102610507 A CN 102610507A CN 201210081515X A CN201210081515X A CN 201210081515XA CN 201210081515 A CN201210081515 A CN 201210081515A CN 102610507 A CN102610507 A CN 102610507A
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China
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semiconductor device
drain
vertical direction
direction
method
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CN201210081515XA
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Chinese (zh)
Inventor
俞柳江
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上海华力微电子有限公司
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Priority to CN201210081515XA priority Critical patent/CN102610507A/en
Publication of CN102610507A publication Critical patent/CN102610507A/en

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Abstract

The invention provides a method for reducing the gate-induced drain leakage of a semiconductor device and a manufacturing method of an MOS (metal oxide semiconductor) device. The method for reducing the gate-induced drain leakage of the semiconductor device comprises the following steps: when annular injection is conducted at a source end and a drain end of the semiconductor device, the annular injection direction of the drain end is opposite to a first acute angle, the vertical direction of the first acute angle inclines to the drain end, and the annular injection direction of the source end is opposite to a second acute angle, and the vertical direction of the second acute angle inclines to the source end; and the included angle of the annular injection direction and the vertical direction of the drain end is larger than the included angle of the annular injection direction and the vertical direction of the source end. In the annular injection process, the injection angles of the drain end and the source end are adjusted, and under the condition of the constant effective length of a channel, the overlapping area of the drain end and a grid electrode is reduced, and the effective longitudinal electric field of the drain end is decreased, so that the gate-induced drain leakage current of the semiconductor device can be reduced.

Description

Reduce semiconductor device gate and induce the method for drain leakage, MOS device making method

Technical field

The present invention relates to field of semiconductor manufacture; More particularly, the present invention relates to a kind of semiconductor device gate that reduces induces the method for drain leakage, has adopted this to reduce MOS device making method and the MOS device of being processed by this MOS device making method that semiconductor device gate is induced the method for drain leakage.

Background technology

Gate-induced drain leaks (GIDL, Gate-Induced Drain Leakage) and is meant, is turn-offing when device under the situation of (off-state); (being Vg=0) is if drain electrode links to each other (being Vd=Vdd) with Vdd; Because the overlapping between grid and the drain electrode; Can there be highfield in overlapping region between grid and drain electrode, and band-to-band-tunneling effect (band to band tunneling) can take place under the highfield effect charge carrier, thereby causes the leakage current between the drain-to-gate.

The gate-induced drain leakage current has become the one of the main reasons of aspects such as influencing small size MOS device reliability, power consumption, and it also has material impact to the erasable operation of memory devices such as EEPROM simultaneously.When technology gets into sub-micro after the epoch, owing to device size dwindles day by day, numerous integrity problems of GIDL electric current initiation become serious further.

Summary of the invention

Technical problem to be solved by this invention is to having above-mentioned defective in the prior art, provides a kind of semiconductor device gate that can reduce effectively to induce the semiconductor device gate that reduces of drain leakage current to induce the method for drain leakage, adopted this to reduce MOS device making method and the MOS device of being processed by this MOS device making method that semiconductor device gate is induced the method for drain leakage.

According to a first aspect of the invention; A kind of method that semiconductor device gate is induced drain leakage that reduces is provided; It comprises: the drain terminal of semiconductor device and source end are being carried out ring-type when injecting; The relative vertical direction of injection direction that the drain terminal ring-type is injected is towards drain terminal first acute angle that tilts, and the relative vertical direction of injection direction that source end ring shape injects is end second acute angle that tilts towards the source; And, injection direction and vertical direction angle that injection direction that the drain terminal ring-type is injected and vertical direction angle inject greater than source end ring shape.

Preferably, induce in the method for drain leakage in the above-mentioned semiconductor device gate that reduces, injection direction that the drain terminal ring-type is injected and first acute angle between the vertical direction are 32 degree, and injection direction that source end ring shape injects and second acute angle between the vertical direction are 28 degree.

Preferably, induce in the method for drain leakage in the above-mentioned semiconductor device gate that reduces, extend in raceway groove the space charge region of source end metallurgical junction.

According to a second aspect of the invention, a kind of MOS device making method is provided, it has adopted the described according to a first aspect of the invention method that semiconductor device gate is induced drain leakage that reduces.

According to a third aspect of the invention we, the MOS device that provides a kind of described according to a second aspect of the invention MOS device making method to process.

The present invention is in the ring-type injection technology; Respectively the angle that drain terminal injects and the source end injects is adjusted; Keeping under the constant situation of raceway groove effective length; Reduced drain terminal and grid overlapping region, reduced effective longitudinal electric field of drain terminal, caused drain leakage current thereby reduced semiconductor device gate.

Description of drawings

In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:

Fig. 1 schematically shows the ring-type method for implanting according to prior art.

Fig. 2 schematically shows the ring-type method for implanting according to the embodiment of the invention.

Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.

Embodiment

In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.

Fig. 1 schematically shows the ring-type method for implanting according to prior art.

In common technology, for the short-channel effect (Short Channel Effect) of suppression device, can take ring-type to inject (Halo Implantation), will be injected among the device channel with the ion that transoid is leaked in the source.As shown in Figure 1, be example with the PMOS device, the x direction is the device channel direction among the figure, and the y direction is the vertical direction (abbreviating vertical direction as) of silicon chip surface, and the source is leaked and to be doped to group iii elements, boron element for example, ring-type is injected and can be adopted group-v element, for example P elements.

Usually, inject for the drain electrode 1 and the ring-type of source electrode 2, can adopt repeatedly to inject and accomplish, wherein ring-type is injected H1 and is represented 1 the ring-type of draining is injected, and ring-type is injected H2 and represented the ring-type of source electrode 2 is injected.Each dosage that injects equates that injection direction equates also that with y direction angulation injection direction becomes different angles to inject in the projection of silicon chip surface with the x direction.For example, the ring-type of PMOS device is injected to inject through four times and is accomplished, and injection direction is respectively 45 degree, 135 degree, 225 degree, 315 degree at the projection and the x direction angulation of silicon chip surface.

Inject through ring-type, near the space charge region the metallurgical junction that leak in the source distributes shown in dotted line among Fig. 1.Ring-type is injected the diffusion of space charge region in raceway groove that has limited metallurgical junction, has therefore suppressed the short-channel effect of device.And the overlapping region of drain terminal and grid has determined the zone of action of drain terminal longitudinal electric field, and this overlapping region is big more, and the zone of longitudinal electric field effect is just big more, and then the hot carrier injection current is big more, and the hot carrier implant damage is just serious more.

Fig. 2 schematically shows the ring-type method for implanting according to the embodiment of the invention.

In embodiments of the present invention, inject for the drain electrode 1 and the ring-type of source electrode 2, same adopt repeatedly to inject accomplish, wherein ring-type is injected H11 and is represented 1 the ring-type of draining is injected, ring-type is injected H22 and is represented the ring-type of source electrode 2 is injected.

In an embodiment of the present invention; Adjust each time ring-type and inject and y direction angulation, make that when the drain terminal ring-type was injected, injection direction and y angular separation increased; When source end ring shape injects; Injection direction and y angular separation reduce, thereby make the space charge region of drain terminal be compressed from channel direction, and the source end gets the space charged region and in raceway groove, extends.That is, when drain terminal and source end ring shape injected, the relative y direction of injection direction that the drain terminal ring-type is injected was towards drain terminal first acute angle that tilts, and the relative y direction of injection direction that source end ring shape injects is end second acute angle that tilts towards the source; And, injection direction and y angular separation (second acute angle) that the injection direction that the drain terminal ring-type is injected and y angular separation (first acute angle) inject greater than source end ring shape.

For example, in 45nm cmos device technology, the ring-type implant angle becomes 30 degree with the y axle usually; In the specific embodiment of the present invention; When the drain terminal ring-type was injected, injection direction became 32 degree with the y axle, when the end ring shape injects in the source; Injection direction becomes 28 degree with the y axle, to reduce conductor device gate-induced drain leakage current.

But said angle 32 degree and 28 degree only are exemplary, and it is not limited to the present invention.Therefore, the present invention can adopt other suitable angle.

For example (as shown in Figure 2); Still inject the ring-type of accomplishing for four times with the PMOS device and be injected to example, the drain terminal ring-type is injected with both direction, is respectively the direction that becomes 45 degree and 315 degree with the x direction; When this both direction injects; Therefore suitably increase with the axial angle of y, being injected in the raceway groove group-v element dosage such as phosphorus increases, and the space charge region of drain terminal metallurgical junction is compressed from channel direction.Source end ring shape injects also has both direction; Be respectively the direction that becomes 135 degree and 225 degree with the x direction, when this both direction injects, suitably reduce with the axial angle of y; Therefore be injected in the raceway groove group-v element dosage such as phosphorus and reduce, extend in raceway groove the space charge region of source end metallurgical junction.

At drain terminal; Because the drain terminal space charge region is compressed from channel direction; Drain terminal and grid overlapping region reduce, and drain when gate turn-off when meeting Vdd, reduce in the sphere of action of the longitudinal electric field of grid and drain terminal overlapping region; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.

In addition, though the space charge region of drain terminal obtains compression, extend in raceway groove the space charge region of source end, so the length of effective channel of device remains unchanged basically, and other performances of device are able to keep.

In a word, the MOS device making method according to the embodiment of the invention at least also has following advantage:

1. do not increase existing MOS device fabrication step.

2. when increasing the drain terminal ring-type and injecting and the angle of y axle; Make the drain terminal space charge region be compressed along channel direction, drain terminal and grid overlapping region reduce, and the sphere of action of longitudinal electric field reduces; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.

3. when the distance of the dopant ion of drain terminal and raceway groove was zoomed out, the dopant ion of source end and the distance of raceway groove were furthered, so the length of effective channel of device remains unchanged basically, and other performances of device are able to keep.

The present invention injects (Halo Implantation) technology in ring-type; Respectively the angle that drain terminal injects and the source end injects is adjusted; Keeping under the constant situation of raceway groove effective length; Reduced drain terminal and grid overlapping region, reduced effective longitudinal electric field of drain terminal, caused drain leakage current thereby reduced semiconductor device gate.

It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (5)

1. one kind reduces the method that semiconductor device gate is induced drain leakage; It is characterized in that comprising: the drain terminal of semiconductor device and source end are being carried out ring-type when injecting; The relative vertical direction of injection direction that the drain terminal ring-type is injected is towards drain terminal first acute angle that tilts, and the relative vertical direction of injection direction that source end ring shape injects is end second acute angle that tilts towards the source; And, injection direction and vertical direction angle that injection direction that the drain terminal ring-type is injected and vertical direction angle inject greater than source end ring shape.
2. according to claim 1ly reduce the method that semiconductor device gate is induced drain leakage; It is characterized in that; Injection direction that the drain terminal ring-type is injected and first acute angle between the vertical direction are 32 degree, and injection direction that source end ring shape injects and second acute angle between the vertical direction are 28 degree.
3. according to claim 1 and 2ly reduce the method that semiconductor device gate is induced drain leakage, it is characterized in that the space charge region of source end metallurgical junction is extended in raceway groove.
4. a MOS device making method is characterized in that adopting the method that semiconductor device gate is induced drain leakage that reduces according to claim 1.
5. MOS device that MOS device making method according to claim 4 is processed.
CN201210081515XA 2012-03-23 2012-03-23 Method for reducing gate-induced drain leakage of semiconductor device, and manufacturing method of MOS (metal oxide semiconductor) device CN102610507A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200419655A (en) * 2003-03-17 2004-10-01 Taiwan Semiconductor Mfg Transistor having asymmetric dual-pocket implantation region and its manufacturing method
CN101529580A (en) * 2005-09-29 2009-09-09 德克萨斯仪器股份有限公司 SRAM cell with asymmetrical transistors for reduced leakage
US20100327374A1 (en) * 2009-06-26 2010-12-30 Kamel Benaissa Low cost transistors using gate orientation and optimized implants
CN102446718A (en) * 2011-09-08 2012-05-09 上海华力微电子有限公司 Method for reducing hot carrier implantation damage of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200419655A (en) * 2003-03-17 2004-10-01 Taiwan Semiconductor Mfg Transistor having asymmetric dual-pocket implantation region and its manufacturing method
CN101529580A (en) * 2005-09-29 2009-09-09 德克萨斯仪器股份有限公司 SRAM cell with asymmetrical transistors for reduced leakage
US20100327374A1 (en) * 2009-06-26 2010-12-30 Kamel Benaissa Low cost transistors using gate orientation and optimized implants
CN102446718A (en) * 2011-09-08 2012-05-09 上海华力微电子有限公司 Method for reducing hot carrier implantation damage of semiconductor device

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Application publication date: 20120725