CN102610504A - Method for preparing floating gate - Google Patents
Method for preparing floating gate Download PDFInfo
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- CN102610504A CN102610504A CN2012100665275A CN201210066527A CN102610504A CN 102610504 A CN102610504 A CN 102610504A CN 2012100665275 A CN2012100665275 A CN 2012100665275A CN 201210066527 A CN201210066527 A CN 201210066527A CN 102610504 A CN102610504 A CN 102610504A
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- barrier layer
- floating boom
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Abstract
The invention provides a method for preparing a floating gate. The method includes the specific steps: firstly, forming STI (shallow trench isolation) and sequentially depositing a gate oxidation layer and the floating gate; secondly, sequentially depositing a first barrier layer and a second barrier layer; thirdly, performing CMP (chemical mechanical polishing) for the second barrier layer until reaching the first barrier layer; fourthly, removing the first barrier layer on an STI area by the aid of the second barrier layer; fifthly, removing the floating gate on the STI area by the aid of the second barrier layer; sixthly, sequentially removing the second barrier layer and the first barrier layer on an active area by a wet process; and seventhly, exposing the floating gate to form a floating gate structure. The floating gate is completely deposited from a furnace tube without CMP, the thickness of the floating gate is uniform, programming and wiping performances are effectively improved, and the floating gate is extremely practical.
Description
Technical field
The present invention relates to the semiconductor device processing technology field, particularly a kind of preparation method of floating boom.
Background technology
Since the D.Kahng of AT&T Labs in 1967 and S.M.Sze have proposed the non-volatile semiconductor memory of FGS floating gate structure, the floating boom semiconductor memory of the MOSFET structure of piling up based on grid just on capacity, cost and power consumption with occupy great advantage replaced before the long-term magnetic memory that uses.On this basis; Toshiba Corp has successfully proposed the notion of Flash memory in 1984, the Flash memory remains the main flow device on the non-volatile semiconductor memory market up to now, but along with the microelectric technique node is constantly pushed ahead; To further reduce of technology live width; Traditional flash based on FGS floating gate structure meets with serious technological difficulties, and main cause is the lasting attenuate owing to tunneling medium layer, and leaky is serious all the more; But seriously limited the downsizing of Flash device, the density refractory that causes floating-gate memory spare is to promote.
Floating boom formula non-volatility memorizer is at present by a large amount of uses and universally recognized main flow non-volatility memorizer, is widely used in electronics and computer equipment.Traditional FGS floating gate structure memory cell is because the restriction of structure and material, causes between requirement and the demand of storing steady in a long-term of quick write/erase operation and produced serious contradiction.And along with dwindling of characteristic size, this contradiction is more remarkable.
Along with characteristic size is advanced into nanoscale, when dwindling memory cell, improving storage density, improve the storage reading and writing data, wipe and keep performance, become the key issue that present floating gate memory cell development faces.This just requires on material and structure, traditional floating gate memory cell to be improved.
Along with the minimizing of device size, a lot of companies floating boom prepare method with FG-CMP.The method has the shortcoming of three aspects: (1) owing to the characteristic of CMP, depression (dishing) and erosion (erosion) phenomenon are more serious, have influenced the height of floating boom.(2) uniformity of Waffer edge and center can not guarantee, causes floating boom different with the height at center on the edge of.The inhomogeneities of common 12 cun poly-CMP (non-uniformity) is usually more than 10%.(3) differing heights of floating boom has influence on coupling coefficient, and then the performance that has influence on programming (program) and wipe (erase).
The folded grid memory of standard is made up of control gate (CG:Control Gate), inter polysilicon oxide layer (IPO:Interpoly Oxide), floating boom (FG:Floating Gate), gate oxide (GO:Gate Oxide) and source, leakage, substrate.Current floating boom preparation technology flow process: at first separator preparation, deposit gate oxide and floating boom again, carry out the floating boom cmp at last.
Chinese patent CN200710121367 relates to technical field of non-volatile, discloses the non-volatility memorizer of the brilliant FGS floating gate structure of a kind of multi-layer nano, comprising: the Semiconductor substrate 11 that is used to support whole non-volatility memorizer; In Semiconductor substrate 11, mix and form source electrode 9 and drain electrode 10; At source electrode 9 and the raceway groove 12 between 10 of draining; Be positioned at the tunnel oxide 13 on the raceway groove 12; Be used to control the controlled oxidation layer 14 of the brilliant FGS floating gate structure oxidation of multi-layer nano; Be positioned at the gate electrode 16 on the controlled oxidation layer 14; The brilliant FGS floating gate structure 15 of multi-layer nano between tunnel oxide 13 and controlled oxidation layer 14 is used for the floating gate memory cell as non-volatility memorizer.The present invention discloses a kind of method for preparing the brilliant FGS floating gate structure non-volatility memorizer of multi-layer nano.The present invention solves the programming time of individual layer nanocrystalline floating gate memory and the contradiction between memory time, the memory time of boost device under short programming time prerequisite.
Chinese patent CN200910078478 discloses a kind of tungsten titanium alloy nanocrystalline gate-floating structure that is used for flash memory, belongs to microelectronics technology.This structure comprises silicon substrate, and the silicon oxide layer, high dielectric constant film, tungsten titanium alloy nanocrystalline charge storage layer, barrier layer and the gate material layer that on said silicon substrate, cover successively.Structure of the present invention has improved memory properties such as the program/erase efficient, program/erase (P/E) speed, effective charge storage capacity, data retention characteristics, program/erase tolerance of the Nonvolatile storage unit of FGS floating gate structure.The present invention discloses a kind of method of making tungsten titanium alloy nanocrystalline gate-floating structure.Method of the present invention is easy, and is compatible with the traditional cmos silicon planner technology.
Chinese patent CN200910302491 relates to the semiconductor device processing technology field; Be specifically related to a kind of preparation method of the nanocrystalline floating gate memory based on nitrogen treatment; Said method is included on the silicon substrate growth and wears dielectric layer then, and in that to wear dielectric layer upper surface grown silicon then nanocrystalline; Silicon nanocrystal is carried out nitrogen treatment, the silicon nanocrystal surface deposition control gate dielectric layer behind nitrogen treatment, deposit polysilicon on the control gate dielectric layer; The etching sandwich construction forms the zone of making grid side wall and source electrode, drain electrode to silicon substrate; Make grid side wall, grid, source electrode and drain electrode, form floating-gate memory.The present invention can be used for the memory cell of non-volatility memorizer, and it is big to have charge storage capacity, and is simple in structure, and reliability is high, and is good with the traditional cmos process compatibility, is easy to produce in batches.
Listed the common computation model of coupling coefficient below:
A1: floating boom is with the face coupling area (flat) of control gate
A2: floating boom is with the sidewall coupling area (sidewall) of control gate
A3: floating boom is with the coupling area (channel) of substrate channel
H: the height of floating boom
L: the length of floating boom
W: the width of floating boom
T1: gate oxide (GO:Gate Oxide)
T2: inter polysilicon oxide layer (IPO:Interpoly Oxide)
Common depression and erosion problem appear in current floating boom preparation technology flow process easily.The reason that produces depression is that lapping liquid exists the selection ratio, and the grinding rate between the unlike material is different.Producing the reason that corrodes is when grinding the target material, and non-target material was caused polishing.Skew of this floating boom height (variation) and inhomogeneities (non-uniformity) can cause the variation of coupling coefficient.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of preparation method of floating boom, be very suitable for practicality.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.
The present invention provides a kind of preparation method of floating boom, it is characterized in that: the concrete steps of said method are following:
Step 1: form shallow trench isolation from (STI), deposit gate oxide and floating boom successively;
Step 2: deposit first barrier layer and second barrier layer more successively;
Step 3: carry out the cmp (CMP) on second barrier layer then, until first barrier layer;
Step 4: as the barrier layer, remove first barrier layer of shallow trench isolation above (STI) zone with second barrier layer;
Step 5: as the barrier layer, remove the floating boom of shallow trench isolation above (STI) zone with second barrier layer;
Step 6: remove second barrier layer and first barrier layer above the active area successively with wet method again;
Step 7: spill floating boom, form FGS floating gate structure.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize:
The degree of depth that the shallow trench isolation that forms in the said step 1 leaves is 2500A～3500A.
The height that the shallow trench isolation that forms in the said step 1 leaves is 500A～2000A.
The thickness of the gate oxide of the deposition in the described step 1 is 90A～110A.
The height of the floating boom that deposits in the said step 1 is 200A～600A.
The length of the floating boom that deposits in the said step 1 is 32nm～0.20um.
The width of the floating boom that deposits in the said step 1 is 60nm～0.3um.
First barrier layer in the described step 2 is SiN.
Second barrier layer in the described step 2 is an oxide.
The thickness on first barrier layer in the described step 2 is 100A～400A.
The thickness on second barrier layer in the described step 2 is 300A～1000A.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 illustrates the preparation method's of a kind of floating boom that the present invention relates to process chart.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the preparation method to a kind of floating boom of proposing according to the present invention specifies as follows.
Different embodiments of the invention will details are as follows, with the different techniques characteristic of embodiment of the present invention, will be understood that, the unit of the specific embodiment of the following stated and configuration are in order to simplify the present invention, and it is merely example and does not limit the scope of the invention.
Embodiment 1
At first form shallow trench isolation from (STI), the degree of depth that shallow trench isolation leaves is 2500A, and the height that shallow trench isolation leaves is 500A.Deposit gate oxide and floating boom more successively; The thickness of the gate oxide of deposition is 90A, and the height of floating boom is 200A, and length is 32nm, and width is 60nm.And then deposit first barrier layer and second barrier layer successively; First barrier layer is SiN, and thickness is 100A, and second barrier layer is an oxide, and thickness is 300A.Carry out the cmp (CMP) on second barrier layer then, until first barrier layer.Again with second barrier layer as the barrier layer, remove shallow trench isolation first barrier layer above (STI) zone, and remove shallow trench isolation floating boom above (STI) zone; Then remove second barrier layer and first barrier layer above the active area successively with wet method again; Spill floating boom at last, form FGS floating gate structure.
Embodiment 2
At first form shallow trench isolation from (STI), the degree of depth that shallow trench isolation leaves is 3500A, and the height that shallow trench isolation leaves is 2000A.Deposit gate oxide and floating boom more successively; The thickness of the gate oxide of deposition is 110A, and the height of floating boom is 600A, and length is 0.20um, and width is 0.3um.And then deposit first barrier layer and second barrier layer successively; First barrier layer is SiN, and thickness is 400A, and second barrier layer is an oxide, and thickness is 1000A.Carry out the cmp (CMP) on second barrier layer then, until first barrier layer.Again with second barrier layer as the barrier layer, remove shallow trench isolation first barrier layer above (STI) zone, and remove shallow trench isolation floating boom above (STI) zone; Then remove second barrier layer and first barrier layer above the active area successively with wet method again; Spill floating boom at last, form FGS floating gate structure.
Embodiment 3
At first form shallow trench isolation from (STI), the degree of depth that shallow trench isolation leaves is 3000A, and the height that shallow trench isolation leaves is 1000A.Deposit gate oxide and floating boom more successively; The thickness of the gate oxide of deposition is 100A, and the height of floating boom is 400A, and length is 64nm, and width is 80nm.And then deposit first barrier layer and second barrier layer successively; First barrier layer is SiN, and thickness is 100A, and second barrier layer is an oxide, and thickness is 300A.Carry out the cmp (CMP) on second barrier layer then, until first barrier layer.Again with second barrier layer as the barrier layer, remove shallow trench isolation first barrier layer above (STI) zone, and remove shallow trench isolation floating boom above (STI) zone; Then remove second barrier layer and first barrier layer above the active area successively with wet method again; Spill floating boom at last, form FGS floating gate structure.
Embodiment 4
At first form shallow trench isolation from (STI), the degree of depth that shallow trench isolation leaves is 3200A, and the height that shallow trench isolation leaves is 1500A.Deposit gate oxide and floating boom more successively; The thickness of the gate oxide of deposition is 110A, and the height of floating boom is 500A, and length is 80nm, and width is 80nm.And then deposit first barrier layer and second barrier layer successively; First barrier layer is SiN, and thickness is 100A, and second barrier layer is an oxide, and thickness is 300A.Carry out the cmp (CMP) on second barrier layer then, until first barrier layer.Again with second barrier layer as the barrier layer, remove shallow trench isolation first barrier layer above (STI) zone, and remove shallow trench isolation floating boom above (STI) zone; Then remove second barrier layer and first barrier layer above the active area successively with wet method again; Spill floating boom at last, form FGS floating gate structure.
The present invention provides a kind of preparation method of floating boom, after forming separator (STI) and deposition floating boom successively, deposits first barrier layer (SiN) and second barrier layer (Oxide) more successively.Be Oxide CMP then, be parked on the first following barrier layer SiN.Because active area (AA, ACT) zone is lower than separator (STI) zone, and the Oxide here also can keep.As barrier layer (stop layer), remove first barrier layer (SiN) and following floating boom above the STI zone with this Oxide successively; And then remove second barrier layer (Oxide) and first barrier layer (SiN) above the active area successively with wet method, expose following floating boom.Because this layer floating boom is that boiler tube deposits out fully, do not pass through the grinding of CMP, so its thickness is uniformly, the performance that has improved programming (program) effectively and wiped (erase).
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (11)
1. the preparation method of a floating boom, it is characterized in that: the concrete steps of said method are following:
Step 1: form shallow trench isolation from (STI), deposit gate oxide and floating boom successively;
Step 2: deposit first barrier layer and second barrier layer more successively;
Step 3: carry out the cmp (CMP) on second barrier layer then, until first barrier layer;
Step 4: as the barrier layer, remove first barrier layer of shallow trench isolation above (STI) zone with second barrier layer;
Step 5: as the barrier layer, remove the floating boom of shallow trench isolation above (STI) zone with second barrier layer;
Step 6: remove second barrier layer and first barrier layer above the active area successively with wet method again;
Step 7: spill floating boom, form FGS floating gate structure.
2. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the degree of depth that the shallow trench isolation that forms in the said step 1 leaves is 2500A ~ 3500A.
3. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the height that the shallow trench isolation that forms in the said step 1 leaves is 500A ~ 2000A.
4. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the thickness of the gate oxide of the deposition in the described step 1 is 90A ~ 110A.
5. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the height of the floating boom that deposits in the said step 1 is 200A ~ 600A.
6. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the length of the floating boom that deposits in the said step 1 is 32nm ~ 0.20um.
7. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the width of the floating boom that deposits in the said step 1 is 60nm ~ 0.3um.
8. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: first barrier layer in the described step 2 is SiN.
9. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: second barrier layer in the described step 2 is an oxide.
10. the preparation method of a kind of floating boom as claimed in claim 1, it is characterized in that: the thickness on first barrier layer in the described step 2 is 100A ~ 400A.
11. the preparation method of a kind of floating boom as claimed in claim 1 is characterized in that: the thickness on second barrier layer in the described step 2 is 300A ~ 1000A.
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| CN2012100665275A CN102610504A (en) | 2012-03-14 | 2012-03-14 | Method for preparing floating gate |
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| CN2012100665275A CN102610504A (en) | 2012-03-14 | 2012-03-14 | Method for preparing floating gate |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050199956A1 (en) * | 2004-03-10 | 2005-09-15 | Yi Ding | Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures |
| CN100501928C (en) * | 1999-02-23 | 2009-06-17 | 西利康存储技术股份有限公司 | Fabrication process of flash memory cell with self-aligned gates |
| CN101800172A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Manufacturing method of self-aligned polysilicon floating gate |
| US20110171819A1 (en) * | 2004-10-29 | 2011-07-14 | Yukihiro Utsuno | Semiconductor device and method for fabricating thereof |
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2012
- 2012-03-14 CN CN2012100665275A patent/CN102610504A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100501928C (en) * | 1999-02-23 | 2009-06-17 | 西利康存储技术股份有限公司 | Fabrication process of flash memory cell with self-aligned gates |
| US20050199956A1 (en) * | 2004-03-10 | 2005-09-15 | Yi Ding | Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures |
| US20110171819A1 (en) * | 2004-10-29 | 2011-07-14 | Yukihiro Utsuno | Semiconductor device and method for fabricating thereof |
| CN101800172A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Manufacturing method of self-aligned polysilicon floating gate |
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Application publication date: 20120725 |