CN102609023A - Built-in analog power supply circuit - Google Patents
Built-in analog power supply circuit Download PDFInfo
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- CN102609023A CN102609023A CN2012100638668A CN201210063866A CN102609023A CN 102609023 A CN102609023 A CN 102609023A CN 2012100638668 A CN2012100638668 A CN 2012100638668A CN 201210063866 A CN201210063866 A CN 201210063866A CN 102609023 A CN102609023 A CN 102609023A
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- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 238000004088 simulation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 230000000087 stabilizing effect Effects 0.000 abstract 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 5
- 238000010276 construction Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 1
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Abstract
The invention discloses a built-in analog power supply circuit comprising a band gap reference source, an operational amplifier, a first compensation capacitor, a second compensation capacitor, a first voltage stabilizing capacitor, a second voltage stabilizing capacitor, a high-voltage PMOS (P-channel Metal Oxide Semiconductor) power tube, a low-voltage NMOS (N-channel Metal Oxide Semiconductor) power tube, a first resistor, a second resistor and an external power voltage; an output end of the operational simplifier and an upper electrode plate of the first compensation capacitor are connected with the grid of the high-voltage PMOS power tube; and the drain of the high-voltage PMOS power tube, one end of the second resistor, a lower electrode plate of the second compensation capacitor, and the drain of the low-voltage NMOS tube are connected with the upper electrode plate of the first voltage stabilizing capacitor. With the adoption of the built-in analog power supply circuit, the capacitance value of the first voltage stabilizing capacitor is smaller and can be generated from the inside, and the increase of the system cost caused by providing capacitance from outside of the chip is avoided.
Description
Technical field
The present invention relates to circuit field, particularly relate to a kind of interior modeling and intend power circuit.
Background technology
In the industrial electronic field,,, interior modeling is widely used so intending power circuit because the chip exterior supply voltage is higher.This can guarantee the application of low-voltage device in large scale integrated circuit, and can reduce chip area, reduces power consumption.
It is as shown in Figure 1 that power circuit is intended in modeling in of the prior art, is made up of generating circuit from reference voltage 101, operation amplifier circuit 102 and output stage 103.Generating circuit from reference voltage 101 is by the resistance R 3 and R4 series connection generation of same type, and the reference voltage Vref that is produced is supplied with the negative input end of operational amplifier OPA; The output stage of operational amplifier OPA links to each other with the grid of PMOS power tube P1; The drain electrode of P1, the top crown of C1 link to each other with the upper end of resistance R 2, and this node also is the output node of internal simulation power supply VCC; The upper end of the lower end of resistance R 2, resistance R 1 links to each other with the positive input terminal of operational amplifier OPA; Outer power voltage VDDA links to each other with the upper end of R4, the power end of operational amplifier OPA, source electrode and the substrate of P1; The lower ends of the ground end of the lower end of ground voltage and R3, operational amplifier OPA, the lower end of resistance R 1 and capacitor C 1.When system's operate as normal; The internal simulation supply voltage is VCC=VDDA* (R3/ (R4+R3)) * ((R1+R2)/R1); When outer power voltage VDDA when floating in a big way, the VCC variation range also can be bigger, so this circuit can not be applied to the bigger situation of outer power voltage domain of walker.
In the prior art, for the phase margin that guarantees that system's loop is enough, and avoid internal power source voltage to start overshoot puncture load low-voltage device, usually need be located at the VCC output node to dominant pole, inferior dominant pole is arranged on operational amplifier OPA output terminal.This just need the capacitance of C1 establish very big, generally need external capacitor to realize, but external capacitor can increase system cost.
Summary of the invention
The purpose of this invention is to provide a kind of interior modeling and intend power circuit, just needed electric capacity can be provided, do not need external capacitor, and then can reduce the cost that power circuit is intended in interior modeling in inside circuit.
For realizing above-mentioned purpose, the invention provides following scheme:
Power circuit is intended in modeling in a kind of, comprising: band gap reference, operational amplifier, first building-out capacitor, second building-out capacitor, first electric capacity of voltage regulation, second electric capacity of voltage regulation, high voltage PMOS power tube, low pressure NMOS pipe, first resistance, second resistance and outer power voltage;
The reference voltage output end of said band gap reference links to each other with the negative input end of said operational amplifier; The reference voltage output end of said band gap reference is through the said second electric capacity of voltage regulation ground connection;
The top crown of the output terminal of said operational amplifier, said first building-out capacitor links to each other with the grid of said high voltage PMOS power tube; The drain electrode of one end of the drain electrode of said high voltage PMOS power tube, said second resistance, the bottom crown of said second building-out capacitor, said low pressure NMOS pipe links to each other with the top crown of said first electric capacity of voltage regulation; The grid of one end of the other end of said second resistance, said first resistance, the top crown of said second building-out capacitor, said low pressure NMOS pipe links to each other with the positive input terminal of said operational amplifier; Said outer power voltage links to each other with the bottom crown of the power end of the power end of said band gap reference, said operational amplifier, said first building-out capacitor, the source electrode and the substrate of said high-voltage power pipe; The bottom crown of the source electrode of the ground end of the ground end of said band gap reference, said operational amplifier, the other end of said first resistance, said low pressure NMOS pipe and substrate, said first electric capacity of voltage regulation links to each other with ground voltage.
Optional, said band gap reference, said operational amplifier, said first building-out capacitor and said high voltage PMOS power tube are high pressure resistant device.
Optional, said first electric capacity of voltage regulation, said second building-out capacitor, said second electric capacity of voltage regulation, said first resistance, said second resistance and said low pressure NMOS pipe are low-voltage device.
Optional; The dominant pole of modeling plan power circuit is arranged on the output terminal of said operational amplifier in said; The inferior limit of modeling plan power circuit is arranged on the internal simulation power output end that power circuit is intended in said interior modeling in said, and said internal simulation power output end links to each other with the drain electrode of said high voltage PMOS power tube.
According to specific embodiment provided by the invention, the invention discloses following technique effect:
Among the present invention, dominant pole is arranged on the amplifier output terminal, and the internal simulation power output end is a time dominant pole, and therefore the capacitance of first electric capacity of voltage regulation is less, can be produced by inside, has avoided being provided and the elevator system cost by chip exterior;
Therefore in addition, internal simulation supply voltage of the present invention does not change with outer power voltage, is applicable to the situation that the outer power voltage variation range is bigger, when particularly externally supply voltage value is low, and still can operate as normal;
The present invention's first building-out capacitor upper and lower side is connected in the grid of outer power voltage and high voltage PMOS power tube respectively; When externally the high frequency burr appears in supply voltage; The grid of high voltage PMOS power tube can change with the variation of outer power voltage, so the internal simulation supply voltage is better to the high frequency electric source voltage rejection ratio of outer power voltage;
When the present invention had successfully solved outer power voltage and starts fast, the overshoot of internal simulation supply voltage punctured the problem of low-voltage device, under toggle speed arbitrarily, the phenomenon that overshoot punctures can not take place.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do simple the introduction to the accompanying drawing of required use among the embodiment below; Conspicuous, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is that circuit construction of electric power figure is intended in interior modeling of the prior art;
Fig. 2 is that circuit construction of electric power figure is intended in interior modeling of the present invention;
Fig. 3 is during for outer power voltage VDDA fast powering-up of the present invention, the oscillogram of internal power source voltage VCC.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, complete description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the present invention done further detailed explanation.
Fig. 2 is that circuit construction of electric power figure is intended in interior modeling of the present invention.As shown in Figure 2, modeling is intended power circuit and is comprised in this: band gap reference Bandgap, operational amplifier OPA, the first building-out capacitor C3, the second building-out capacitor C2, the first electric capacity of voltage regulation C1, the second electric capacity of voltage regulation C4, high voltage PMOS power tube P1, low pressure NMOS pipe N1, first resistance R 1, second resistance R 2 and outer power voltage VDDA;
The reference voltage output end Vref of said band gap reference Bandgap links to each other with the negative input end of said operational amplifier OPA; The reference voltage output end Vref of said band gap reference Bandgap is through the said second electric capacity of voltage regulation C4 ground connection;
The top crown of the output terminal of said operational amplifier OPA, the said first building-out capacitor C3 links to each other with the grid of said high voltage PMOS power tube P1; The drain electrode of one end of the drain electrode of said high voltage PMOS power tube P1, said second resistance R 2, the bottom crown of the said second building-out capacitor C2, said low pressure NMOS pipe N1 links to each other with the top crown of the said first electric capacity of voltage regulation C1, and this node also is the output node of internal simulation power supply VCC; The grid of one end of the other end of said second resistance R 2, said first resistance R 1, the top crown of the said second building-out capacitor C2, said low pressure NMOS pipe N1 links to each other with the positive input terminal of said operational amplifier OPA; Said outer power voltage VDDA links to each other with the bottom crown of the power end of the power end of said band gap reference Bandgap, said operational amplifier OPA, the said first building-out capacitor C3, source electrode and the substrate of said high voltage PMOS power tube P1; The bottom crown of the source electrode of the ground end of said band gap reference Bandgap, the ground end of said operational amplifier OPA, the other end of said first resistance R 1, said low pressure NMOS pipe N1 and substrate, the said first electric capacity of voltage regulation C1 links to each other with ground voltage.
In the practical application, band gap reference Bandgap, operational amplifier OPA can adopt high pressure resistant device.The first building-out capacitor C3 and high voltage PMOS power tube P1 can adopt high pressure resistant device.The first electric capacity of voltage regulation C1, the second building-out capacitor C2, the second electric capacity of voltage regulation C4, first resistance R 1, second resistance R 2, low pressure NMOS pipe N1 can adopt low-voltage device.First resistance R 1, second resistance R 2 are same type resistance.
Principle of work in the face of modeling plan power circuit in of the present invention is elaborated down.
In order to make system stability, the dominant pole of Fig. 2 cyclic system is located at operational amplifier OPA output node place, and inferior dominant pole is located at VCC output node place.C2, C3 are the building-out capacitor of increase system loop phase nargin, and C3 is littler before dominant pole frequency is compensated, and also has VDDA and starts function fast.Make the P1 grid voltage follow the effect of VDDA voltage before OPA does not work as yet, make VCC the phenomenon of overshoot occur starting to avoid the too early conducting of power tube P1; C2 can make VCC and N1 grid set up a quick path when overshoot takes place VCC, makes in overshoot moment that up voltage is approximately equal to up voltage on the VCC on the N1 grid, rushes down the positive charge at VCC place with the electric current that increases through N1, avoids or reduce the generation of overshoot voltage; The quick path of C2, R1, R2 and N1 composition also has the effect of output impedance when reducing high frequency simultaneously, strengthens the driving force of VCC, increases the output stage dot frequency, plays the effect of phase compensation; C1 then exists as the electric capacity of voltage regulation of VCC, alleviates the overshoot phenomenon of VCC when starting simultaneously.
Concrete start-up course is following: before externally power vd DA powers on; The last bottom crown supply voltage of C3 electric capacity is zero; When the VDDA fast powering-up, the mirror current source that bandgap provides does not make before the OPA startup as yet, and the P1 grid voltage can be because the effect of C1 raises along with the quick rising of VDDA voltage; P1 can conducting, so this stage does not have electric current and through the P1 power tube VCC voltage raise.After OPA started, the output current of OPA can fill negative charge to the C3 lower end, so that the P1 grid voltage reduces; The conducting gradually of P1 power tube, V1 voltage raises, simultaneously; In the start-up course of bandgap, because the C4 capacitance is bigger, the Vref that connects the OPA negative input end rises slower; The OPA output terminal can drop to normal working voltage under the reciprocation of positive-negative input end voltage V1, Vref, therefore the amplifier output voltage also can descend slower, reduces the possibility that overshoot takes place VCC.When overshoot took place VCC, because of C2 electric capacity is bigger, the grid of N1 was followed together fast rise of VCC in addition, and the big electric current that flows through N1 can make VCC fall after rise fast, avoids puncturing the possibility of load low-voltage device.
After system's operate as normal; Operational amplifier OPA and output stage are formed low pressure drop (LDO) linear voltage regulator; VCC=Vref* ((R1+R2)/R1) is therefore arranged; And the reference voltage that Vref provides for bandgap voltage reference bandgap, the variation with outer power voltage VDDA does not change, and therefore interior modeling is intended power supply VCC and is not also changed with the variation of outer power voltage; And the bias current of OPA is produced by bandgap reference current mirror image, and the variation with VDDA does not change, so this system is applicable to the situation that the outer power voltage variation range is bigger.
Because power tube of the present invention adopts PMOS (P1); The output voltage of OPA can drop to (VCC-Vth (P1)) (Vth (P1) is the threshold voltage of P1 pipe); P1 still is operated in the saturation region; Compared to the circuit structure of NMOS as power tube, the present invention can be under lower outer power voltage VDDA operate as normal, so its outer power voltage work lower limit can be lower.
Fig. 3 is during for outer power voltage VDDA fast powering-up of the present invention, the oscillogram of internal power source voltage VCC.Can be found out that by Fig. 3 adopt interior modeling of the present invention to intend after the power circuit, when outer power voltage VDDA fast powering-up, internal power source voltage VCC can stablize rising, does not occur " burr " in the waveform of VCC, overshoot phenomenon can not take place in expression.
Used concrete example among this paper principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, part all can change on embodiment and range of application.In sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. power circuit is intended in modeling in one kind; It is characterized in that, comprising: band gap reference, operational amplifier, first building-out capacitor, second building-out capacitor, first electric capacity of voltage regulation, second electric capacity of voltage regulation, high voltage PMOS power tube, low pressure NMOS pipe, first resistance, second resistance and outer power voltage;
The reference voltage output end of said band gap reference links to each other with the negative input end of said operational amplifier; The reference voltage output end of said band gap reference is through the said second electric capacity of voltage regulation ground connection;
The top crown of the output terminal of said operational amplifier, said first building-out capacitor links to each other with the grid of said high voltage PMOS power tube; The drain electrode of one end of the drain electrode of said high voltage PMOS power tube, said second resistance, the bottom crown of said second building-out capacitor, said low pressure NMOS pipe links to each other with the top crown of said first electric capacity of voltage regulation; The grid of one end of the other end of said second resistance, said first resistance, the top crown of said second building-out capacitor, said low pressure NMOS pipe links to each other with the positive input terminal of said operational amplifier; Said outer power voltage links to each other with the bottom crown of the power end of the power end of said band gap reference, said operational amplifier, said first building-out capacitor, the source electrode and the substrate of said high-voltage power pipe; The bottom crown of the source electrode of the ground end of the ground end of said band gap reference, said operational amplifier, the other end of said first resistance, said low pressure NMOS pipe and substrate, said first electric capacity of voltage regulation links to each other with ground voltage.
2. power circuit is intended in modeling in according to claim 1, it is characterized in that, and said band gap reference, said operational amplifier, said first building-out capacitor and said high voltage PMOS power tube are high pressure resistant device.
3. power circuit is intended in modeling in according to claim 1, it is characterized in that, said first electric capacity of voltage regulation, said second building-out capacitor, said second electric capacity of voltage regulation, said first resistance, said second resistance and said low pressure NMOS pipe are low-voltage device.
4. power circuit is intended in modeling in according to claim 1; It is characterized in that; The dominant pole of modeling plan power circuit is arranged on the output terminal of said operational amplifier in said; The inferior limit of modeling plan power circuit is arranged on the internal simulation power output end that power circuit is intended in said interior modeling in said, and said internal simulation power output end links to each other with the drain electrode of said high voltage PMOS power tube.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100638668A CN102609023B (en) | 2012-03-12 | 2012-03-12 | Built-in analog power supply circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100638668A CN102609023B (en) | 2012-03-12 | 2012-03-12 | Built-in analog power supply circuit |
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| CN102609023B CN102609023B (en) | 2013-11-20 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015154566A1 (en) * | 2014-08-15 | 2015-10-15 | 中兴通讯股份有限公司 | Circuit start method, control circuit and voltage reference circuit |
| CN105700610A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN107749710A (en) * | 2017-11-15 | 2018-03-02 | 上海华虹宏力半导体制造有限公司 | A kind of LDO overshoot protections circuit and its implementation |
| CN108227799A (en) * | 2016-12-09 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of regulator circuit |
| CN109002074A (en) * | 2018-09-12 | 2018-12-14 | 杰华特微电子（杭州）有限公司 | Linear voltage-stabilizing circuit, method for stabilizing voltage and the electric power management circuit using it |
| CN110647202A (en) * | 2018-06-27 | 2020-01-03 | 艾普凌科有限公司 | Voltage stabilizer |
| US11095216B2 (en) | 2014-05-30 | 2021-08-17 | Qualcomm Incorporated | On-chip dual-supply multi-mode CMOS regulators |
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| US20050127885A1 (en) * | 2003-12-16 | 2005-06-16 | Quicklogic Corporation | Regulator with variable capacitor for stability compensation |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| US20110193538A1 (en) * | 2010-02-05 | 2011-08-11 | Dialog Semiconductor Gmbh | Domino voltage regulator (dvr) |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11095216B2 (en) | 2014-05-30 | 2021-08-17 | Qualcomm Incorporated | On-chip dual-supply multi-mode CMOS regulators |
| US11726513B2 (en) | 2014-05-30 | 2023-08-15 | Qualcomm Incorporated | On-chip dual-supply multi-mode CMOS regulators |
| WO2015154566A1 (en) * | 2014-08-15 | 2015-10-15 | 中兴通讯股份有限公司 | Circuit start method, control circuit and voltage reference circuit |
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| CN105700610A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN108227799A (en) * | 2016-12-09 | 2018-06-29 | 北京兆易创新科技股份有限公司 | A kind of regulator circuit |
| CN108227799B (en) * | 2016-12-09 | 2024-05-17 | 兆易创新科技集团股份有限公司 | Voltage stabilizing circuit |
| CN107749710A (en) * | 2017-11-15 | 2018-03-02 | 上海华虹宏力半导体制造有限公司 | A kind of LDO overshoot protections circuit and its implementation |
| CN107749710B (en) * | 2017-11-15 | 2020-05-01 | 上海华虹宏力半导体制造有限公司 | LDO overshoot protection circuit and implementation method thereof |
| CN110647202A (en) * | 2018-06-27 | 2020-01-03 | 艾普凌科有限公司 | Voltage stabilizer |
| CN110647202B (en) * | 2018-06-27 | 2022-04-08 | 艾普凌科有限公司 | Voltage stabilizer |
| CN109002074A (en) * | 2018-09-12 | 2018-12-14 | 杰华特微电子（杭州）有限公司 | Linear voltage-stabilizing circuit, method for stabilizing voltage and the electric power management circuit using it |
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| CN102609023B (en) | 2013-11-20 |
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Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |