CN102595776B - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
- Publication number
- CN102595776B CN102595776B CN201210058152.8A CN201210058152A CN102595776B CN 102595776 B CN102595776 B CN 102595776B CN 201210058152 A CN201210058152 A CN 201210058152A CN 102595776 B CN102595776 B CN 102595776B
- Authority
- CN
- China
- Prior art keywords
- power supply
- pad
- main channel
- pcb
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010410 layer Substances 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000002344 surface layer Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
The invention discloses a printed circuit board (PCB), which comprises a surface layer board, a power plane layer board and a grounding layer board, which are stacked, wherein the surface of the power plane layer board is an electroconductive layer and is provided with power connecting holes and isolation bonding pads. A cross main channel is arranged on the electroconductive layer, and the power connecting holes and the isolation bonding pads are arranged in four quadrant areas formed by the main channel. Compared with the prior art, the PCB provided by the invention has the advantages that the line routing width on a power plane and a ground plane is increased, the power supply and backflow capacities of power supply and ground systems in an BGA (Ball Grid Array) area are improved obviously, meanwhile, the routing and fan-out areas of other signal lines are not influenced and occupied, the number of PCB application numbers can be decreased, the number of filter capacitors capable of being placed in a bottom-layer core power supply area right below a chip is increased, and thus, the filter effect of the power supply and the stability of the power supply system are enhanced and heat conduction is facilitated.
Description
Technical field
The present invention relates to a kind of printed circuit board (PCB) (PCB).
Background technology
Along with the miniaturization of electronic product volume and the integrated development trend of function, to adopting the pcb board of ball grid array structure (BGA:Ball Grid Array) packaging technology to propose more and more higher requirement.As, more than the number of plies of pcb board need reach 4-6 layer, and high-layer more, and the distribution of the BGA pad of pcb board also needs very intensive, spacing between adjacent BGA pad is also more and more less, as, 1 millimeter of solder pad space length, 0.8 millimeter of solder pad space length, 0.5 millimeter of solder pad space length etc.In pcb board design process, also need layout via hole, on the inwall of via hole, be coated with one deck Copper Foil, in order to the interconnection between unlike signal layer and plane layer, the same signal of unlike signal layer is connected together.
Meanwhile, along with the upgrading of semiconductor technology, the development trend of chip is low-voltage and high-current.At present, the core voltage of mainstream chip drops to below 1.0V, or even lower.According to chip to the requirement of power-supply fluctuation be normal voltage ± 5% voltage range within, the Virtex-5 of Ru Sai SEL chip, core voltage is 0.9V, admissible fluctuation is only 0.045V.
By formula
This just requires us in the situation that maximum current is constant, reduces as much as possible target impedance, suppresses and falls to reduction loop, and reduces to disturb, and voltage is fluctuateed within the range of permission.
Refer to Fig. 1, it is the floor map of power plane laminate of the pcb board of prior art.The surface of this power plane laminate has a conductive layer 3, is provided with power supply and connects hole 4 and isolation pad 5 on this conductive layer.This power supply connect hole 4 and power supply area on the substrate of top layer to cross hole site corresponding, it is corresponding with via hole and the pad of all the other positions on the substrate of top layer that this isolates pad 5.In existing technology, as, the chip of 1 millimeter of solder pad space length, the spacing between this isolation pad 5 is 1mm, and according to existing PCB manufacturing technology level, the diameter of isolation pad 5 is 0.75mm, and therefore, the trace width between two isolation pads 5 is only 0.25mm.And to 0.8 millimeter of packaging below solder pad space length, the trace width between two isolation pads is less, for for meeting the requirement of current low-voltage and high-current, can solve by increasing the power plane number of plies, but this can increase the manufacturing cost of PCB.
Summary of the invention
The object of the invention is to overcome the shortcoming of prior art with not enough, provide a kind of manufacturing cost lower, thermal diffusivity is good and can realize the printed circuit board (PCB) of low-voltage and high-current requirement.
The present invention is achieved by the following technical solutions: a kind of printed circuit board (PCB), comprise sheet surface layer, power plane laminate, ground connection laminate and the bottom plate of stacked setting, and the surface of this power plane laminate is conductive layer, is provided with power supply and connects hole and isolation pad on it.On this conductive layer, be provided with " cross " main channel, this power supply connects hole and isolation pad is arranged in four quadrant areas of this main channel formation.
Further, the width of this main channel is 1.25mm.
Further, the surface of this ground connection laminate is conductive layer, is also provided with the cross main channel corresponding with this power plane laminar substrate on it.
With respect to prior art, the power plane layer of pcb board provided by the invention has criss-cross main channel, increased the trace width of power plane and ground plane, power supply and the backflow ability of BGA region power supply, grounding system are obviously improved, also do not affect and take cabling and the fan-out area of other holding wire simultaneously, can reduce PCB and use the number of plies, under increase chip, bottom core power supply area can be placed the number of filter capacitor, and then increase power filter suburb really, strengthen the stability of power-supply system, and be beneficial to heat conduction.
Accompanying drawing explanation
Fig. 1 is the floor map of power plane laminate of the pcb board of prior art.
Fig. 2 is the floor map of pcb board sheet surface layer 10 of the present invention.
Fig. 3 is the floor map of the power plane laminate 20 of pcb board of the present invention.
Fig. 4 is the floor map of the ground connection laminate 30 of pcb board of the present invention.
Embodiment
According to resistance formula:
Wherein, ρ is resistivity, and l is conductor length, and A is cross-sectional area,
At resistivity and thickness, constant in the situation that, should increase as much as possible cabling area.
Separately, according to desirable return path play voltage drop formula:
Wherein, V
gbfor ground bullet voltage, L
totalfor return path total inductance, L
bfor local self-induction, L
abfor local mutual inductance,
Can derive, in the time cannot reducing signal along rate of change and increase the PCB return path number of plies, should increase as far as possible trace width.
Pcb board of the present invention comprises sheet surface layer 10, power plane laminate 20, ground connection laminate 30 and the bottom plate of sequentially stacked setting.
Refer to Fig. 2, it is the floor map of pcb board sheet surface layer 10 of the present invention.Pad 11 and via hole 12 matrix arrays are arranged on this sheet surface layer 10, and wherein, every row via hole 12 is arranged between adjacent lines pad 11, and every row via hole 12 is also arranged between adjacent column pad 11.Each pad 11 via hole 12 adjacent thereto connects by connecting line.This pad 11 is in order to be welded and fixed the bga chip (not shown) being arranged on this pcb board.On the inwall of this via hole 12, be coated with one deck Copper Foil, in order to connect the power supply of power plane laminate 20 grades that are arranged on these sheet surface layer 10 lower floors, connect hole.And on this sheet surface layer 10, divide and have power supply area, the pad 11 on power supply area connects the power pin of chip.
Refer to Fig. 3, it is the floor map of the power plane laminate 20 of pcb board of the present invention.The surface of this power plane laminate 20 is provided with conductive layer 21, is specially copper foil layer.On this conductive layer 21, be provided with power supply and connect hole 23 and isolation pad 24.On this conductive layer 21, divide the main channel 25 of one " ten " font, this power supply connects hole 23 and isolation pad 24 is arranged in four quadrant areas of these main channel 25 formation, and connects hole 23 and isolation pad 24 at the interior non-transformer in the main channel 25 of " ten " font.It is corresponding that power supply on this power plane laminate 20 connects via hole 12 positions of the power supply area on 23Yu top layer, hole substrate 10, and this isolation pad 24 is corresponding with via hole and the pad of all the other positions on top layer substrate 10.This main channel 25 can need to be in level and vertical offset according to circuit design.Particularly, the width of this main channel 25 is 1.25mm.The crosspoint of this main channel should be corresponding with the core power supply area of bga chip disposed thereon.
Refer to Fig. 4, it is the floor map of pcb board ground connection laminate 30 of the present invention.The surface of this ground connection laminate 30 is provided with conductive layer 31, is specially copper foil layer.On this conductive layer 31, be provided with earth point 33 and isolating points 34.The same main channel 35 of dividing one " ten " font on this conductive layer 31, this earth point 33 and isolating points 34 are arranged in four quadrant areas of these Zhu Tong 35 roads formation, and at the interior no ground point 33 in the main channel 35 of " ten " font and isolating points 34.Earth point 33 on this ground connection laminate 30 and isolating points 34 require to arrange according to circuit design.This main channel 35 can need to be in level and vertical offset according to circuit design.Particularly, the width of this main channel 35 is 1.25mm.The crosspoint of this main channel should be corresponding with the core power supply area of bga chip disposed thereon.Main channel 35 on this ground connection laminate 30 is corresponding with the position, main channel on power plane laminate 20.
With respect to prior art, power plane layer and the ground plane layer of pcb board provided by the invention have criss-cross main channel, increased the trace width of power plane and ground plane, make BGA region power supply, power supply and the backflow ability of system obviously improve, also do not affect and take cabling and the fan-out area of other holding wire simultaneously, can reduce PCB and use the number of plies, and be beneficial to heat conduction.
The present invention is not limited to above-mentioned execution mode, if various changes of the present invention or distortion are not departed to the spirit and scope of the present invention, within if these changes and distortion belong to claim of the present invention and equivalent technologies scope, the present invention is also intended to comprise these changes and distortion.
Claims (4)
1. a printed circuit board (PCB), comprise power plane laminate, the surface of this power plane laminate is conductive layer, on it, be provided with power supply and connect hole and isolation pad, described power supply connects hole formation power supply and connects bore region, it is characterized in that: on this conductive layer, be provided with " cross " main channel, this power supply connects hole and isolation pad is arranged in four quadrant areas of this main channel formation; The crosspoint of described " cross " main channel is arranged in described power supply and connects in bore region; The width that is somebody's turn to do " cross " main channel is 1.25mm; Above described power plane laminate, be provided with sheet surface layer, on described sheet surface layer, be provided with via hole and pad that matrix is arranged, every row via hole is arranged between adjacent lines pad, every row via hole is also arranged between adjacent column pad, between this pad and via hole, interval arranges, each pad via hole adjacent thereto connects by connecting line, on this sheet surface layer, divide and have power supply area, power supply on this power plane laminate connect hole and power supply area on sheet surface layer to cross hole site corresponding, it is corresponding with via hole and the pad of all the other positions that this isolates pad.
2. printed circuit board (PCB) according to claim 1, is characterized in that: below described power plane laminate, be provided with ground connection laminate, the surface of described ground connection laminate is conductive layer, is also provided with the cross main channel corresponding with this power plane laminate on it.
3. printed circuit board (PCB) according to claim 2, is characterized in that: the cross main channel width of this ground connection laminate is 1.25mm.
4. printed circuit board (PCB) according to claim 2, is characterized in that: below described ground connection laminate, be provided with bottom plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210058152.8A CN102595776B (en) | 2012-03-06 | 2012-03-06 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210058152.8A CN102595776B (en) | 2012-03-06 | 2012-03-06 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102595776A CN102595776A (en) | 2012-07-18 |
| CN102595776B true CN102595776B (en) | 2014-12-10 |
Family
ID=46483824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210058152.8A Expired - Fee Related CN102595776B (en) | 2012-03-06 | 2012-03-06 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102595776B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113079630B (en) * | 2020-05-29 | 2022-12-20 | 新华三技术有限公司合肥分公司 | Circuit board and preparation process thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373139B1 (en) * | 1999-10-06 | 2002-04-16 | Motorola, Inc. | Layout for a ball grid array |
| US7259336B2 (en) * | 2000-06-19 | 2007-08-21 | Nortel Networks Limited | Technique for improving power and ground flooding |
| US6714308B2 (en) * | 2001-09-04 | 2004-03-30 | Zygo Corporation | Rapid in-situ mastering of an aspheric fizeau |
| EP1461985B1 (en) * | 2002-11-20 | 2014-10-22 | Rockstar Consortium US LP | Technique for accommodating electronic components on a multilayer signal routing device |
| US7816247B2 (en) * | 2003-02-25 | 2010-10-19 | Broadcom Corporation | Optimization of routing layers and board space requirements for ball grid array package implementations including array corner considerations |
| CN1971897B (en) * | 2005-11-24 | 2010-05-26 | 鸿富锦精密工业（深圳）有限公司 | Ball grid array wiring structure |
-
2012
- 2012-03-06 CN CN201210058152.8A patent/CN102595776B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN102595776A (en) | 2012-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7326860B2 (en) | Routing vias in a substrate from bypass capacitor pads | |
| US6891258B1 (en) | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit | |
| CN1951161B (en) | Shared via decoupling for area arrays components | |
| CN102106194B (en) | Ceramic package substrate with recessed device | |
| US8379391B2 (en) | Memory module with vertically accessed interposer assemblies | |
| US8154466B2 (en) | Antenna feed module | |
| US10985097B2 (en) | Interposer-based damping resistor | |
| US7847404B1 (en) | Circuit board assembly and packaged integrated circuit device with power and ground channels | |
| US8076588B2 (en) | Multilayer wiring board | |
| US9209240B2 (en) | Metal-oxide-metal capacitor structure | |
| JP7394495B2 (en) | Wiring design methods, wiring structures, and flip chips | |
| TWI677065B (en) | Electronic apparatus and circuit board | |
| KR101947774B1 (en) | Semiconductor device having intermediate contacts, intermediate contacts, and method of manufacturing intermediate contacts | |
| US9313877B2 (en) | Electronic device and noise suppression method | |
| CN100525578C (en) | Method for increasing a routing density for a circuit board and such a circuit board | |
| CN104218016A (en) | IC (integrated circuit) carrier board and semiconductor device with same | |
| CN102595776B (en) | Printed circuit board | |
| US20190348360A1 (en) | Signal routing in integrated circuit packaging | |
| US9565762B1 (en) | Power delivery network in a printed circuit board structure | |
| US20090167334A1 (en) | Controlled Impedance Structures for High Density Interconnections | |
| US20080151513A1 (en) | High-frequency PCB connections that utilize blocking capacitors between the pins | |
| TW202027570A (en) | Control device and circuit board | |
| JP6535788B2 (en) | Semiconductor device | |
| CN203057697U (en) | PCB plate with crossed blind holes | |
| US8354600B2 (en) | Printed wiring board and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGXIN COMMUNICATION SYSTEM CO LTD (GUANGZHOU) Free format text: FORMER OWNER: COMBA TELECOM SYSTEMS (CHINA) CO., LTD. Effective date: 20150821 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150821 Address after: 510663 Guangdong city of Guangzhou province Guangzhou economic and Technological Development Zone Jinbi Road No. 6 Patentee after: Comba Telecom Systems (Guangzhou) Co., Ltd. Address before: 510663 Guangzhou Science City, Guangdong Shenzhou Road, No. 10 Patentee before: Comba Telecom System (China) Co., Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20200116 Address after: 510663 Guangzhou Science City, Guangdong Shenzhou Road, No. 10 Patentee after: Jingxin Communication System (China) Co., Ltd. Address before: 510663, No. 6, Jin Lu, Guangzhou economic and Technological Development Zone, Guangdong, Guangzhou Patentee before: Jingxin Communication System (Guangzhou) Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141210 Termination date: 20210306 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |