CN102595063B - Sense amplifier and the equipment including sense amplifier including negative capacitance circuit - Google Patents
Sense amplifier and the equipment including sense amplifier including negative capacitance circuit Download PDFInfo
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- CN102595063B CN102595063B CN201110399317.3A CN201110399317A CN102595063B CN 102595063 B CN102595063 B CN 102595063B CN 201110399317 A CN201110399317 A CN 201110399317A CN 102595063 B CN102595063 B CN 102595063B
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Abstract
Disclose and a kind of there is the sense amplifier of negative capacitance circuit, imageing sensor, image processing equipment and the method for operation sense amplifier.Sense amplifier receives differential input signal via data wire docking, and use the voltage difference between the difference single-ended amplifier pair differential output signal corresponding with the differential input signal that negative capacitance circuit loads sense and amplify, to produce corresponding data output signal.
Description
This application claims the priority of the korean patent application No.10-2011-0002308 submitted on January 10th, 2011, disclosed and be fully incorporated in this as reference.
Technical field
Present inventive concept relates to semiconductor device, relates more specifically to complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.The specific embodiment of present inventive concept relates to the sense amplifier including negative capacitance circuit.This sense amplifier can be used in cmos image sensor and relevant device, to advantageously promote the speedy carding process that bit error rate (BER) reduces.
Background technology
Multiple data storage elements (such as, 1 bit static RAM (SRAM) element) are generally connected by traditional cmos image sensor with the one or more data channel being connected sense amplifier (sense amplifier).Each passage can include relatively long holding wire, and the data storage elements of selection is connected by holding wire respectively with sense amplifier.The length of the holding wire of the number of the data storage elements connected, the bandwidth of passage and composition passage can affect can transmit the speed to sense amplifier consistently by data consistent.Therefore, increase must solve the restriction etc. in terms of these factors that is mutually related, such as channel width, signal transmission characteristics and acceptable bit error rate (BER) by the trial of the speed of CMOS sense amplifier output data.Relative to cmos image sensor and the allowed size of building block and power consumption characteristics, all of these factors taken together must be weighed.
Summary of the invention
Specific embodiment according to present inventive concept, it is proposed that a kind of sense amplifier, including negative capacitance circuit (negative capacitance circuit), be connected to for the data wire transmitting differential input signal between；Current biasing circuit, provides bias current to negative capacitance circuit；Voltage offset electric circuit, to described data wire to providing bias voltage；And comparator, receive the differential output signal corresponding with the differential input signal that negative capacitance circuit loads, and produce corresponding data output signal.
Specific embodiment according to present inventive concept, it is proposed that a kind of imageing sensor, including: the pixel of picture element signal is provided；Analog digital conversion (ADC) circuit, is converted to differential input signal by described picture element signal；And data wire pair, transmit differential input signal.Voltage difference between differential input signal is sensed and amplifies by sense amplifier, and sense amplifier includes: negative capacitance circuit, be connected to data wire between；Current biasing circuit, provides bias current to negative capacitance circuit；Voltage offset electric circuit, to described data wire to providing bias voltage；And comparator, receive the differential output signal corresponding with the differential input signal that negative capacitance circuit loads, and produce corresponding data output signal.
Specific embodiment according to present inventive concept, it is proposed that a kind of image processing equipment, including: lens；Imageing sensor, is configured to be converted to the optical signalling received via lens corresponding electricity view data；And processor, control the operation of imageing sensor.Imageing sensor includes: provide the pixel of picture element signal；Analog digital conversion (ADC) circuit, is converted to differential input signal by described picture element signal；And sense amplifier, to by data wire, the voltage difference between transmission to the differential input signal of sense amplifier is sensed and amplifies.Sense amplifier includes: negative capacitance circuit, be connected to data wire between；Current biasing circuit, provides bias current to negative capacitance circuit；Voltage offset electric circuit, to described data wire to providing bias voltage；And comparator, receive the differential output signal corresponding with the differential input signal that negative capacitance circuit loads, and produce corresponding data output signal.
Specific embodiment according to present inventive concept, it is proposed that a kind of method operating sense amplifier, described method includes: via data wire to receiving differential input signal in negative capacitance circuit；And use the voltage difference between the difference single-ended amplifier pair differential output signal corresponding with the differential input signal that negative capacitance circuit loads to be amplified, to produce corresponding data output signal.
Accompanying drawing explanation
When considering specific embodiment with reference to accompanying drawing, the above and other feature and advantage in present inventive concept will be more clearly understood from and are easier to understand, wherein:
Fig. 1 is the circuit diagram of the sense amplifier according to present inventive concept embodiment；
Fig. 2 is the circuit diagram of the Capacitor banks further illustrating the Fig. 1 according to present inventive concept embodiment；
Fig. 3 is the circuit diagram of the current source further illustrating the Fig. 1 according to present inventive concept embodiment；
Fig. 4 is combined with the block diagram of the imageing sensor of sense amplifier shown in Fig. 1；
Fig. 5 is the circuit diagram replicating sense amplifier further illustrating Fig. 4；
Fig. 6 is oscillogram set, show the relation between input signal and the output signal occurred in the sense amplifier of Fig. 1, and the relation between the comparative input/output signal of the sense amplifier of the negative capacitance circuit in not including present inventive concept embodiment；
Fig. 7 is combined with the block diagram of the image processing equipment of imageing sensor shown in Fig. 4；And
Fig. 8 is the flow chart of a kind of possible operation method of the sense amplifier summarizing Fig. 1.
Detailed description of the invention
It is described in greater detail with reference to the attached drawings the specific embodiment of present inventive concept.But, present inventive concept can implement in many different forms, and should not be limited only to embodiment set forth herein.On the contrary, it is provided that illustrated embodiment is so that the present invention is open the most in further detail and completely.Run through specification and drawings, similar figure numbers and labelling for indicating similar element.
Should be understood that when mention element " connect " or " coupling " to another element time, this element can be directly connected to or coupled to another element described, or can there is intermediary element.On the contrary, when mention element " be directly connected to " or " direct-coupling " to another element time, there is not intermediary element.As used herein, term "and/or" includes one or more arbitrarily and all the combining of associated listed entry, and can be abbreviated as "/".
Although should be understood that term first, second used herein etc. describes Various Components, but these elements should not be limited by these terms.These terms are served only for making a distinction an element with another element.Such as, in the case of without departing from the open teaching of the present invention, the first signal can be referred to as secondary signal, and secondary signal can be referred to as the first signal similarly.
Terms used herein is the purpose in order to describe specific embodiment, and is not intended to limit present inventive concept.As it is used herein, unless explicitly pointed out in literary composition, otherwise " ", " a kind of " and " being somebody's turn to do " of singulative also aims to include plural form.Will also be understood that, used herein such as " include " or the term of " comprising " etc represents feature, region, integer, step, operation, element and/or the assembly that existence is stated, but be not precluded from existing or adding other features one or more, region, integer, step, operation, element, assembly and/or a combination thereof.
Unless explicitly defined otherwise, all terms the most used herein (including technical term and scientific terminology) have the identical meanings that those skilled in the art are generally understood that.Should also be understood that term (e.g., the term defined in common dictionary) should be interpreted that implication is consistent with the implication in association area context, and should not idealize or excessively explain these terms formally, unless the most so limited.
Fig. 1 is the circuit diagram of the sense amplifier 10 according to present inventive concept embodiment.In order to describe purpose, it is assumed that SRAM element 50-1 is operably associated with sense amplifier 10.But, it will be appreciated by those skilled in the art that other input data sources (such as, depositor, latch or memory component) can alternatively be associated with sense amplifier 10.
With reference to Fig. 1, sense amplifier 10 includes that the data wire for differential signal transmission is to 11-1 and 11-2.That is, by data wire, 11-1 and 11-2 is received Differential Input data signal from SRAM 50-1, and corresponding difference output data signal is applied to output comparator 19.Negative capacitance circuit 13 be connected to data wire to 11-1 and 11-2 between.Current biasing circuit 15 provides bias current to negative capacitance circuit 13, and voltage offset electric circuit 17 provides bias voltage to data wire 11-1 and 11-2.After 11-1 and 11-2 is loaded by negative capacitance circuit 13 by data wire, difference between differential output signal present on 11-1 and 11-2 is amplified by comparator 19 by data wire.In this, term " loads " and should be broadly construed as: compared with corresponding differential output signal, negative capacitance circuit 13 change in the electric current caused for differential input signal and/or any change of voltage level and sequential.
It will be appreciated by those of ordinary skill in the art that the data wire in embodiment illustrated in fig. 1 is used as 1 bit data bus (or holding wire) to 11-1 and 11-2, the single bit data that SRAM 50-1 provides is transferred to sense amplifier 10.
The loading effect (such as total capacitance) that (or setting) is provided can be controlled by negative capacitance circuit 13 according to specific outside " control routine " provided.Each control routine can include the control data of individual bit or multiple bit.It should be understood by one skilled in the art that is can to realize negative capacitance circuit 13 in a variety of forms according to the master-plan of sense amplifier 10 and running parameter.It is, for example possible to use negative impedance circuit or negative conductance circuit.In the particular example shown in Fig. 1, negative capacitance circuit 13 includes Capacitor banks (capacitor bank) 13-1 and a pair (first and second) cross-coupled transistor 13-2 and 13-3.
Fig. 2 shows the partial circuit diagram of a kind of possible relevant portion realizing example of Fig. 1 Capacitor banks 13-1 according to present inventive concept embodiment.Include multiple capacitor C1 to Cm with reference to Fig. 2, Capacitor banks 13-1, by corresponding capacitor switch group SW11 to SW1m and SW11 ' to SW1m ' (wherein m is natural number), multiple capacitors are optionally switched in and out the parallel connected array of capacitor.
Such as, when the first on-off control bit CT11 in response to the first control routine CTS1 applied connects the first group capacitor switch SW11 and SW11 ', by the first capacitor C1 incision Capacitor banks 13-1 (be conceptually illustrated in and occur between two conductive node B and C).When the m-th on-off control bit CT1m in response to the first control routine CTS1 connects m group (last group) capacitor switch SW1m and SW1m ', m-th capacitor Cm is cut in Capacitor banks 13-1.Therefore, it can optionally control total (accumulation) electric capacity of (or setting) Capacitor banks 13-1 according to the first control routine CTS1.
Such as, in the case of using N-type metal-oxide semiconductor (MOS) (NMOS) transistor to realize each group capacitor switch SW11 to SW1m and SW11 ' to SW1m ', each capacitor switch SW11 to SW1m and SW11 ' can be connected to SW1m ' by having the respective switch control bit of the first level (such as logic " high " or data value " 1 ").
Returning to Fig. 1, node B (i.e. the side of Capacitor banks 13-1) is connected by the first interconnection transistor 13-2 with the first data wire 11-1 of data wire pair.The grid of the first interconnection transistor 13-2 and node C (i.e. Capacitor banks 13-1 another or opposite side) are connected.On the contrary, node C (i.e. the opposite side of Capacitor banks 13-1) is connected by the second interconnection transistor 13-3 with the second data wire 11-2 of data wire pair, and the grid of the second interconnection transistor 13-3 is connected with node B (the above-mentioned side of Capacitor banks 13-1).
Those of ordinary skill in the art are it will also be appreciated that may be implemented in a variety of ways current biasing circuit 15.In the certain illustrated embodiment of Fig. 1, current biasing circuit 15 includes that current source 15-1, current source 15-1 provide reference current to current mirror 15-3, and current mirror 15-3 carries out, by the reference current providing current source 15-1, the bias current that mirror image provides required.
Fig. 3 shows the partial circuit diagram of a kind of possible relevant portion realizing example of the current source 15-1 of the Fig. 1 according to present inventive concept embodiment.Can include multiple current transistor N1 to Nn and corresponding multiple current switch SW21 to Sw2n with reference to Fig. 3, current source 15-1, wherein " n " is natural number.The level of the final reference current produced provided by current source 15-1 can control according to the second control routine CTS2 that outside provides (or setting).
Such as, when the bit CT21 to CT2n in response to the second control routine CTS2 is optionally respectively turned on current switch SW21 to SW2n, current transistor N1 to Nn can be cut into respectively between current source (such as Vdd) and control node A in the current transistor group obtained.
The gained level (or amount) of the reference current of the current transistor N1 to Nn flowing through " incision " by optionally distinguishing the channel width-length ratio of each current transistor N1 to Nn, can be regulated.Therefore, it can control, according to the second control routine CTS2, the reference current that (or setting) is produced by current source 15-1.
Such as, can measure and/or definition sense amplifier 10 digital independent performance test process during, test and/or definition include the semiconductor equipment of sense amplifier 10 (such as, imageing sensor shown in Fig. 4 or the image processing equipment shown in Fig. 6) digital independent performance test process during, the first control routine CTS1 and the second control routine CTS2 are set.
Turning again to Fig. 1, voltage offset electric circuit 17 includes the first resistor R1 being connected between supply voltage Vdd and the first data wire 11-1 and the second resistor R2 being connected between supply voltage Vdd and the second data wire 11-2.The resistance value of the first resistor R1 can be identical or different with the resistance value of the second resistor R2.
It is, for example possible to use difference single-ended amplifier (differential-to-single-ended amplifier) realizes comparator 19.Therefore, the voltage difference between the differential output signal that negative capacitance circuit 13 is loaded can be amplified by comparator 19, to export Single-end output signal (Dout).
Fig. 4 is the block diagram of the imageing sensor 30 of the sense amplifier 10 including Fig. 1.With reference to Fig. 4, imageing sensor 30 uses cmos image sensor, cmos image sensor to include: active pixel sensor array 40, row decoder 42, correlated-double-sampling (CDS) module 44, comparator module 46, ramp generator 47, column counter module 48, counter controller 49, memory module 50, Memory Controller 51, column decoder 60, sense amplifier 10, duplication (replica) sense amplifier 65 and time schedule controller 70.
CDS module 44, comparator module 46, column counter module 48 and memory module 50 can serve as analog digital conversion (ADC) circuit.
Active pixel sensor array 40 includes multiple pixel P.Each pixel P can be realized by light-sensitive element, and light-sensitive element produces picture element signal according to incident optical signal.For example, it is possible to define picture element signal according to reset signal and imager signal.
Row decoder 42 may be used for producing multiple control signal, and described control signal optionally activates the photo sensing operation of each pixel P under the control of time schedule controller 70.In certain embodiments, row decoder 42 may be used for driving line by line pixel.
CDS module 44 includes the layout in column of CDS circuit 44-1.Each CDS circuit 44-1 is connected with corresponding row respectively, and the picture element signal provided in row performs CDS operation, to export CDS picture element signal.
Comparator module 46 includes multiple comparator 46-1.The ramp signal exported from ramp generator 47 is compared by each comparator 46-1 with the CDS picture element signal from CDS circuit 44-1, to export comparison signal.
Column counter module 48 includes multiple column counter 48-1.Each column counter 48-1, under the control of counter controller 49, is determined (or " counting ") in response to the corresponding persistent period between the clock signal conversion to comparison signal, to export count value.
Memory module 50 is included in the multiple memorizer 50-1 controlling lower operation of Memory Controller 51 and/or timing sequencer 70.Each memorizer 50-1 stores the count value provided by column counter 48-1 under the control of Memory Controller 51.In a particular embodiment, it is possible to use the SRAM used in embodiment as shown in Figure 1 realizes each memorizer 50-1.
Column decoder 60 produces selection signal, described selection signal behavior each memorizer 50-1 under the control of time schedule controller 70.Such as, when column decoder 60 output is activated the selection signal selecting first memory 50-1, the data of storage in first memory 50-1 are transmitted to sense amplifier 10 to 11 via data wire.Column decoder 60 thus can sequentially activate each select signal so that by each memorizer 50-1 storage data sequentially export to corresponding data wire 11.
Then the difference between the sense amplifier 10 the including negative capacitance circuit 13 gained differential output signal to being received by data wire 11-1 and 11-2 can be used to sense and amplify, and export data Dout of amplification.Because the sense amplifier 10 according to present inventive concept embodiment is connected to data wire between 11, so also providing for replicating sense amplifier 65, impedance using the passage (that is, as the differential signal line of ingredient) that coupling is connected with sense amplifier 10.
Fig. 5 is the one circuit diagram in the cards replicating sense amplifier 65 of Fig. 4.Different from the sense amplifier 10 shown in Fig. 1, replicate sense amplifier 65 and do not include comparator.
With reference to Fig. 1 and Fig. 5, replicate sense amplifier 65 can include having similarly configure with negative capacitance circuit 13 the second negative capacitance circuit 13 ', there is the second current biasing circuit 15 ' similarly configured with current biasing circuit 15 and there is the voltage offset electric circuit 17 ' similarly configured with voltage offset electric circuit 17.
The total capacitance that can control the Capacitor banks 13-1 in (or setting) sense amplifier 10 by time schedule controller 70 according to the first control routine CTS1 such as provided and the total capacitance of the Capacitor banks 13-1 ' replicated in sense amplifier 65.The reference current that (or setting) is produced by the current source 15-1 in sense amplifier 10 and the reference current produced by the current source 15-1 ' replicated in sense amplifier 65 can be controlled by time schedule controller 70 according to the second control routine CTS2 such as provided.
As understood routinely, time schedule controller 70 is provided for control signal, controls sense amplifier 10, row decoder 42, ramp generator 47, counter controller 49, Memory Controller 51 and replicates the operation of each (and interactive operation) of sense amplifier 65.
Fig. 6 is oscillogram set, show the relation (situation I) between input signal and the output signal occurred in Fig. 1 sense amplifier 10, and at the similarity relation (situation II) not included between the input and output signal of sense amplifier of negative capacitance circuit.Jointly with reference to Fig. 1,4 and 6, when 11-1 and 11-2 transmission being inputted data according to the input data rate of (such as) 100Mbps via data wire, according to present inventive concept embodiment include the example sense amplifier of negative capacitance circuit 13 by produce not there is error export data accordingly, as shown in situation I.
But, do not include that the conventional sense amplifier of negative capacitance circuit 13 may not correctly sense and amplifies input traffic, this input traffic includes the data value " 1 " being followed by the value " 0 " that multiple continuous print number is followed by multiple continuous print numerical value " 0 ", or this input traffic includes the data value " 0 " that is followed by multiple continuous data value " 1 ".The possible error result of input data rate for only 80Mbps is shown in situation II of Fig. 6.
Therefore, even data wire 11-1 and 11-2 composition to bandwidth limit frame rate time, for the passage of given number, also increase including the sense amplifier 10 of negative capacitance circuit 13 and can obtain the maximum rate reading data.In other words, the conventional sense amplifier limited compared to the relevant transmission with similar passage and data storage elements, can operate with higher frequency according to the sense amplifier 10 of present inventive concept embodiment.
Fig. 7 is the block diagram of the image processing equipment 100 of the imageing sensor 30 including Fig. 4.With reference to Fig. 7, image processing equipment 100 includes: imageing sensor 30, optical lens 32, processor 110 and display 120.Image processing equipment 100 can be digital camera or the data handling equipment including digital camera, such as personal computer (PC), cell phone, smart phone, flat board PC or information technology (IT) equipment.Digital camera can be single anti-(DSLR) camera of numeral.
The optical image signal of the object 31 received by optical lens 32 is converted to electricity view data by imageing sensor 30.Processor 110 controls the operation of imageing sensor 30, processes the view data from imageing sensor 30 output, and the view data of process is transferred to display 120, with the view data handled by display.View data can be produced according to the outputting data signals (Dout) provided from the sense amplifier similar with above-mentioned sense amplifier.
Fig. 8 is the flow chart of a kind of possible operation method of the sense amplifier summarizing Fig. 1.With reference to Fig. 1 and Fig. 8, sense amplifier 10 receives Differential Input data signal (S10) via the data wire being connected with negative capacitance circuit 13 to 11-1 and 11-2.It is connected to data wire the corresponding differential output signal provided as negative capacitance circuit 13 loading result is amplified by the comparator 19 (such as difference single-ended amplifier) between 11-1 and 11-2, and exports data output signal (Dout) (S20).Voltage offset electric circuit 17 provides bias voltage to data wire to 11-1 and 11-2, and current biasing circuit 15 provides bias current to negative capacitance circuit 13.
As it has been described above, according to the specific embodiment of present inventive concept, the sense amplifier including negative capacitance circuit can correctly sense with of a relatively high speed and amplify input data.It is thus possible to increase the reading data that the equipment being combined with this sense amplifier is obtained.
Although illustrate and describe the design of the present invention by reference to exemplary embodiments, it should be understood by one skilled in the art that is in the case of the scope without departing from the present inventive concept being defined by the following claims, can be to carry out the various changes in form and details.
Claims (24)
1. a sense amplifier, including:
Negative capacitance circuit, be connected to for the data wire transmitting differential input signal between；
Current biasing circuit, provides bias current to negative capacitance circuit；
Voltage offset electric circuit, to described data wire to providing bias voltage；And
Comparator, receives the difference corresponding with the differential input signal that negative capacitance circuit loads defeated
Go out signal, and produce data output by amplifying the voltage difference between described differential output signal
Signal.
Sense amplifier the most according to claim 1, wherein said comparator is difference
Single-ended amplifier.
Sense amplifier the most according to claim 1, is wherein carried by outside at least one
The control routine of confession determines in the electric capacity of negative capacitance circuit and the level of bias current at least
One.
Sense amplifier the most according to claim 3, wherein said negative capacitance circuit bag
Include:
Capacitor banks, including multiple capacitors, in response at least one outside control provided described
Described Capacitor banks is optionally cut/cut out to the plurality of capacitor by one of code processed；With
And
Cross-coupled transistor pair, be connected to Capacitor banks and data wire between.
Sense amplifier the most according to claim 3, wherein said current biasing circuit
Including:
Current source, produces what one of control routine according at least one outside offer described determined
Reference current；And
Current mirror, provides bias current by reference current is carried out mirror image.
Sense amplifier the most according to claim 3, wherein said outside at least one
The control routine provided includes the first control routine and the second control routine,
Described negative capacitance circuit includes: Capacitor banks, including multiple capacitors, in response to first
Described Capacitor banks is optionally cut/cut out to the plurality of capacitor by control routine；And
Cross-coupled transistor pair, be connected to Capacitor banks and data wire between；And
Described current biasing circuit includes: current source, and generation determines according to the second control routine
Reference current；And current mirror, provide bias current by reference current is carried out mirror image.
7. an imageing sensor, including:
The pixel of picture element signal is provided；
Analog digital conversion adc circuit, is converted to differential input signal by picture element signal；And
Data wire pair, transmits differential input signal；
Sense amplifier, senses the voltage difference between differential input signal and amplifies, its
Described in sense amplifier include:
Negative capacitance circuit, be connected to data wire between；
Current biasing circuit, provides bias current to negative capacitance circuit；
Voltage offset electric circuit, to described data wire to providing bias voltage；And
Comparator, receives the difference corresponding with the differential input signal that negative capacitance circuit loads
Divide output signal, and produce by amplifying the voltage difference between described differential output signal
Data output signal.
Imageing sensor the most according to claim 7, also includes:
Time schedule controller, it is provided that the first control routine and the second control routine, described first controls
Code arranges the electric capacity of negative capacitance circuit, and described second control routine arranges the electricity of bias current
Flat.
Imageing sensor the most according to claim 7, also includes:
Replicate sense amplifier, be connected to data wire between, to being connected to described data wire pair
Between the impedance of sense amplifier mate.
Imageing sensor the most according to claim 9, wherein said duplication reads amplifies
Device includes:
There is the negative capacitance circuit similarly configured with the negative capacitance circuit in sense amplifier；
There is the current biasing circuit similarly configured with the current biasing circuit in sense amplifier；
And
There is the voltage offset electric circuit similarly configured with the voltage offset electric circuit in sense amplifier.
11. imageing sensors according to claim 10, wherein said duplication reads and puts
Big device the end of described data wire pair be connected to described data wire between, and described reading
Go out amplifier to connect at the other end contrary with replicating sense amplifier of described data wire pair
Described data wire between.
12. imageing sensors according to claim 10, also include:
Time schedule controller, it is provided that the first control routine and the second control routine, described first controls
Code arranges the electric capacity of negative capacitance circuit, and described second control routine arranges the electricity of bias current
Flat.
13. imageing sensors according to claim 8, wherein said negative capacitance circuit bag
Include: Capacitor banks, including multiple capacitors, in response to the first control routine by the plurality of electricity
Described Capacitor banks is optionally cut/cut out to container；And cross-coupled transistor pair,
Be connected to Capacitor banks and data wire between.
14. imageing sensors according to claim 8, wherein said current biasing circuit
Including: current source, produce the reference current determined according to the second control routine；And current mirror,
Bias current is provided by reference current is carried out mirror image.
15. 1 kinds of image processing equipments, including:
Lens；
Imageing sensor, is configured to be converted to the optical signalling received via lens accordingly
Electricity view data；And
Processor, controls the operation of imageing sensor,
Wherein said imageing sensor includes:
The pixel of picture element signal is provided；
Analog digital conversion adc circuit, is converted to differential input signal by picture element signal；With
And
Sense amplifier, to by data wire to transmission to the Differential Input of sense amplifier
Voltage difference between signal senses and amplifies；
Wherein said sense amplifier includes:
Negative capacitance circuit, be connected to data wire between；
Current biasing circuit, provides bias current to negative capacitance circuit；
Voltage offset electric circuit, to described data wire to providing bias voltage；And
Comparator, receives the difference corresponding with the differential input signal that negative capacitance circuit loads
Divide output signal, and produce by amplifying the voltage difference between described differential output signal
Data output signal.
16. image processing equipments according to claim 15, wherein said reading is amplified
Device also includes that time schedule controller, described time schedule controller provide the first control routine and second to control
Code, described first control routine arranges the electric capacity of negative capacitance circuit, described second control routine
The level of bias current is set.
17. image processing equipments according to claim 16, wherein said reading is amplified
Device also includes: be connected to data wire between duplication sense amplifier, to being connected to described number
According to line between the impedance of sense amplifier mate.
18. image processing equipments according to claim 17, wherein said duplication reads
Amplifier the end of described data wire pair be connected to described data wire between, and described
Sense amplifier connects at the other end contrary with replicating sense amplifier of described data wire pair
Be connected on described data wire between.
19. image processing equipments according to claim 15, wherein said image procossing
Equipment is the single anti-DSLR camera of numeral.
20. 1 kinds of methods operating sense amplifier, described method includes:
Via data wire to receiving differential input signal in negative capacitance circuit；And
Use difference single-ended amplifier pair relative with the differential input signal that negative capacitance circuit loads
Voltage difference between the differential output signal answered is amplified, to produce corresponding data output letter
Number.
21. methods according to claim 20, also include:
Use voltage offset electric circuit to described data wire to providing bias voltage；And
Current biasing circuit is used to provide bias current to described negative capacitance circuit.
22. methods according to claim 21, also include:
The first control routine according to being supplied to described sense amplifier defines described negative capacitance
The electric capacity of circuit.
23. methods according to claim 22, also include:
The second control routine according to being supplied to described sense amplifier defines described biased electrical
The level of stream.
24. methods according to claim 20, wherein by digital ratio during predetermined amount of time
In special static RAM SRAM, the single data bit of storage defines described difference
Divide input signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2011-0002308 | 2011-01-10 | ||
| KR1020110002308A KR101798992B1 (en) | 2011-01-10 | 2011-01-10 | Sense amplifier with negative capacitance circuit and apparatuses including the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102595063A CN102595063A (en) | 2012-07-18 |
| CN102595063B true CN102595063B (en) | 2016-12-14 |
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|---|---|---|---|---|
| US6437612B1 (en) * | 2001-11-28 | 2002-08-20 | Institute Of Microelectronics | Inductor-less RF/IF CMOS buffer for 50Ω off-chip load driving |
| CN1564751A (en) * | 2002-01-28 | 2005-01-12 | 夏普株式会社 | Capacitive load driving circuit, capacitive load driving method, and apparatus using the same |
| CN1795509A (en) * | 2003-03-26 | 2006-06-28 | 薄膜电子有限公司 | Sense amplifier systems and a matrix-addressable memory device provided therewith |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6437612B1 (en) * | 2001-11-28 | 2002-08-20 | Institute Of Microelectronics | Inductor-less RF/IF CMOS buffer for 50Ω off-chip load driving |
| CN1564751A (en) * | 2002-01-28 | 2005-01-12 | 夏普株式会社 | Capacitive load driving circuit, capacitive load driving method, and apparatus using the same |
| CN1795509A (en) * | 2003-03-26 | 2006-06-28 | 薄膜电子有限公司 | Sense amplifier systems and a matrix-addressable memory device provided therewith |
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