CN102594127B - Repetition frequency compact pulse multiplier based on Fitch circuit - Google Patents
Repetition frequency compact pulse multiplier based on Fitch circuit Download PDFInfo
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- CN102594127B CN102594127B CN201210053777.5A CN201210053777A CN102594127B CN 102594127 B CN102594127 B CN 102594127B CN 201210053777 A CN201210053777 A CN 201210053777A CN 102594127 B CN102594127 B CN 102594127B
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- multiplier
- circuit
- electric capacity
- pulse
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Abstract
The invention discloses a repetition frequency compact pulse multiplier based on a Fitch circuit. The positive electrode of input voltage needing to be multiplied is connected to one end of the multiplier by a satiable inductor or a magnetic switch, and the negative electrode of the input voltage is directly connected with the other end of the multiplier; the multiplier comprises N capacitors connected in parallel, and a series circuit of a coupling inductor and a high-frequency silicon stack is connected between the two ends of the nth capacitor and the n+1th capacitor connected with the negative electrode of the input voltage; another coupling inductor is connected between the two ends of the n+1th capacitor and the n+2th capacitor connected with the positive electrode of the input voltage; n is equal to 1, 3, 5 ...; due to the arrangement of a plurality of dotted terminals of the coupling inductor, the condition that the sum of the flowing inductive current when the capacitors are charged counteracts to be zero can be ensured; a plurality of the dotted terminals of another coupling inductor are consistent in direction; and the two ends of the nth capacitor are connected with the satiable inductor in parallel. In the invention, the charging time is the pulse multiplier is short, and the voltage-second product of the satiable inductor is small; no electrode erosion and insulation recovery exist in the magnetic switch, so that the circuit can be operated under high repetition frequency.
Description
Technical field:
The invention belongs to pulse power field, be specifically related to a kind of pulse voltage-multiplying circuit of repetition rate.
Background technology:
The repetitive frequency pulsed voltage-multiplying circuit that present stage extensively adopts is a kind of magnetic compression circuit of exempting from reset, and its circuit structure as shown in Figure 1
[1-2].Low pressure charging capacitor C
1with thyristor THY
1(or IGBT
[3]), air core inductor L
1(or magnetic switch
[4]) and pulse transformer PT
1armature winding connect and form closed-loop path.High-voltage charging capacitor C
2and C
3with magnetic switch MS1 and air core inductor L
2(or semiconductor opening switch
[5], upper end anode, lower end negative electrode) connect and form closed-loop path.Pulse transformer secondary winding and high-voltage charging capacitor C
3parallel connection, and form closed-loop path.Load and air core inductor L
2parallel connection also forms closed-loop path.
Nitrogen oxide removal need to be exported pulse amplitude and is greater than 40kV, is therefore necessary that an input voltage is doubly pressed onto tens of kilovolts and carries out rising edge compression.The pulse transformer in magnetic switch circuit of exempting to reset has completed the target of voltage multiplication.But pulse transformer need to be the voltage multiplication to tens of several hectovolts kilovolt, therefore its no-load voltage ratio is very large.This can bring two problems: 1, the large armature winding that requires of no-load voltage ratio can not be a lot, is difficult to realize otherwise secondary winding is too many.So, for ensure pulse transformer at input pulse to unsaturated before peaking, its magnetic core sectional area must be very large, this causes pulse transformer volume very large, is unfavorable for the miniaturization of clock.2, document [5] is recorded, output voltage amplitude is in 10kV or following pulse transformer air insulation, and amplitude needs oilpaper mix insulation at 10kV to the pulse transformer between 50kV, this will greatly increase pulse transformer weight, be unfavorable for its miniaturization and portability.
Document 6 has proposed a kind of pulse voltage multiple circuit.Wherein, N capacitances in series, and alternate electric capacity two ends air core inductor in parallel, air core inductor is connected by ball gap with electric capacity.Electric capacity at different levels connects by resistance, and the effect of resistance is to provide loop for capacitor charging.After electric capacity has charged by resistance, the synchronous conducting of ball gaps at different levels, alternate electric capacity and air core inductor voltage carry out resonance.In the time that polarity of voltage reverses completely, output obtains N input voltage doubly.
But the circuit that document 6 proposes has following shortcoming: 1, electric capacity charges by resistance, the charging interval is very long, cannot accomplish to rerun.2, adopt ball gap as switch, its insulator recovery time and electrode erosion have also limited the frequency that reruns of whole system.
[1] Zhang Dongdong, Yan Ping, Wang Yu, etc. single-stage magnetic pulse compression system experimental study [J], light laser and the particle beams, 2008:20 (8), 1397-1410.
[2] Zhang Dongdong, Yan Ping, Wang Yu, etc. single-stage magnetic pulse compression system is analyzed [J], high voltage technique, 2009,35 (3): 661-666.
[3]Scott?J.Pendleton，Daniel?Singleton，Andras?Kuthi，et?al.Compact?solid?state?high?repetition?rate?variable?amplitude?pulse?generator[J].2009.PPC′09.IEEE.2009：922-925.
[4]A.Pokryvailo，Y.Yankelevich，M.Wolf，et?al.A?1KW?pulsed?corona?system?for?pollution?control?applications[J].2003.PPC′03.IEEE.2003：225-228.
[5]F.Zagulov，V.Kladukhin，D.Kuznetsov，et?al.A?high-current?nanosecond?electron?accelerator?with?a?semiconductor?opening?switch[J].Instruments?and?Experimetal?Techniques.2000，43(5)：647-651
[6]Richard?Anthony?Fitch，Mortimer.“Electrical?Pulse?Generator”，US?Patent?nr3,366,799,30.
Summary of the invention:
Therefore, the object of the invention is to propose a kind of compact pulse voltage multiplie of repetition rate.After this voltage doubler stage is associated in pulse transformer, the output pulse of pulse transformer is carried out to secondary multiplication of voltage, thereby reduce no-load voltage ratio and the output voltage amplitude of pulse transformer, its volume and weight are greatly reduced.
Specific as follows:
The pulse multiplier operation principle that the present invention proposes is that electric capacity is carried out to charged in parallel, when charging, makes adjacent capacitor charging voltage size identical, opposite direction.After to be charged completing, alternate charging capacitor (the 1st, 3,5... or the 2nd, 4,6... is filled an electric capacity) and saturated after magnetic switch carry out oscillating discharge, in the time that its voltage is turned to negative sense, output produces a pulse after multiplication of voltage.
The structure that this patent proposes the compact pulse multiplier of repetition rate based on Fitch circuit is as follows:
A kind of repetitive frequency pulsed multiplier based on Fitch circuit, need the input voltage positive pole of multiplication to be connected to one end of this multiplier by an inductance, negative pole is directly connected with the other end of multiplier, this multiplier comprises N electric capacity in parallel, is connected with the series circuit of a coupling inductance and high frequency silicon stack with described input voltage negative pole between n the electric capacity being connected and the two ends of n+1 electric capacity; With between anodal n+1 the electric capacity being connected of described input voltage and the two ends of n+2 electric capacity, be connected with another coupling inductance; N=1,3,5.......; All coupling inductances are all coupling on a magnetic core; It is 0 that the Same Name of Ends of multiple described coupling inductances flows through the counteracting of inductive current summation while arranging guarantee capacitor charging; Multiple described another coupling inductance Same Name of Ends directions are consistent; N electric capacity two ends satiable inductor in parallel.All satiable inductors are coupling on a magnetic core.
Suppose satiable inductor saturated after and its capacitance voltage in parallel overturn as negative polarity completely and be worth identically, be positioned at the described high frequency silicon stack of coupling inductance series connection of a certain side of capacitance group, the electric discharge between prevention adjacent capacitor.In addition, also should ensure that the opposite side coupling inductance Same Name of Ends direction in capacitance group is consistent.
The invention has the beneficial effects as follows:
The principle of pulse multiplier of the present invention and Fitch have similarity at the United States Patent (USP) [6] of 1964, are all that after utilizing electric capacity to be full of electricity, polarity upset is realized multiplication of voltage.But circuit and traditional F itch circuit have remarkable difference described in this patent: 1, charge circuit is made up of coupling inductance instead of resistance, thereby ensure that the charging interval is shorter, the voltagesecond product of satiable inductor is less.2, controlling inductance and electric capacity starting of oscillation is not by gas switch, but satiable inductor (magnetic switch).Magnetic switch does not have the problem of electrode erosion and insulation recovery, thereby this circuit can be moved under high repetition frequency.
Brief description of the drawings:
Fig. 1 exempts to reset magnetic compression circuit topology figure;
Fig. 2 is level Four pulse multiplier emulation voltage oscillogram;
Fig. 3 level Four pulse multiplier circuit figure;
Fig. 4 is Pyatyi pulse multiplier circuit figure;
Fig. 5 is eight grades of pulse multiplier circuit figure;
Fig. 6 level Four pulse multiplier experimental voltage oscillogram.
Embodiment:
Below in conjunction with accompanying drawing, the present invention is described in detail.
Embodiment 1:
Designed level Four pulse multiplier, accompanying drawing 3 is shown in by its circuit diagram:
1,4 charging capacitor C6-C9 are placed side by side, and the upper end of C6 and C7, the lower end of C7 and C8, and C8 is connected with the upper end of C9.
2, the pin (being C6 lower end and C7 upper end, C7 lower end and C8 upper end, C8 lower end and C9 upper end) that adjacent capacitor does not connect links together by coupling inductance.Connect according to illustrated Same Name of Ends, in the time of capacitor charging, coupling inductance current flowing summation is zero, and this can be explained as follows.Suppose that when charging each capacitor charging waveform is consistent, therefore its charging current i is identical any moment.Connect according to the coupling inductance in figure, can obtain: flow through L
1current i
l1=4i.i
l2=3i.i
l3=2i.i
l4=i. and L
1with L
3for Same Name of Ends current flowing, L
2with L
4for different name end current flowing, therefore total current is zero.
3, C6 satiable inductor MS3 in parallel with C8 two ends and MS4, and the two is coupling on a magnetic core.
4, L2 and L4 series connection high frequency silicon stack D1 and D2, thus prevent that, after C6 and the upset of C8 voltage, C7 and C9 are respectively to their electric discharge.Because another coupling inductance in capacitance group only has mono-of L3, therefore there is not the problem that its Same Name of Ends direction is consistent.
The operation principle of this circuit meets the operation principle of the pulse multiplier described in patent, is summarized as follows:
1, C5 is charged to u by front stage circuits
0time, magnetic switch MS2 is saturated, and C5 starts to the resonant charging of pulse multiplier by the pulsactor of MS2 subsequently.Recharge here the stage, the electric current summation of the coupling inductance of pulse multiplier is 0, thereby ensures that it can be considered short circuit.Therefore, pulse multiplier is equivalent to four capacitor C 6-C9 parallel connection.
2, when C6-C9 resonant charging is to peak value u
0time, magnetic switch MS3 and MS4 are saturated, C6 and MS3, C8 and MS4 resonant discharge.And because now coupling inductance and diode play inter-stage buffer action, therefore the upper voltage of C7 and C9 keeps almost constant.
3, as C6 and oscillate to approximately-u of C8 both end voltage
0time, four capacitances in series voltage sums are from 0 drop to-4u
0, i.e. output (C9 lower end is to C6 lower end) pulse voltage, and amplitude is 4u, thereby realizes the target of 4 times of pulse multiplications.
Embodiment 2:
As shown in Figure 4, for the structure of Pyatyi pulse multiplier Pyatyi pulse multiplier is equivalent to the final stage Capacitance parallel connection coupling inductance L18 of level Four pulse multiplier and connecting of capacitor C 24, and capacitor C 24 is in parallel with magnetic switch M13.In addition, to flow into net current be that zero, L15 connects with the coupling inductance L16 of the same number of turn to coupling inductance when ensureing to charge, and the coupling direction of L14 and L17 and level Four pulse multiplier is contrary.
Embodiment 3:
As shown in Figure 5, be eight grades of pulse multipliers, to compare with level Four pulse multiplier, the structure of eight grades of pulse multipliers is equivalent to after two level Four pulse multiplier stage connection, by the coupling direction negate of L5 and L11 in upper figure.This arrangement mode of coupling inductance is to be zero in order to ensure that eight grades of pulse multipliers coupling inductance in the time charging flows into net current, and the coupling direction of upper row's coupling inductance is consistent.
According to above-mentioned method for designing, can design the pulse multiplier of different progression (N electric capacity is exactly N level), they have the double effects of pulse amplitude multiplication and rising edge compression.
Utilize Matlab Simulink module to carry out circuit simulation to level Four pulse multiplier, obtained capacitance voltages at different levels and output voltage waveforms, as shown in Figure 2.Visible, each step voltage is consistent at charging stage waveform, and now equiva lent impedance is very low to show coupling inductance.In 25 μ s, when capacitance voltage is charged to 100V, magnetic switch is saturated, and two-stage capacitance voltage overturns at 2 μ s, and therefore, voltage multiplication efficiency is 95.5% to output voltage-382V., and pulse compression multiple is 12.5 times.
Level Four pulse multiplier has been built in experiment, as shown in Figure 3.First order electric capacity and output voltage waveforms are as shown in Figure 4.Visible, in 15 μ s, capacitance voltage is charged to 400V.Subsequently, magnetic switch is saturated, and in 5 μ s, therefore, voltage multiplication efficiency is 90% to output pulse amplitude 1.44kV., and rising edge compression multiple is 3 times.
Claims (1)
1. the repetitive frequency pulsed multiplier based on Fitch circuit, need the input voltage positive pole of multiplication to be connected to one end of this multiplier by a satiable inductor or magnetic switch, negative pole is directly connected with the other end of multiplier, it is characterized in that: this multiplier comprises N electric capacity in parallel, between n the electric capacity being connected with described input voltage negative pole and the two ends of n+1 electric capacity, be connected with the series circuit of a coupling inductance and high frequency silicon stack; With between anodal n+1 the electric capacity being connected of described input voltage and the two ends of n+2 electric capacity, be connected with another coupling inductance; N=l, 3,5 ....; All coupling inductances are all coupling on a magnetic core; It is 0 that the Same Name of Ends of multiple described coupling inductances flows through the counteracting of inductive current summation while arranging guarantee capacitor charging; Multiple described another coupling inductance Same Name of Ends directions are consistent; N electric capacity two ends satiable inductor in parallel;
All satiable inductors are coupling on a magnetic core;
N is 4 or 5 or 8.
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|---|---|---|---|
| CN201210053777.5A CN102594127B (en) | 2012-03-02 | 2012-03-02 | Repetition frequency compact pulse multiplier based on Fitch circuit |
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|---|---|---|---|
| CN201210053777.5A CN102594127B (en) | 2012-03-02 | 2012-03-02 | Repetition frequency compact pulse multiplier based on Fitch circuit |
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| CN102594127A CN102594127A (en) | 2012-07-18 |
| CN102594127B true CN102594127B (en) | 2014-11-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931867B (en) * | 2012-10-10 | 2015-01-07 | 西安交通大学 | Pulse voltage-multiplying generation device with repetition frequency |
| CN107659200A (en) * | 2017-11-15 | 2018-02-02 | 西安交通大学 | Cascade connection type submicrosecond level high-voltage pulse generator for vacuum interrupter ageing |
| CN111464067B (en) * | 2020-03-17 | 2021-07-06 | 重庆大学 | High-frequency extremely short electron gun grid regulation pulse power supply system |
| CN112366976A (en) * | 2020-11-14 | 2021-02-12 | 大连理工大学 | Multistage magnetic pulse compression power supply |
| CN112366975A (en) * | 2020-11-14 | 2021-02-12 | 大连理工大学 | Multi-pulse-width output magnetic compression power supply |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4375594A (en) * | 1981-01-12 | 1983-03-01 | The United States Of America As Represented By The Secretary Of The Army | Thyratron Marx high voltage generator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5105097A (en) * | 1991-02-01 | 1992-04-14 | Lasertechnics, Inc. | Passive magnetic switch for erecting multiple stage, high-pulse-rate voltage multipliers |
| US5914974A (en) * | 1997-02-21 | 1999-06-22 | Cymer, Inc. | Method and apparatus for eliminating reflected energy due to stage mismatch in nonlinear magnetic compression modules |
| PL213859B1 (en) * | 2008-03-27 | 2013-05-31 | Univ West Pomeranian Szczecin Tech | The manner of forming of high voltage impulse in generator's module and high voltage impulse in generator |
-
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- 2012-03-02 CN CN201210053777.5A patent/CN102594127B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4375594A (en) * | 1981-01-12 | 1983-03-01 | The United States Of America As Represented By The Secretary Of The Army | Thyratron Marx high voltage generator |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平10-323057A 1998.12.04 * |
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Granted publication date: 20141105 Termination date: 20180302 |