CN102593076B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN102593076B CN102593076B CN201110148043.0A CN201110148043A CN102593076B CN 102593076 B CN102593076 B CN 102593076B CN 201110148043 A CN201110148043 A CN 201110148043A CN 102593076 B CN102593076 B CN 102593076B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a kind of semiconductor device.Above-mentioned semiconductor device comprises a substrate, and comprise a circuit region and a sealing ring district, above-mentioned sealing ring district is around foregoing circuit district.One seal ring structure, be arranged at the top in above-mentioned sealing ring district, above-mentioned seal ring structure has a Part I and is positioned at the Part II above above-mentioned Part I, wherein above-mentioned Part I has a width W 1, above-mentioned Part II has a width W 2, and above-mentioned width W 1 is less than above-mentioned width W 2.The present invention can promote the yield of packaging technology significantly.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly a kind of seal ring structure and forming method thereof, with Protective IC chip.
Background technology
In an integrated circuit (IC) technique, first can manufacture semiconductor wafer, each semiconductor wafer comprises multiple semi-conductor chip.Manufacture after semiconductor wafer, cutting semiconductor chip to isolate semi-conductor chip, distinctly to encapsulate each semi-conductor chip.
In cutting and packaging technology, use that a seal ring structure does not decay by moisture with Protective IC, the impact of ionic soil and damage.
In some configurations, seal ring structure occupies a huge width of the chip area of each semi-conductor chip.So effective chip area that each semi-conductor chip provides functional circuitry can be reduced.In order to increase more effectively chip area, the chip area of each semi-conductor chip must be increased.Therefore, can tail off with the chip count in semiconductor wafer, and the cost of each semi-conductor chip can uprise.
Therefore, in this technical field, have and need a kind of semiconductor device and manufacture method thereof, to meet the demand and to overcome the shortcoming of known technology.
Summary of the invention
In view of this, one embodiment of the invention provides a kind of semiconductor device.Above-mentioned semiconductor device comprises a substrate, and comprise a circuit region and a sealing ring district, above-mentioned sealing ring district is around foregoing circuit district.One seal ring structure, be arranged at the top in above-mentioned sealing ring district, above-mentioned seal ring structure has a Part I and is positioned at the Part II above above-mentioned Part I, wherein above-mentioned Part I has a width W 1, above-mentioned Part II has a width W 2, and above-mentioned width W 1 is less than above-mentioned width W 2.
Another embodiment of the present invention provides a kind of semiconductor device.Above-mentioned semiconductor device one substrate, comprise a circuit region and a sealing ring district, above-mentioned sealing ring district is around foregoing circuit district.One first dielectric layer, is arranged at the top in above-mentioned sealing ring district, and said first dielectric layer has bottom one and is positioned at the top above above-mentioned bottom.One second dielectric layer, is arranged at the top of said first dielectric layer, and wherein said first dielectric layer and said second dielectric layer have different specific inductive capacity.One seal ring structure, among the above-mentioned top being embedded in said second dielectric layer and said first dielectric layer, wherein above-mentioned seal ring structure does not extend in the above-mentioned bottom of said first dielectric layer.。
The present invention again another embodiment provides a kind of manufacture method of semiconductor device.Above-mentioned manufacturing method for semiconductor device comprises provides a substrate, and it has a circuit region and a sealing ring district.Form one first dielectric layer in the top in above-mentioned sealing ring district, said first dielectric layer has bottom one and is positioned at the top above above-mentioned bottom.Form one second dielectric layer in the top of said first dielectric layer, wherein said first dielectric layer and said second dielectric layer have different specific inductive capacity.Form a seal ring structure, among the above-mentioned top being embedded in said second dielectric layer in above-mentioned sealing ring district and said first dielectric layer.
In an embodiment of the present invention, seal ring structure is embedded among the top of the second dielectric layer and the first dielectric layer.What the top of above-mentioned seal ring structure can prevent the interface along the first dielectric layer and the second dielectric layer from producing breaks, peel off or lamination.Therefore, the yield of packaging technology can be promoted significantly.In other embodiments of the present invention, the bottom being narrower than top of seal ring structure is formed in the first dielectric layer, to provide additional space for the use of Functional integrated circuit and circuit coiling in sealing ring district.
Accompanying drawing explanation
Fig. 1 is the process flow diagram with the manufacture method of the semiconductor device of seal ring structure according to one embodiment of the invention.
Fig. 2 is the process flow diagram with the manufacture method of the semiconductor device of seal ring structure according to another embodiment of the present invention.
Fig. 3 is the plane top view of two integrated circuit dies with seal ring structure.
Fig. 4 and Fig. 5 is the sectional view obtaining the seal ring structure of different embodiments of the invention from the C-C ' tangent line of Fig. 3.
Fig. 6 to Fig. 9 is the processed semiconductor devices sectional view with seal ring structure of the embodiment of the present invention according to Fig. 4.
Figure 10 to Figure 13 is the processed semiconductor devices sectional view with seal ring structure of the embodiment of the present invention according to Fig. 5.
Wherein, description of reference numerals is as follows:
100,200 ~ method;
102,104,106,108,110,202,204,206,208 ~ step;
300A, 300B ~ semiconductor device;
301 ~ semiconductor substrate;
302 ~ circuit region;
304 ~ sealing ring district;
306 ~ Cutting Road district;
308 ~ contact bar;
310A ~ the first dielectric layer;
310A
1~ bottom;
310A
2~ top;
310B, 320B ~ dielectric layer;
312 ~ metal level;
314 ~ interlayer aperture layer;
316A ~ Part I;
316B ~ Part II;
316C ~ seal ring structure;
318 ~ outside seal ring structure;
320A ~ the second dielectric layer;
322 ~ protective seam;
324 ~ metal gasket;
326 ~ polyimide layer;
W1, W2, W3, W4, W5 ~ width.
Embodiment
Describe in detail and the example illustrated along with accompanying drawing, as reference frame of the present invention with each embodiment below.In accompanying drawing or instructions describe, similar or identical part all uses identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can expand, and to simplify or conveniently to indicate.Moreover in accompanying drawing, the part of each element will to describe explanation respectively, and it should be noted that in figure the element do not drawn or describe, be the form known to art technician.
Multiple nude film is manufactured on semiconductor wafer.Above-mentioned nude film is separated from each other by the Cutting Road between nude film.In instructions " wafer " word is usually relevant with semiconductor substrate, and it is formed with different layers and component structure.In certain embodiments, semiconductor substrate can comprise silicon or elemental semiconductor, such as gallium arsenide (gallium arsenic), indium phosphide (indium phosphide), SiGe (Si/Ge) or silit (siliconcarbide).And above-mentioned different layers such as can comprise dielectric layer, doped layer and/or polysilicon layer.And said elements structure example is as comprised transistor, resistance and/or electric capacity, it or may may can not be connected internally to extra active circuit by an internal connecting layer.
Please refer to Fig. 1, the manufacture method 100 with the semiconductor device of seal ring structure of one embodiment of the invention originates in step 102.Step 102 provides semiconductor substrate.Above-mentioned semiconductor substrate has a circuit region and a sealing ring district.Above-mentioned sealing ring district is around foregoing circuit district.Then, carry out step 104, in the top in above-mentioned sealing ring district and foregoing circuit district, the top of meaning and semiconductor substrate, forms one first dielectric layer.Then, carry out step 106, form a Part I of a seal ring structure, and be embedded in first dielectric layer in above-mentioned sealing ring district.Then, carry out step 108, form one second dielectric layer in the top of said first dielectric layer.In an embodiment of the present invention, the first dielectric layer and the second dielectric layer have different specific inductive capacity.Then, carry out step 110, form a Part II of above-mentioned seal ring structure, the width of above-mentioned Part II is greater than the width of above-mentioned Part I, and above-mentioned Part II is embedded among said first dielectric layer in above-mentioned sealing ring district and said second dielectric layer.The above-mentioned Part II of above-mentioned seal ring structure is positioned at the top of the above-mentioned Part I of above-mentioned seal ring structure.Also can before the step of method 100, among or provide other layers afterwards, wire, interlayer hole and structure.In other embodiments of the present invention, the order of above-mentioned technique can be changed.
Please refer to Fig. 2, the manufacture method 200 with the semiconductor device of seal ring structure of one embodiment of the invention originates in step 202.Step 202 provides semiconductor substrate.Above-mentioned semiconductor substrate has a circuit region and a sealing ring district.Above-mentioned sealing ring district is around foregoing circuit district.Then, carry out step 204, in the top in above-mentioned sealing ring district and foregoing circuit district, the top of meaning and semiconductor substrate, forms one first dielectric layer.Said first dielectric layer has bottom a top and one.Then, carry out step 206, form one second dielectric layer in the top of said first dielectric layer.In an embodiment of the present invention, said first dielectric layer and said second dielectric layer have different specific inductive capacity.Then, carry out step 208, form a seal ring structure, among the above-mentioned top being embedded in said second dielectric layer in above-mentioned sealing ring district and said first dielectric layer.Seal ring structure does not stretch into the bottom of first dielectric layer in sealing ring district.In an embodiment of the present invention, the above-mentioned bottom of the first dielectric layer does not comprise any seal ring structure.Also can before the step of method 200, among or provide other layers afterwards, wire, interlayer hole and structure.In other embodiments of the present invention, the order of above-mentioned technique can be changed.
Fig. 3 is the plane top view of two integrated circuit (IC) nude films with seal ring structure.Semiconductor device 300A or 300B comprises circuit region 302, sealing ring district 304 and a Cutting Road district 306.Fig. 4 and Fig. 5 is the sectional view obtaining the seal ring structure of different embodiments of the invention from the C-C ' tangent line of Fig. 3.
Please refer to Fig. 4, semiconductor device 300A can comprise semiconductor substrate 301, and it has above-mentioned semiconductor substrate and has a sealing ring district 304 and the Cutting Road district 306 around a circuit region 302.In an embodiment of the present invention, sealing ring district 304 is in order to make a seal ring structure formed thereon, and circuit region 302 is in order to form at least one transistor.Semiconductor substrate 301 can comprise silicon or elemental semiconductor, such as gallium arsenide (gallium arsenic), indium phosphide (indium phosphide), SiGe (Si/Ge) or silit (silicon carbide).Semiconductor substrate 301 also can comprise doped region, such as a P type trap, a N-type trap and/or a heavy doping active area, such as P type heavy doping (P+) active area.
Semiconductor device 300A also can comprise the isolated district be formed in semiconductor substrate 301, such as shallow trench insulation (STI) or selective oxidation insulation (LOCOS), in order to be completely cut off in other regions of active area and semiconductor substrate 301.In an embodiment of the present invention, active area can form N-type metal-oxide semiconductor (MOS) (NMOS) element or a P-type mos (PMOS) element.
Semiconductor device 300A can also comprise the component structure be formed at above semiconductor substrate 301, such as transistor, resistance and/or electric capacity (figure does not show).Semiconductor device 300A also can comprise contact bar 308, semiconductor substrate 301 to be electrically coupled to the seal ring structure 318/316A/316B of follow-up formation.
Semiconductor device 300A comprises the one first dielectric layer 310A of top being arranged at sealing ring district 304, Cutting Road district 306 and circuit region 302.First dielectric layer 310A can comprise the dielectric layer 310B of multilayer.In some embodiments of the invention, dielectric layer 310B can be combined to form by some of the low-k of specific inductive capacity between 2.9 and 3.8 (low-k) material, the ultralow dielectric of specific inductive capacity between 2.5 and 2.9 (ULK) material or low-k (low-k) material.As a rule, the specific inductive capacity of dielectric layer 310B is lower, and dielectric layer can become more frangible, be easier to produce layering (delamination) or fracture phenomena.
One second dielectric layer 320A is set above the first dielectric layer 310A.Said first dielectric layer 310A and said second dielectric layer 320A has different specific inductive capacity.In an embodiment of the present invention, the specific inductive capacity of said first dielectric layer 310A is less than the specific inductive capacity of said second dielectric layer 320A.Said second dielectric layer 320A has compared with the more tolerance of the first dielectric layer 310A, to reduce corrosion or the mechanical damage of the integrated circuit (IC) to below.Said second dielectric layer 320A can comprise the dielectric layer 320B of multilayer.In an embodiment of the present invention, dielectric layer 320B can be formed by oxide, undoped silicon glass (USG) or silicon dioxide.
Please refer to Fig. 4, a seal ring structure 316A/316B is set above sealing ring district 304, and be embedded among the first dielectric layer 310A and the second dielectric layer 320A.Seal ring structure 316A/316B is abutted to circuit region 302, and does not have other seal ring structure between seal ring structure 316A/316B and circuit region 302.Seal ring structure 316A/316B has a Part I 316A and is positioned at the Part II 316B of top of Part I 316A.Part I 316A is embedded in the first dielectric layer 310A, and Part II 316B is embedded among the first dielectric layer 310A and the second dielectric layer 320A.In an embodiment of the present invention, Part II 316B has a width W 2, between 4 μm and 10 μm.Part I 316A has a width W 1, and it is less than width W 2.In some embodiments of the invention, width W 1 is less than 75% of width W 2.In another embodiment of the present invention, seal ring structure 316A/316B also comprises a Part III (figure does not show), and the Part III be positioned at below Part I 316A has a width W 3, and it is less than width W 1.In some embodiments of the invention, width W 3 is less than 50% of W2.The present invention is again in another embodiment, semiconductor device 300A also can comprise an internal connection-wire structure, a component structure or an alignment mark (figure does not show), be arranged in sealing ring district 304, and to be positioned at below Part II 316B and to be abutted to Part I 316A, meaning is namely between Part I 316A and circuit region 302.Said elements structure example, as comprised one or more transistor, resistance and/or electric capacity (figure does not show), is positioned at above semiconductor substrate 301.Valuably, the seal ring structure 316A/316B with narrower Part I 316A can provide additional space for the use of Functional integrated circuit and circuit coiling in sealing ring district 304.The seal ring structure 316A/316B with wider Part II 316B provides strong intensity can put in circuit region 302 along the interface of the first dielectric layer 310A and the second dielectric layer 320A to prevent any breaking in sealing ring district 304.
Semiconductor device 300A also can comprise an outside seal ring structure 318, is arranged in sealing ring district 304.Outside seal ring structure 318 is adjacent and around seal ring structure 316A/316B.Outside seal ring structure 318 has a width W 4, between 2 μm and 4 μm.Outside seal ring structure 318 separates by a width W 5 with seal ring structure 316A/316B.Width W 5 is between 2 μm and 4 μm.
In some embodiments of the invention, form seal ring structure 316A/316B and outside seal ring structure 318 above semiconductor substrate 301 while, in circuit region 302, form internal connection-wire structure (figure does not show).Seal ring structure 316A/316B, outside seal ring structure 318 and internal connection-wire structure can comprise Bu Tong stacking metal level 312 and interlayer aperture layer 314, are arranged at the metal level 312 in one or more dielectric layer 310B, 320B and interlayer aperture layer 314.Metal level 312 and interlayer aperture layer 314 can comprise a conducting metal, such as aluminium, aluminium alloy, copper, aldary or combinations thereof.The layer of internal connection-wire structure and seal ring structure 316A/316B and outside seal ring structure 318 share identical metal level 312 and interlayer aperture layer 314.Internal connection-wire structure is electrically connected integrated circuit, and provides the electric connection from integrated circuit to top layer.Integrated circuit in seal ring structure 316A/316B and outside seal ring structure 318 protection circuit district 302 is by the impact of moisture and pollution.In addition, during cutting nude film technique, seal ring structure 316A/316B and outside seal ring structure 318 protection circuit district 302 injury-free.In some embodiments of the invention, outside seal ring structure 318 can be omitted, make seal ring structure 316A/316B become unique seal ring structure between circuit region 302 and Cutting Road district 306.
In an embodiment of the present invention, semiconductor device 300A can comprise multiple metal level 312, and the Part II 316B of seal ring structure 316A/316B occupies several topmost metal layer of multiple metal level 312, such as, occupy and go up three-layer metal layer most.Part I 316A occupies remaining metal level 312.Outside seal ring structure 318 occupies whole metal levels 312.
Refer again to Fig. 4, a protective seam 322 is set in the top of Part II 320A, seal ring structure 316A/316B and outside seal ring structure 318.Protective seam 322 can comprise one layer or more, such as silicon nitride or silicon oxynitride.Protective seam 322 is avoided or reduces integrated circuit suffering moisture, machinery and radiation damage.
One metal gasket 324 is set in the top of protective seam 322.Metal gasket 324 extends through protective seam 322 and contacts with the metal level 312 of the superiors of seal ring structure 316A/316B.Available not synsedimentary, patterning and etching technique and technique form the structure of metal gasket 324.Metal gasket 324 provides physical strength with the interface between polyimide (polyimide) layer 326 protecting protective seam 322 and follow-up formation.Valuably, metal gasket 324 has and is reduced in chip when using cutting technique, and chip edge breaks or interface debonding phenomenon between protective seam 322 and polyimide (polyimide) layer 326.
Refer again to Fig. 4, a polyimide (polyimide) layer 326 is set in the top of protective seam 322 and metal gasket 324.Polyimide (polyimide) layer 326 can be considered a pressure buffer thing, is passed to protective seam 322 with the pressure reducing group technology.
Valuably, the seal ring structure 316A/316B with narrower Part I 316A provides strong intensity can put in circuit region 302 along the interface of the first dielectric layer 310A and the second dielectric layer 320A to prevent any breaking in sealing ring district 304.
Fig. 5 is the sectional view obtaining the seal ring structure of different embodiments of the invention from the C-C ' tangent line of the semiconductor device 300B of Fig. 3.The structure of a part can be similar in fact the embodiment that Fig. 4 discloses, and the explanation of sharing structure is at this no longer repeated description.
Please refer to Fig. 5, semiconductor device 300B can comprise semiconductor substrate 301, and it has above-mentioned semiconductor substrate and has a sealing ring district 304 and the Cutting Road district 306 around a circuit region 302.In an embodiment of the present invention, sealing ring district 304 is in order to make a seal ring structure formed thereon, and circuit region 302 is in order to form at least one transistor.
Semiconductor device 300B can also comprise the component structure be formed at above semiconductor substrate 301, such as transistor, resistance and/or electric capacity (figure does not show).Semiconductor device 300A also can comprise contact bar 308, semiconductor substrate 301 to be electrically coupled to the outside seal ring structure 318 of follow-up formation.
Refer again to Fig. 5, in sealing ring district 304, the top of Cutting Road district 306 and circuit region 302 arranges one first dielectric layer 310A.First dielectric layer 310A can have one bottom 310A
1with a top 310A
2, and the dielectric layer 310B of multilayer can be comprised.In some embodiments of the invention, dielectric layer 310B can be combined to form by some of the low-k of specific inductive capacity between 2.9 and 3.8 (low-k) material, the ultralow dielectric of specific inductive capacity between 2.5 and 2.9 (ULK) material or low-k (low-k) material.
One second dielectric layer 320A is set above the first dielectric layer 310A.Said first dielectric layer 310A and said second dielectric layer 320A has different specific inductive capacity.In an embodiment of the present invention, the specific inductive capacity of said first dielectric layer 310A is less than the specific inductive capacity of said second dielectric layer 320A.Said second dielectric layer 320A has compared with the more tolerance of the first dielectric layer 310A, to reduce corrosion or the mechanical damage of the integrated circuit (IC) to below.Said second dielectric layer 320A can comprise the dielectric layer 320B of multilayer.In an embodiment of the present invention, dielectric layer 320B can be formed by oxide, undoped silicon glass (USG) or silicon dioxide.
Please refer to Fig. 5, a seal ring structure 316C is set above sealing ring district 304, and be embedded in the top 310A of the second dielectric layer 320A and the first dielectric layer 310A
2among both.Seal ring structure 316C does not stretch into the bottom 310A of the first dielectric layer 310A
1.Seal ring structure 316C is abutted to circuit region 302.Other seal ring structure is not had between seal ring structure 316C and circuit region 302.In an embodiment of the present invention, the bottom 310A of the first dielectric layer 310A
1do not comprise any seal ring structure.Seal ring structure 316C has a width W 2, between 4 μm and 10 μm.The present invention is again in another embodiment, and semiconductor device 300B also can comprise an internal connection-wire structure, a component structure or an alignment mark (figure does not show), is arranged in sealing ring district 304, and is positioned at below seal ring structure 316C.Said elements structure example, as comprised one or more transistor, resistance and/or electric capacity (figure does not show), is positioned at above semiconductor substrate 301.Valuably, the bottom 310A of the first dielectric layer 310A is not stretched into
1seal ring structure 316C can provide below seal ring structure 316C additional space for Functional integrated circuit and circuit coiling the use in sealing ring district 304.In addition, the top 310A of the first dielectric layer 310A is extended into from the second dielectric layer 320A
2seal ring structure 316C in sealing ring district 304, provide strong intensity can put in circuit region 302 along the interface of the first dielectric layer 310A and the second dielectric layer 320A to prevent any breaking.
Semiconductor device 300B also can comprise an outside seal ring structure 318, is arranged in sealing ring district 304.Outside seal ring structure 318 is adjacent and around seal ring structure 316C.Outside seal ring structure 318 has a width W 4, between 2 μm and 4 μm.Outside seal ring structure 318 separates by a width W 5 with seal ring structure 316C.Width W 5 is between 2 μm and 4 μm.
In some embodiments of the invention, form seal ring structure 316C and outside seal ring structure 318 above semiconductor substrate 301 while, in circuit region 302, form internal connection-wire structure (figure does not show).Seal ring structure 316C, outside seal ring structure 318 and internal connection-wire structure can comprise Bu Tong stacking metal level 312 and interlayer aperture layer 314, are arranged at the metal level 312 in one or more dielectric layer 310B, 320B and interlayer aperture layer 314.The layer of internal connection-wire structure and seal ring structure 316A/316B and outside seal ring structure 318 share identical metal level 312 and interlayer aperture layer 314.During cutting nude film technique, seal ring structure 316C and outside seal ring structure 318 protection circuit district 302 injury-free.In some embodiments of the invention, outside seal ring structure 318 resists moisture and cutting damage around seal ring structure 316C to provide.
In an embodiment of the present invention, semiconductor device 300B can comprise multiple metal level 312 in sealing ring district 304, and wherein seal ring structure 316C occupies several topmost metal layer of multiple metal level 312, such as, go up three-layer metal layer most.Outside seal ring structure 318 occupies whole metal levels 312.
Refer again to Fig. 5, protective seam 322, metal gasket 324 and a polyimide (polyimide) layer 326 is sequentially set in the top of Part II 320A.The manufacture method of above-mentioned layer, materials and structures can be similar in fact the announcement embodiment of Fig. 4, at this no longer repeated description.
Valuably, the bottom 310A of the first dielectric layer 310A is not stretched into
1seal ring structure 316C additional space can be provided for the use of circuit coiling, enter in circuit region 302 to prevent any breaking.
Fig. 6 to Fig. 9 is the pass figure of Fig. 1 and 3 figure, and it is the process section with the semiconductor device 300A of seal ring structure of one or more embodiment of the present invention according to Fig. 4.
Fig. 6 shows the step 102 according to Fig. 1, provides semiconductor substrate 301.Above-mentioned semiconductor substrate 301 has a sealing ring district 304 and the Cutting Road district 306 around a circuit region 302.Semiconductor substrate 301 can comprise silicon or elemental semiconductor, such as gallium arsenide (gallium arsenic), indium phosphide (indiumphosphide), SiGe (Si/Ge) or silit (silicon carbide).Semiconductor substrate 301 also can comprise doped region, and such as a P type trap, a N-type trap and/or are doped with source region, such as P type heavy doping (P+) active area.The component structure of such as transistor, resistance and/or electric capacity (figure does not show) can be formed in the top of semiconductor substrate 301.Contact bar 308 can be formed, semiconductor substrate 301 to be electrically coupled to the seal ring structure 318/316A/316B of follow-up formation.
Then, in sealing ring district 304, the top of Cutting Road district 306 and circuit region 302 forms one first dielectric layer 310A, and meaning is namely according to the step 104 of Fig. 1.First dielectric layer 310A can have as shown in Figure 6 first formed one bottom 310A
1, and the top 310A formed afterwards as shown in Figure 7
2.First dielectric layer 310A can comprise the dielectric layer 310B of multilayer.In an embodiment of the present invention, can utilize conventional depositing operation, such as chemical vapor deposition (CVD) method and/or high-density plasma CVD method form dielectric layer 310B.In some embodiments of the invention, dielectric layer 310B can be combined to form by some of the low-k of specific inductive capacity between 2.9 and 3.8 (low-k) material, the ultralow dielectric of specific inductive capacity between 2.5 and 2.9 (ULK) material or low-k (low-k) material.
Form the Part I 316A of seal ring structure in the top in sealing ring district 304, and be embedded in the bottom 310A of the first dielectric layer 310A
1in, meaning is namely according to the step 106 of Fig. 1.Seal ring structure is abutted to circuit region 302, and does not have other seal ring structure between seal ring structure and circuit region 302.In an embodiment of the present invention, Part I 316A has a width W 1.In another embodiment of the present invention, seal ring structure also comprises a Part III (figure does not show), is positioned at the below of Part I 316A.Part III has a width W 3, and it is less than width W 1.
Optionally in sealing ring district 304, form an outside seal ring structure 318.Outside seal ring structure 318 is adjacent and around the Part I 316A of seal ring structure.Outside seal ring structure 318 has a width W 4, between 2 μm and 4 μm.Outside seal ring structure 318 separates by a width W 5 with seal ring structure 316A.Width W 5 is between 2 μm and 4 μm.
In some embodiments of the invention, while the Part I 316A forming seal ring structure above semiconductor substrate 301 and outside seal ring structure 318, in circuit region 302, form internal connection-wire structure.Part I 316A, the outside seal ring structure 318 of seal ring structure can comprise Bu Tong stacking metal level 312 and interlayer aperture layer 314 with internal connection-wire structure, are arranged in one or more dielectric layer.Different depositing operation, Patternized technique and etch process can be utilized to form metal level 312 and interlayer aperture layer 314.Metal level 312 and interlayer aperture layer 314 can comprise a conducting metal, such as aluminium, aluminium alloy, copper, aldary or combinations thereof.
Please refer to Fig. 7, in the bottom 310A shown in Fig. 6
1the top 310A of upper formation first dielectric layer 310A
2.Utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make outside seal ring structure 318 continue to extend into the top 310A of the first dielectric layer 310A
2.The Part II 316B of seal ring structure is formed above the Part I 316A of seal ring structure.Also can utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make the Part II 316B of seal ring structure be embedded in the top 310A of the first dielectric layer 310A
2in.In an embodiment of the present invention, Part II 316B has a width W 2, between 4 μm and 10 μm.Part I 316A has a width W 1, and it is less than width W 2.In some embodiments of the invention, width W 1 is less than 75% of width W 2.In other embodiments of the invention, the width W 3 of Part III is less than 50% of W2.
The present invention is again in another embodiment, semiconductor device 300A also can comprise an internal connection-wire structure, a component structure or an alignment mark (figure does not show), be arranged in sealing ring district 304, and to be positioned at below Part II 316B and to be abutted to Part I 316A, meaning is namely between Part I 316A and circuit region 302.Said elements structure example, as comprised one or more transistor, resistance and/or electric capacity (figure does not show), is positioned at above semiconductor substrate 301.Valuably, the seal ring structure 316A/316B with narrower Part I 316A can provide additional space for the use of Functional integrated circuit and circuit coiling.
Please refer to Fig. 8, arrange one second dielectric layer 320A in the top of the first dielectric layer 310A, meaning is namely according to the step 108 of Fig. 1.Said first dielectric layer 310A and said second dielectric layer 320A has different specific inductive capacity.In an embodiment of the present invention, the specific inductive capacity of said first dielectric layer 310A is less than the specific inductive capacity of said second dielectric layer 320A.Said second dielectric layer 320A can comprise the dielectric layer 320B of multilayer.In one embodiment of the invention, can utilize conventional depositing operation, such as chemical vapor deposition (CVD) method and/or high-density plasma CVD method form dielectric layer 320B.In an embodiment of the present invention, dielectric layer 320B can be formed by oxide, undoped silicon glass (USG) or silicon dioxide.
Utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make outside seal ring structure 318 continue to extend into the second dielectric layer 320A.Also can utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make the Part II 316B of seal ring structure be embedded among the first dielectric layer 310A and the second dielectric layer 320A, meaning is namely according to the step 110 of Fig. 1.In an embodiment of the present invention, semiconductor device 300A can comprise and forms multiple metal level 312, and the Part II 316B of seal ring structure occupy multiple metal level 312 go up three-layer metal layer most.Part I 316A occupies remaining metal level 312.In an alternative embodiment of the invention, outside seal ring structure 318 occupies whole metal levels 312.The seal ring structure 316A/316B with wider Part II 316B provides strong intensity in sealing ring district 304, can put in circuit region 302 to prevent any breaking along the interface of the first dielectric layer 310A and the second dielectric layer 320A.
Please refer to Fig. 9, a protective seam 322 is set in the top of Part II 320A, seal ring structure 316A/316B and outside seal ring structure 318.Protective seam 322 can comprise one layer or more, such as silicon nitride or silicon oxynitride.Conventional depositing operation can be utilized, such as chemical vapor deposition (CVD) method Deposition of protective layer 322.The structure that micro-shadow after depositing operation and etch process are wanted with selectivity patterning.Protective seam 322 is avoided or reduces integrated circuit suffering moisture, machinery and radiation damage.
One metal gasket 324 is set in the top of protective seam 322.Metal gasket 324 extends through protective seam 322 and contacts with the metal level 312 of the superiors of seal ring structure 316A/316B.Plated metal pad 324 can be carried out by physical vapour deposition (PVD) (PVD) method of the sputter deposition of the sputtered target material such as utilizing aluminium, copper or its alloy to form, then utilize micro-shadow and etch process patterned deposition layer.
In the top of protective seam 322 and metal gasket 324, a polyimide (polyimide) layer 326 is set.Polyimide (polyimide) layer 326 can be considered a pressure buffer thing, is passed to protective seam 322 with the pressure reducing group technology.
Figure 10 to Figure 13 is the graph of a relation of the 2nd and 3 figure, and it is the process section with the semiconductor device 300B of seal ring structure of one or more embodiment of the present invention according to Fig. 5.The manufacture method of above-mentioned layer, materials and structures can be similar in fact the embodiment that Fig. 6 to Fig. 9 discloses, at this no longer repeated description.
Figure 10 shows the step 202 according to Fig. 2, provides semiconductor substrate 301.Above-mentioned semiconductor substrate 301 has a sealing ring district 304 and the Cutting Road district 306 around a circuit region 302.The component structure of such as transistor, resistance and/or electric capacity (figure does not show) can be formed in the top of semiconductor substrate 301.Form contact bar 308, semiconductor substrate 301 to be electrically coupled to the seal ring structure 318/316A/316B of follow-up formation.
Then, in the sealing ring district 304 of semiconductor substrate 301, the top of Cutting Road district 306 and circuit region 302 forms one first dielectric layer 310A, and meaning is namely according to the step 204 of Fig. 2.First dielectric layer 310A can have as shown in Figure 10 first formed one bottom 310A
1, and the top 310A formed afterwards as shown in figure 11
2.First dielectric layer 310A can comprise the dielectric layer 310B of multilayer.In some embodiments of the invention, dielectric layer 310B can be combined to form by some of the low-k of specific inductive capacity between 2.9 and 3.8 (low-k) material, the ultralow dielectric of specific inductive capacity between 2.5 and 2.9 (ULK) material or low-k (low-k) material.
In sealing ring district 304, form an outside seal ring structure 318, and be embedded in the bottom 310A of Part I 316A
1.Outside seal ring structure 318 has a width W 4, between 2 μm and 4 μm.Form outside seal ring structure 318 above semiconductor substrate 301 while, in circuit region 302, form internal connection-wire structure (figure does not show).Outside seal ring structure 318 and internal connection-wire structure can comprise Bu Tong stacking metal level 312 and interlayer aperture layer 314, are arranged in one or more dielectric layer.The layer of internal connection-wire structure and outside seal ring structure 318 shares identical metal level 312 and interlayer aperture layer 314.Different depositing operation, Patternized technique and etch process can be utilized to form metal level 312 and interlayer aperture layer 314.
Please refer to Figure 11, sequentially in the bottom 310A shown in Figure 10
1the top 310A of upper formation first dielectric layer 310A
2.Utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make outside seal ring structure 318 continue to extend into the top 310A of the first dielectric layer 310A
2.Also utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, form seal ring structure 316C and make it be embedded in top 310A
2among.Seal ring structure 316C does not stretch into the bottom 310A of the first dielectric layer 310A
1.Seal ring structure 316C is abutted to circuit region 302.Other seal ring structure is not had between seal ring structure 316C and circuit region 302.In an embodiment of the present invention, the bottom 310A of the first dielectric layer 310A
1do not comprise any seal ring structure.
In an embodiment of the present invention, seal ring structure 316C has a width W 2, between 4 μm and 10 μm.Outside seal ring structure 318 separates by a width W 5 with seal ring structure 316C.Width W 5 is between 2 μm and 4 μm.
Valuably, the bottom 310A of the first dielectric layer 310A is not stretched into
1seal ring structure 316C can provide additional space, for the use of Functional integrated circuit and circuit coiling.In one embodiment of the invention, semiconductor device 300B also can comprise an internal connection-wire structure, a component structure or an alignment mark (figure does not show), is arranged in sealing ring district 304, and is positioned at below seal ring structure 316C.Said elements structure example, as comprised one or more transistor, resistance and/or electric capacity (figure does not show), is positioned at above semiconductor substrate 301.
Please refer to Figure 12, arrange one second dielectric layer 320A above the first dielectric layer 310A, meaning is namely according to the step 206 of Fig. 2.Said first dielectric layer 310A and said second dielectric layer 320A has different specific inductive capacity.In an embodiment of the present invention, the specific inductive capacity of said first dielectric layer 310A is less than the specific inductive capacity of said second dielectric layer 320A.Said second dielectric layer 320A can comprise the dielectric layer 320B of multilayer.In an embodiment of the present invention, dielectric layer 320B can be formed by oxide, undoped silicon glass (USG) or silicon dioxide.
Utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make outside seal ring structure 318 and seal ring structure 316C continue to extend into the second dielectric layer 320A.Also can utilize the mode of be staggeredly stacked metal level 312 and interlayer aperture layer 314, make seal ring structure 316C be embedded in the top 310A of the first dielectric layer 310A
2among the second dielectric layer 320A, meaning is namely according to the step 208 of Fig. 2.In an embodiment of the present invention, semiconductor device 300B can comprise and forms multiple metal level 312, and seal ring structure 316C occupy multiple metal level 312 go up three-layer metal layer most.In an embodiment of the present invention, outside seal ring structure 318 occupies whole metal levels 312.Valuably, the top 310A of the first dielectric layer 310A is extended into from the second dielectric layer 320A
2seal ring structure 316C in sealing ring district 304, provide strong intensity can put in circuit region 302 along the interface of the first dielectric layer 310A and the second dielectric layer 320A to prevent any breaking.
Please refer to Figure 13, protective seam 322, metal gasket 324 and a polyimide (polyimide) layer 326 is sequentially set in the top of Part II 320A.Through above-mentioned technique, form semiconductor device 300B.The manufacture method of above-mentioned layer, materials and structures can be similar in fact the announcement embodiment of Fig. 9, at this no longer repeated description.
In some embodiments of the invention, seal ring structure is embedded among the top of the second dielectric layer and the first dielectric layer.What the top of above-mentioned seal ring structure can prevent the interface along the first dielectric layer and the second dielectric layer from producing breaks, peel off or lamination.Therefore, the yield of packaging technology can be promoted significantly.In other embodiments of the present invention, the bottom being narrower than top of seal ring structure is formed in the first dielectric layer, to provide additional space for the use of Functional integrated circuit and circuit coiling in sealing ring district.
Although the present invention discloses as above with embodiment; but itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when the scope standard defined depending on the claim of enclosing.
Claims (8)
1. a semiconductor device, comprising:
One substrate, comprise a circuit region and a sealing ring district, sealing ring district is around this circuit region; And
One seal ring structure, is arranged at the top in sealing ring district, and sealing ring structure has a Part I and is positioned at the Part II above this Part I, and wherein this Part I comprises:
At least one the first metal layer, defines a width W 1 of this Part I; And
At least one first interlayer aperture layer, is located immediately on this at least one the first metal layer, and an interlayer hole of this at least one first interlayer aperture layer has a width, and this width is less than this width W 1;
This Part II comprises:
At least one second metal level, defines a width W 2 of this Part II; And
At least one second interlayer aperture layer, be located immediately on this at least one second metal level, an interlayer hole of this at least one second interlayer aperture layer has a width, and this width is less than this width W 2, and this width W 1 is less than this width W 2.
2. semiconductor device as claimed in claim 1, also comprises:
One first dielectric layer, is arranged at the top in sealing ring district;
One second dielectric layer, is arranged at the top of this first dielectric layer, and wherein this first dielectric layer and this second dielectric layer have different specific inductive capacity; And
Sealing ring structure is embedded among this first dielectric layer and this second dielectric layer, and wherein this Part I is arranged in this first dielectric layer, and this Part II is positioned among this first dielectric layer and this second dielectric layer.
3. semiconductor device as claimed in claim 1, wherein the specific inductive capacity of this first dielectric layer is less than the specific inductive capacity of this second dielectric layer.
4. semiconductor device as claimed in claim 1, wherein this semiconductor device lacks any other seal ring structure between sealing ring structure and this circuit region.
5. semiconductor device as claimed in claim 1, also comprises multiple metal level, is arranged in sealing ring district, and what wherein this Part II occupied those metal levels goes up three-layer metal layer most.
6. semiconductor device as claimed in claim 1, also comprises an intraconnections, a component structure or an alignment mark, is arranged in sealing ring district, and is positioned at below this Part II.
7. semiconductor device as claimed in claim 1, wherein this width W 1 is less than 75% of this width W 2.
8. semiconductor device as claimed in claim 1, wherein sealing ring structure also comprises a Part III, is positioned at below this Part I, and this Part III has the width W 3 being less than this width W 1, and wherein this width W 3 is less than 50% of this width W 2.
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| US13/004,261 US9117831B2 (en) | 2011-01-11 | 2011-01-11 | Seal ring structure for integrated circuit chips |
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| US8587090B2 (en) * | 2011-07-29 | 2013-11-19 | Mediatek Inc. | Die seal ring structure |
| JP5968711B2 (en) * | 2012-07-25 | 2016-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US9048246B2 (en) * | 2013-06-18 | 2015-06-02 | United Microelectronics Corp. | Die seal ring and method of forming the same |
| US9881884B2 (en) | 2015-08-14 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
| KR102541563B1 (en) * | 2016-04-27 | 2023-06-08 | 삼성전자주식회사 | Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device |
| US9728474B1 (en) | 2016-09-28 | 2017-08-08 | Globalfoundries Singapore Pte. Ltd. | Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same |
| DE102016125686B4 (en) | 2016-12-23 | 2024-08-29 | Infineon Technologies Ag | SEMICONDUCTOR ARRANGEMENT WITH A SEALING STRUCTURE |
| US20180337228A1 (en) * | 2017-05-18 | 2018-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel seal ring for iii-v compound semiconductor-based devices |
| CN110310938A (en) * | 2018-03-20 | 2019-10-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and electronic device |
| US10381403B1 (en) * | 2018-06-21 | 2019-08-13 | Globalfoundries Singapore Pte. Ltd. | MRAM device with improved seal ring and method for producing the same |
| CN108987377B (en) * | 2018-07-20 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for positioning boundary of field area |
| CN110858578B (en) * | 2018-08-23 | 2021-07-13 | 联华电子股份有限公司 | Die seal ring and manufacturing method thereof |
| CN111656517A (en) * | 2020-04-10 | 2020-09-11 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and method for manufacturing the same |
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| US5880528A (en) * | 1997-09-30 | 1999-03-09 | Intel Corporation | Energy absorbing structures to prevent damage to an integrated circuit |
| JP2005142262A (en) * | 2003-11-05 | 2005-06-02 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| JP2007027639A (en) * | 2005-07-21 | 2007-02-01 | Nec Electronics Corp | Semiconductor device |
| JP4699172B2 (en) | 2005-10-25 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US8125052B2 (en) * | 2007-05-14 | 2012-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structure with improved cracking protection |
| KR101581431B1 (en) * | 2009-09-04 | 2015-12-30 | 삼성전자주식회사 | Semiconductor chips having guard rings and methods of fabricating the same |
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| US9117831B2 (en) | 2015-08-25 |
| CN104485313A (en) | 2015-04-01 |
| CN104485313B (en) | 2019-02-15 |
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