CN102590732B - Multi-channel circuit asymmetry calibration method - Google Patents

Abstract

The invention relates to a multi-channel circuit asymmetry calibration method which comprises the following steps: S1, establishing the input-output responding mathematical models F (F, x, n) of a multi-channel circuit; S2, fitting to obtain the coefficient factors (aijn, bijn ) of the mathematical models F (F, x, n); and S3, collecting the actual output value of the multi-channel circuit by taking the peripheral actual multi-channel signal as the actual input signal of the multi-channel circuit, selecting the corresponding coefficient factors (aijn, bijn ) according to the amplitude and the frequency of the actual multi-channel signal, and calculating to obtain the amplitude of the calibration input signal according to the selected coefficient factors (aijn, bijn ), the actual output value and the expression (1) so as to correct the amplitude of the actual input signal and calibrate the asymmetry of the multi-channel circuit. The multi-channel circuit asymmetry calibration method has high precision and good flexibility and can be used for effectively correcting the asymmetry of the multi-channel circuit without affecting the data bandwidth and the noise level of the original signal.

Description

A kind of calibration steps of multi-channel circuit asymmetry

Technical field

The present invention relates to one for the asymmetric automatic calibrating method of multi-channel circuit, relate in particular to a kind of calibration steps of the multi-channel circuit asymmetry for accelerator field digital line position monitoring processor (DBPM).

Background technology

In Beam position monitor system, position probe is output as multi channel signals, and therefore, corresponding need to be at the output terminal connecting multi-channel radio-frequency front-end treatment circuit of position probe.Because the performance of the components and parts of the same model in each passage front-end processing circuit there are differences with non-linear, as power amplifier, wave filter and modulus conversion chip, therefore, easily cause the input and output response of each single circuit passage asymmetric; Multichannel asymmetry can affect the high-acruracy survey performance of DBPM processor, therefore, need to effectively calibrate this multi-channel circuit asymmetry.

Multi-channel circuit asymmetry modification method is the multichannel balance method based on radio-frequency (RF) switch at present, and main contents are the real-time switching by radio-frequency (RF) switch, periodically carry out processing signals with each passage, revise passage asymmetry by average mode.Owing to having used the switch periodically switching in the method, the periodic noise of therefore being introduced by change-over switch will affect noise level and the data bandwidth of processor.For this reason, need to improve the modification method of this multi-channel circuit asymmetry now.

Summary of the invention

The problem existing in order to solve above-mentioned prior art, the present invention aims to provide the calibration steps of the multi-channel circuit asymmetry that a kind of precision is high, dirigibility is good, effectively to revise the asymmetry of multi-channel circuit, and do not affect data bandwidth and the noise level of original signal.

The calibration steps of a kind of multi-channel circuit asymmetry of the present invention, it comprises the following steps:

Step S1, set up the input and output response mathematical model f (f of described multi-channel circuit, x, n), this step S1 comprises: according to different incoming frequency scopes and amplitude range, the input and output response function of described multi-channel circuit is divided into multiple first-order linear functions, the expression formula of described multiple first-order linear functions is:

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{11n}\·x+b_{11n},& X_0\≤x\≤X_1\\ a_{12n}\·x+b_{12n},& X_1\≤x\≤X_2\\ a_{13n}\·x+b_{13n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{1\mathrm{jn}}\·x+b_{1\mathrm{jn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_0\≤f\≤F_1$

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{21n}\·x+b_{21n},& X_0\≤x\≤X_1\\ a_{22n}\·x+b_{22n},& X_1\≤x\≤X_2\\ a_{23n}\·x+b_{23n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{2\mathrm{jn}}\·x+b_{2\mathrm{jn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_1\≤f\≤F_2$

… (1)

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{(i-1)1n}\·x+b_{(i-1)1n},& X_0\≤x\≤X_1\\ a_{(i-1)2n}\·x+b_{(i-1)2n},& X_1\≤x\≤X_2\\ a_{(i-1)3n}\·x+b_{(i-1)3n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{(i-1)jn}\·x+b_{(i-1)jn},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_{i-2}\≤f\≤F_{i-1}$

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{i1n}\·x+b_{i1n},& X_0\≤x\≤X_1\\ a_{i2n}\·x+b_{i2n},& X_1\≤x\≤X_2\\ a_{i3n}\·x+b_{i3n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{\mathrm{ijn}}\·x+b_{\mathrm{ijn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_{i-1}\≤f\≤F_i$

Wherein, f is frequency variable, and x is amplitude variable, and n is port number, and n>=1, F ₀, F ₁..., F _ifor frequency defines a little, the interval number that i is frequency partition, and i>=1, X ₀, X ₁..., X _jfor amplitude defines a little, j is the interval number that amplitude is divided, and j>=1, (a _ijn, b _ijn) be the coefficient factor;

Step S2, matching obtains the coefficient factor (a of described mathematical model f (f, x, n) _ijn, b _ijn), this step S2 comprises:

Step S21, the input signal using the n road signal of a standard signal source output as n passage of described multi-channel circuit, and the frequency f of the input signal of each passage _iequate, and define the amplitude X of the input signal of each passage _ij1=X _ij2=...=X _ijn, the output valve of a described n passage is respectively Y _ij1, Y _ij2..., Y _ijn;

Step S22, controls the initial magnitude X of the input signal of n passage of described multi-channel circuit ₁₀₁=X ₁₀₂=...=X _10n=A ₀original frequency f ₁=B ₁, the initial output valve Y of n passage of collection ₁₀₁, Y ₁₀₂..., Y _10n;

Step S23, the frequency of input signal of controlling n passage of described multi-channel circuit is constant, changes the amplitude of this input signal, makes X _1jn=X _{1 (j-1) n}+ A _j, wherein, n is taken as respectively 1,2 ..., n, being captured in respectively frequency is f ₁the input signal of different amplitudes under the output valve Y of n passage _1j1, Y _1j2..., Y _1jn, wherein, A _jfor the increment value of signal source amplitude, j>=1;

Step S24, by data group (X _{1 (j-1) n}, Y _{1 (j-1) n}) and (X _1jn, Y _1jn) in substitution expression formula (1), calculate the coefficient factor $a_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}-Y_{1(j-1)n}}{X_{1\mathrm{jn}}-X_{1(j-1)n}},$ $b_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}\·X_{1(j-1)n}-Y_{1(j-1)n}\·X_{1\mathrm{jn}}}{X_{1(j-1)n}-X_{1\mathrm{jn}}},$ Wherein, j >=1, n is taken as respectively 1,2 ..., n;

Step S25, changes the frequency of the input signal of n passage of described multi-channel circuit, makes f _i=f _i-1+ B _i, the amplitude of initialization current input signal, makes X _i01=X _i02=...=X _i0n=A ₀, gather the initial output valve Y of a current n passage _i01, Y _i02..., Y _i0n, wherein, B _ifor the increment value of signal source frequency, i>=2;

Step S26, repeating step S23, obtaining in frequency is f _ithe input signal of different amplitudes under the output valve Y of n passage _ij1, Y _ij2..., Y _ijn, wherein, i>=2, j>=1;

Step S27, repeating step S24, obtains the coefficient factor wherein, i>=2, j>=1, n is taken as respectively 1,2 ..., n;

Step S3, using periphery, actual multiple signals, as the real input signal of described multi-channel circuit, gather the real output value of this multi-channel circuit, according to the amplitude of described actual multiple signals and the corresponding coefficient factor of frequency selection purposes (a _ijn, b _ijn), and according to this coefficient factor (a choosing _ijn, b _ijn), described real output value and expression formula (1), calculate the amplitude of calibration input signal, to revise the amplitude of described real input signal, calibrate the asymmetry of described multi-channel circuit.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, the increment value A of described each signal source amplitude _jall identical, wherein, j>=1.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, the increment value A of described each signal source amplitude _jall not identical, wherein, j>=1.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, the increment value B of described each signal source frequency _iall identical, i>=2.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, the increment value B of described each signal source frequency _iall not identical, i>=2.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, the n road signal of described standard signal source output is unifrequency sinusoidal signal.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, described step S2 also comprises: step S28, stores the described coefficient factor (a _ijn, b _ijn), wherein, i>=1, j>=1.

In the calibration steps of above-mentioned multi-channel circuit asymmetry, described method is by being connected to FPGA, embedded controller or the computer realization of output terminal of described multi-channel circuit.

Owing to having adopted above-mentioned technical solution, the present invention is by setting up the input and output response mathematical model of multi-channel circuit to be calibrated, and use standard signal source to measure the coefficient factor of mathematical model building, finally in the time of signal processing stage, utilize the inconsistency of the multiple passages of coefficient factor correction that matching obtains.Because method of the present invention does not need to switch in real time radio-frequency (RF) switch, only FPGA (field programmable logic array (FPLA)), embedded controller or computer realization need be utilized, thereby data bandwidth and the noise level of original input signal can be avoided affecting.

Brief description of the drawings

Fig. 1 is the circuit theory diagrams of realizing the calibration steps of a kind of multi-channel circuit asymmetry of the present invention.

Embodiment

Below in conjunction with accompanying drawing, provide preferred embodiment of the present invention, and be described in detail.

As shown in Figure 1, in the present embodiment, the present invention, i.e. a kind of calibration steps of multi-channel circuit asymmetry, using the FPGA 2 of output terminal that is connected to multi-channel circuit to be calibrated 1 as implementation platform, the 4 passage front-end processing circuit that multi-channel circuit 1 is measured for being applied to accelerator.

Method of the present invention comprises the following steps:

Step S1, set up the input and output response mathematical model f (f of multi-channel circuit 1, x, n), this step S1 comprises: according to different incoming frequency scopes and amplitude range, the input and output response function of multi-channel circuit 1 is divided into multiple first-order linear functions, the expression formula of the plurality of first-order linear function is:

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{11n}\·x+b_{11n},& X_0\≤x\≤X_1\\ a_{12n}\·x+b_{12n},& X_1\≤x\≤X_2\\ a_{13n}\·x+b_{13n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{1\mathrm{jn}}\·x+b_{1\mathrm{jn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_0\≤f\≤F_1$

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{21n}\·x+b_{21n},& X_0\≤x\≤X_1\\ a_{22n}\·x+b_{22n},& X_1\≤x\≤X_2\\ a_{23n}\·x+b_{23n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{2\mathrm{jn}}\·x+b_{2\mathrm{jn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_1\≤f\≤F_2$

… (1)

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{(i-1)1n}\·x+b_{(i-1)1n},& X_0\≤x\≤X_1\\ a_{(i-1)2n}\·x+b_{(i-1)2n},& X_1\≤x\≤X_2\\ a_{(i-1)3n}\·x+b_{(i-1)3n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{(i-1)jn}\·x+b_{(i-1)jn},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_{i-2}\≤f\≤F_{i-1}$

$f(f,x,n)=\left\{\begin{array}{cc}{a}_{i1n}\·x+b_{i1n},& X_0\≤x\≤X_1\\ a_{i2n}\·x+b_{i2n},& X_1\≤x\≤X_2\\ a_{i3n}\·x+b_{i3n},& X_2\≤x\≤X_3\\ ...,& ...\\ a_{\mathrm{ijn}}\·x+b_{\mathrm{ijn}},& X_{j-1}\≤x\≤X_j\end{array}\right\},F_{i-1}\≤f\≤F_i$

Wherein, f is frequency variable, and x is amplitude variable, and n is port number, and n>=1, F ₀, F ₁..., F _ifor frequency defines a little, the interval number that i is frequency partition, and i>=1, X ₀, X ₁..., X _jfor amplitude defines a little, j is the interval number that amplitude is divided, and j>=1, (a _ijn, b _ijn) be the coefficient factor;

In the present embodiment, n is taken as respectively 1,2,3 and 4, i=10 (that is, being 10 intervals by frequency partition), j=50 (, amplitude being divided into 50 intervals);

Step S2, matching obtains the coefficient factor (a of mathematical model f (f, x, n) _ijn, b _ijn); This step S2 comprises:

Step S21, the 4 road signals of a standard signal source 3 being exported by switching radio-frequency (RF) switch 4 are as the input signal of 4 passages of multi-channel circuit 1, and the frequency f of the input signal of each passage _iequate, and define the amplitude X of the input signal of each passage _ij1=X _ij2=X _ij3=X _ij4, the output valve of a described n passage is respectively Y _ij1, Y _ij2, Y _ij3and Y _ij4;

Step S22, FPGA 2 controls the initial magnitude X of the input signal of 4 passages of multi-channel circuit 1 ₁₀₁=X ₁₀₂=X ₁₀₃=X ₁₀₄=A ₀, original frequency f ₁=B ₁, the initial output valve Y of n passage of collection ₁₀₁, Y ₁₀₂, Y ₁₀₃, Y ₁₀₄;

Step S23, the frequency of the input signal of 4 passages of FPGA2 control multi-channel circuit 1 is constant, changes the amplitude of this input signal, makes X _1jn=X _{1 (j-1) n}+ A _j, wherein, n is taken as respectively 1,2,3 and 4, and being captured in respectively frequency is f ₁the input signal of different amplitudes under the output valve Y of 4 passages _1j1, Y _1j2, Y _1j3, Y _1j4, wherein, A _jfor the increment value of signal source amplitude, 1≤j≤50; Can select the increment value A of each signal source amplitude according to practical application _jall identical, i.e. A ₁=A ₂=...=A _j, also can select different A _j, i.e. A ₁≠ A ₂≠ A _j, in the present embodiment, adopt identical amplitude increment value A _j;

Step S24, by FPGA 2 by data group (X _{1 (j-1) n}, Y _{1 (j-1) n}) and (X _1jn, Y _1jn) in substitution expression formula (1), calculate the coefficient factor $a_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}-Y_{1(j-1)n}}{X_{1\mathrm{jn}}-X_{1(j-1)n}},$ $b_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}\·X_{1(j-1)n}-Y_{1(j-1)n}\·X_{1\mathrm{jn}}}{X_{1(j-1)n}-X_{1\mathrm{jn}}},$ Wherein, 1≤j≤50, n is taken as respectively 1,2,3 and 4;

For example, in the time of j=1, the coefficient factor is:

$a_{111}=\frac{Y_{111}-Y_{101}}{X_{111}-X_{101}},$ $b_{111}=\frac{Y_{111}\·X_{101}-Y_{101}\·X_{111}}{X_{101}-X_{111}}$

$a_{112}=\frac{Y_{112}-Y_{102}}{X_{112}-X_{102}},$ $b_{112}=\frac{Y_{112}\·X_{102}-Y_{102}\·X_{112}}{X_{102}-X_{112}}$

$a_{113}=\frac{Y_{113}-Y_{103}}{X_{113}-X_{103}},$ $b_{111}=\frac{Y_{113}\·X_{103}-Y_{103}\·X_{113}}{X_{103}-X_{113}}$

$a_{114}=\frac{Y_{114}-Y_{104}}{X_{114}-X_{104}},$ $b_{111}=\frac{Y_{114}\·X_{104}-Y_{104}\·X_{114}}{X_{104}-X_{114}}$

Step S25, FPGA 2 changes the frequency of the input signal of 4 passages of multi-channel circuit, makes f _i=f _i-1+ B _i, the amplitude of initialization current input signal, makes X _i01=X _i02=X _i03=X _i04=A ₀, gather the initial output valve Y of current 4 passages _i01, Y _i02, Y _i03, Y _i04, wherein, B _ifor the increment value of signal source frequency, 2≤i≤10; Can select the increment value B of each signal source frequency according to practical application _iall identical, i.e. B ₁=B ₂=...=B _i, also can select different B _i, i.e. B ₁≠ B ₂≠ B _i;

Step S26, repeating step S23, obtaining in frequency is f _ithe input signal of different amplitudes under the output valve Y of 4 passages _ij1, Y _ij2, Y _ij3, Y _ij4, wherein, 2≤i≤10,1≤j≤50;

Step S27, repeating step S24, obtains the coefficient factor wherein, 2≤i≤10,1≤j≤50, n is taken as respectively 1,2,3 and 4;

Step S28, by the coefficient factor (a _ijn, b _ijn) be stored in the storer 21 of FPGA 2, wherein, 1≤i≤10,1≤j≤50, n is taken as respectively 1,2,3 and 4

Step S3, by switching the real input signal of the just peripheral actual multiple signals of radio-frequency (RF) switch 4 (being probe signal in the present embodiment) as multi-channel circuit 1, gather the real output value of this multi-channel circuit 1, in storer 21, choose the corresponding coefficient factor (a according to the amplitude of actual multiple signals and frequency _ijn, b _ijn), and according to this coefficient factor (a choosing _ijn, b _ijn), real output value and expression formula (1), calculate the amplitude of calibration input signal, to revise the amplitude of real input signal, the asymmetry of calibration multi-channel circuit 1.

In the present embodiment, what standard signal source adopted is the circuit based on phaselocked loop, and 4 road signals of its output are unifrequency sinusoidal signal, and the output power of signal and frequency are controlled by FPGA 2.Method of the present invention can also be by being connected to embedded controller or the computer realization of output terminal of described multi-channel circuit; Multi-channel circuit 1 can also be for being applied to 8 passages of accelerator measurement or the front-end processing circuit of 16 passages.

Above-described, be only preferred embodiment of the present invention, not in order to limit scope of the present invention, the above embodiment of the present invention can also make a variety of changes.Be that simple, the equivalence that every claims according to the present patent application and description are done changes and modify, all fall into the claim protection domain of patent of the present invention.The present invention not detailed description be routine techniques content.

Claims (7)

1. a calibration steps for multi-channel circuit asymmetry, is characterized in that, said method comprising the steps of:

Step S1, set up the input and output response mathematical model f (f of described multi-channel circuit, x, n), this step S1 comprises: according to different incoming frequency scopes and amplitude range, the input and output response function of described multi-channel circuit is divided into multiple first-order linear functions, the expression formula of described multiple first-order linear functions is:

Wherein, f is frequency variable, and x is amplitude variable, and n is port number, and n>=1, F ₀, F ₁..., F _ifor frequency defines a little, the interval number that i is frequency partition, and i>=1, X ₀, X ₁..., X _jfor amplitude defines a little, j is the interval number that amplitude is divided, and j>=1, (a _ijn, b _ijn) be the coefficient factor;

Step S2, matching obtains the coefficient factor (a of described mathematical model f (f, x, n) _ijn, b _ijn), this step S2 comprises:

Step S21, the input signal using the n road signal of a standard signal source output as n passage of described multi-channel circuit, the n road signal of described standard signal source output is unifrequency sinusoidal signal, and the frequency f of the input signal of each passage _iequate, and define the amplitude X of the input signal of each passage _ij1=X _ij2=...=X _ijn, the output valve of a described n passage is respectively Y _ij1, Y _ij2..., Y _ijn;

Step S22, controls the initial magnitude X of the input signal of n passage of described multi-channel circuit ₁₀₁=X ₁₀₂=...=X _10n=A ₀original frequency f ₁=B ₁, the initial output valve Y of n passage of collection ₁₀₁, Y ₁₀₂..., Y _10n;

Step S23, the frequency of input signal of controlling n passage of described multi-channel circuit is constant, changes the amplitude of this input signal, makes X _1jn=X _{1 (j-1) n}+ A _j, wherein, n is taken as respectively 1,2 ..., n, being captured in respectively frequency is f ₁the input signal of different amplitudes under the output valve Y of n passage _1j1, Y _1j2..., Y _1jn, wherein, A _jfor the increment value of signal source amplitude, j>=1;

Step S24, by data group (X _{1 (j-1) n}, Y _{1 (j-1) n}) and (X _1jn, Y _1jn) in substitution expression formula (1), calculate the coefficient factor $a_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}-Y_{1(j-1)n}}{X_{1\mathrm{jn}}-X_{1(j-1)n}},$ $b_{1\mathrm{jn}}=\frac{Y_{1\mathrm{jn}}\·X_{1(j-1)n}-Y_{1(j-1)n}\·X_{1\mathrm{jn}}}{X_{1(j-1)n}-X_{1\mathrm{jn}}},$ Wherein, j >=1, n is taken as respectively 1,2 ..., n;

Step S25, changes the frequency of the input signal of n passage of described multi-channel circuit, makes f _i=f _i-1+ B _i, the amplitude of initialization current input signal, makes X _i01=X _i02=...=X _i0n=A ₀, gather the initial output valve Y of a current n passage _i01, Y _i02..., Y _i0n, wherein, B _ifor the increment value of signal source frequency, i>=2;

Step S26, repeating step S23, obtaining in frequency is f _ithe input signal of different amplitudes under the output valve Y of n passage _ij1, Y _ij2..., Y _ijn, wherein, i>=2, j>=1;

Step S27, repeating step S24, obtains the coefficient factor wherein, i>=2, j>=1, n is taken as respectively 1,2 ..., n;

Step S3, using periphery, actual multiple signals, as the real input signal of described multi-channel circuit, gather the real output value of this multi-channel circuit, according to the amplitude of described actual multiple signals and the corresponding coefficient factor of frequency selection purposes (a _ijn, b _ijn), and according to this coefficient factor (a choosing _ijn, b _ijn), described real output value and expression formula (1), calculate the amplitude of calibration input signal, to revise the amplitude of described real input signal, calibrate the asymmetry of described multi-channel circuit.

2. the calibration steps of multi-channel circuit asymmetry according to claim 1, is characterized in that, the increment value A of described each signal source amplitude _jall identical, wherein, j>=1.

3. the calibration steps of multi-channel circuit asymmetry according to claim 1, is characterized in that, the increment value A of described each signal source amplitude _jall not identical, wherein, j>=1.

4. according to the calibration steps of the multi-channel circuit asymmetry described in claim 1,2 or 3, it is characterized in that the increment value B of described each signal source frequency _iall identical, i>=2.

5. according to the calibration steps of the multi-channel circuit asymmetry described in claim 1,2 or 3, it is characterized in that the increment value B of described each signal source frequency _iall not identical, i>=2.

6. the calibration steps of multi-channel circuit asymmetry according to claim 1, is characterized in that, described step S2 also comprises: step S28, stores the described coefficient factor (a _ijn, b _ijn), wherein, i>=1, j>=1.

7. the calibration steps of multi-channel circuit asymmetry according to claim 1, is characterized in that, described method is by being connected to FPGA, embedded controller or the computer realization of output terminal of described multi-channel circuit.