CN107976646A - A kind of signal power characteristic compensation method and device based on vector network analyzer - Google Patents

Abstract

The invention discloses a signal power characteristic compensation method and device based on a vector network analyzer, which collects uncompensated power values at each frequency point, calculates the DAC value required when the uncompensated power value is compensated to the set power, and according to the DAC value to adjust the power, and store the DAC value in the memory; according to the current frequency and step frequency, get the storage position of the DAC value required for current frequency compensation, read the DAC value from the memory, and output it to the compensation circuit Perform power compensation. The present invention saves the compensation data in the hardware and implements the power compensation function through the hardware, which reduces the calculation time and improves the scanning speed. At the same time, a point is calibrated every 16MHz. When the scanning point falls within this range, the The compensation data is called, and the compensation accuracy is improved by increasing the number of calibration points.

Description

A signal power characteristic compensation method and device based on vector network analyzer

technical field

The invention relates to the field of signal power characteristic compensation, in particular to a signal power characteristic compensation method and device based on a vector network analyzer.

Background technique

For a vector network analyzer, the power accuracy of the output signal has a direct impact on the measurement accuracy. At present, there is a certain gap between the domestic vector network analyzer and the similar foreign products in the power accuracy of the port output signal, mainly because Due to the influence of the frequency characteristics of components during the signal generation process, the power of the output signal at different frequency points is different.

At present, the domestic vector network analyzer mainly uses the software interpolation method to compensate the power of the output signal to keep the power of the output signal at the set value. Since this method is realized by software, each scanning point needs software calculation and then Compensation increases the scanning time. At the same time, this method only selects a small number of points in the entire scanning frequency band for power calibration, and the compensation accuracy is relatively poor.

With the development of measurement technology, users have higher and higher requirements for vector network analyzers. Due to the influence of device frequency characteristics, the power of the output signal of the vector network analyzer at different frequency points may be quite different from the program setting value, resulting in errors during measurement. Compared with similar foreign products, domestic vector network analyzers There is a certain gap, so reducing the power error and improving the measurement accuracy has become one of the problems that the vector network analyzer needs to solve.

At present, domestic vector network analyzers mostly use software interpolation method to improve output power accuracy. This method is to select several points in the entire scanning frequency band (generally, one point is selected every few hundred MHz). When the power is set to 0dBm, Use a power meter to calibrate the power of each calibration point to around 0dBm, and obtain a DAC value for each calibration point. During the scanning process, judge which two calibration points the currently scanned point falls between, and use these two The DAC value of the calibration point is used as a reference for the interpolation slope algorithm to obtain the DAC value of the current point, and then the DAC value of the current point is sent to the power setting circuit for DA conversion and added to the summation circuit to realize power compensation. Finally, all points scanned can meet the power accuracy index.

The existing technology mainly uses the software interpolation method for compensation. This method mainly realizes the power compensation of each scanning point through software. The software will select several points and calibrate them to the set value through the power meter to obtain the corresponding compensation data. During the process, the software will first judge which two calibration points the current scanning point falls between, and use these two points as a reference to perform an interpolation algorithm. Since each point needs to make such a judgment, the scanning time will increase and reduce. At the same time, the number of reference points selected by the software when calibrating with the power meter is relatively small, resulting in poor compensation accuracy.

To sum up, in the prior art, there is still no effective solution to the problems of increased scanning time and poor compensation accuracy of the software interpolation method.

Contents of the invention

In order to overcome the shortcomings of the prior art above, the present invention provides a signal power characteristic compensation method and device based on a vector network analyzer.

The technical scheme adopted in the present invention is:

A method for compensating signal power characteristics based on a vector network analyzer, comprising the following steps:

Step 1: Collect the uncompensated power value at each frequency point, calculate the DAC value required to compensate the uncompensated power value to the set power, adjust the power according to the DAC value, and store the DAC value in the memory;

Step 2: Obtain the storage location of the DAC value required for current frequency compensation according to the current frequency and step frequency, read the DAC value from the memory, and output it to the compensation circuit for power compensation.

Further, in the step 1, the uncompensated power value of each frequency point is collected, the DAC value required when the uncompensated power value is compensated to the set value is calculated, the power is adjusted according to the DAC value, and the DAC value is stored in memory, including:

Step 1.1: Divide the scanning range into multiple frequency bands at equal intervals, and calculate the adjustable power range of the compensation circuit;

Step 1.2: Collect the uncompensated power values of each point in each frequency band, and calculate the DAC value required for each uncompensated power value to compensate to the set power;

Step 1.3: The compensation circuit converts the DAC value into a voltage value for power adjustment according to the received DAC value, and obtains the adjusted power value;

Step 1.4: Verify whether the adjusted power value meets the expected compensation threshold, if not, calculate the DAC value again, and return to step 1.3; if satisfied, go to step 1.5;

Step 1.5: Store the DAC value into memory.

Further, the scanning range is divided into multiple frequency bands at equal intervals, and the adjustable power range of the compensation circuit is calculated, including:

Divide the entire scanning range into multiple frequency bands at equal intervals, and select the middle frequency point of each frequency band as the calibration reference;

Set the DAC value to 0 and 4095 respectively, and read the minimum adjustable power value when the DAC value is 0; the maximum adjustable power value when the DAC value is 4095;

The vector network analyzer sets a power value.

The power setting value is taken as the compensation target, and a certain error range deviated from the power setting value is taken as the compensation threshold.

Further, after the adjustable power range is calculated, the DAC value required for every 1dB change in power is also calculated.

Further, the acquisition of the uncompensated power value of each point in each frequency band, and calculating the DAC value required for each uncompensated power value to compensate the set power, including:

(1) The vector network analyzer collects the uncompensated power value at the current frequency point by connecting a power meter;

(2) According to the DAC value required when the power changes by 1dB, calculate the DAC value required when the uncompensated power value is compensated to the set power;

(3) Add a fixed frequency value on the basis of the current frequency to get the frequency of the next point, and repeat steps (1)-(2) until the frequency compensation of all points in the entire frequency range is obtained to the set power. DAC value.

Further, the verifying whether the adjusted power value reaches the power value threshold includes:

When the error between the adjusted power value and the power setting value is less than the power value threshold, the requirement is met; otherwise, the requirement is not met, according to the required DAC value and the error between the power value and the power setting value when the power changes by 1dB, Correct the DAC value required when the power value is compensated to the set value, and send the corrected DAC value to the compensation circuit for readjustment until the expected compensation threshold is met.

Further, in the step 2, according to the current frequency and the step frequency, the storage position of the DAC value required for the current frequency compensation is obtained, the DAC value is read from the memory, and output to the compensation circuit for power compensation, including :

Step 2.1: CPLD receives the start frequency and step frequency sent from the vector network analyzer;

Step 2.2: Divide the current frequency by the step frequency and round to get the storage position of the DAC value required for compensation of the frequency in the memory;

Step 2.3: Read the stored DAC value and output it to the compensation circuit;

Step 2.4: The compensation circuit performs power compensation at the current frequency point according to the DAC value, and at the same time adds the step frequency to the current frequency to obtain the frequency value of the next scanning point;

Step 2.5: Judging whether a trigger signal is received, if a trigger signal is received, repeat steps 2.2-2.4; otherwise, complete power compensation.

A signal power characteristic compensation device based on a vector network analyzer, comprising a vector network analyzer, a CPLD, a memory and a compensation circuit;

The vector network analyzer is connected with a power meter, which is used to collect the uncompensated power value of each frequency point, calculate the DAC value required when the uncompensated power value is compensated to the set value, and send it to the CPLD;

The CPLD is used to send the DAC value to the compensation circuit;

The compensation circuit is used to convert the received DAC value into a voltage value through DA conversion for power adjustment;

The memory is used to store the DAC value after power adjustment.

Further, the vector network analyzer sends the start frequency and the step frequency to the CPLD; the CPLD divides the frequency of the scan point by the step frequency, and rounds to obtain the frequency that should compensate for the DAC value in the memory. The address is stored, and the stored DAC value is read and output to the compensation circuit; the compensation circuit performs power compensation according to the received DAC value.

Compared with prior art, the beneficial effect of the present invention is:

(1) The present invention adds a 12-bit DAC circuit in the compensation circuit, the power can be adjusted by setting a suitable DAC, and data storage and reading are changed to hardware implementation, which avoids the time of software calculation and improves the scanning speed , and there are more calibration points at the same time, which also improves the compensation accuracy;

(2) The present invention saves the compensation data in the hardware and realizes the power compensation function through the hardware, realizes the part of the software calculation through the hardware, reduces the calculation time, improves the scanning speed, and adopts a point every 16MHz to calibrate at the same time, when scanning When the point falls within this range, the compensation data is called directly from the memory, and the compensation accuracy is improved by increasing the number of calibration points.

Description of drawings

The accompanying drawings constituting a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application, and do not constitute improper limitations to the present application.

Fig. 1 is the flow chart of the calibration process in the signal power characteristic compensation method based on vector network analyzer disclosed in the embodiment of the present invention;

Fig. 2 is a flow chart of the scanning process in the signal power characteristic compensation method based on the vector network analyzer disclosed in the embodiment of the present invention.

Detailed ways

It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and/or combinations thereof.

As introduced in the background technology, the software interpolation method in the prior art has the disadvantages of increased scan time and poor compensation accuracy. In order to solve the above technical problems, this application proposes a signal power characteristic compensation based on a vector network analyzer Methods and Apparatus.

Embodiment one

The purpose of this embodiment is to propose a signal power characteristic compensation method based on a vector network analyzer, which includes a calibration process and a scanning process.

1. Calibration process

As shown in Figure 1, it is a flow chart of the calibration process of signal power characteristic compensation. When calibrating, divide the entire scanning range into four to five frequency bands, select the middle frequency point of each frequency band as the calibration reference, set the 12-bit DAC to 0 and 4095, and the read power meter values are the minimum and maximum possible The adjusted power value is obtained by calculating the DAC value required for every 1dB change in power, and then starting from the starting frequency, select frequency points every 16MHz for power calibration, first read the power value at this point, and then calculate the The DAC value required when the power is compensated to the set value is added to the circuit for verification. If the error requirement is met, it will be saved to the memory. If it is not met, continue to adjust until it is met. The specific process is:

Step 101: Divide the scanning range into multiple frequency bands at equal intervals, and calculate the adjustable power range of the compensation circuit.

Divide the entire scanning range into multiple frequency bands at equal intervals, select the middle frequency point of each frequency band as the calibration reference; set the DAC value to 0 and 4095 respectively, and read the minimum adjustable power value when the DAC value is 0; when When the DAC value is 4095, the maximum adjustable power value is determined; a power setting value is determined by a vector network analyzer; the power setting value is used as the compensation target, and a certain error range from the power setting value is used as the compensation threshold.

At the same time, the DAC value required for every 1dB change in power is also calculated

Step 102: Collect the uncompensated power value P1 of each point in each frequency band, and calculate the DAC value required when each uncompensated power value is compensated to the set power.

The vector network analyzer collects the uncompensated power value at the current frequency point by connecting a power meter; according to the DAC value required when the power changes by 1dB, calculate the DAC value required when the uncompensated power value is compensated to the set power; at the current Add 16MHz to the frequency to get the frequency of the next point, and calculate the uncompensated power value P1 of the frequency at this point again; according to the DAC value required when the power changes by 1dB, calculate the uncompensated power value when it is compensated to the set power The required DAC value, until the frequency compensation of all points in the entire frequency band is obtained to the DAC value required for the set power, the DAC value is sent to the CPLD, and then sent to the compensation circuit through the CPLD.

Step 103: According to the received DAC value, the compensation circuit converts the DAC value into a voltage value for power adjustment, and obtains an adjusted power value P2.

In the compensation circuit, the DAC value is converted into a voltage value through DA conversion for power adjustment, and the adjusted power value P2 is read through a vector network analyzer.

Step 104: verify whether the adjusted power value P2 satisfies the expected compensation threshold, and if not, calculate the DAC value again and send it to the compensation circuit for readjustment until the expected compensation threshold is met.

When the error between the adjusted power value and the power setting value is less than the power value threshold, the requirement is met; otherwise, the requirement is not met, according to the DAC value required for every 1dB change in power and the error between the power value and the power setting value , modify the DAC value required when the power value is compensated to the set value, and send the corrected DAC value to the compensation circuit for readjustment until the expected compensation threshold is met.

Step 105: Store the DAC value after the power adjustment into the memory.

2. Scanning process

As shown in Figure 2, it is a flow chart of the scanning process of signal power characteristic compensation. When scanning, first send the frequency of the starting point and the scanning step to the CPLD. After receiving the starting frequency, the CPLD divides the frequency by 16MHz and rounds it up to obtain the storage location of the compensation data, and then calls the data from the memory chip. , added to the summing compensation circuit, so that the power at this point is compensated. At the same time, the CPLD will add step data to the initial frequency to find the frequency of the next scanning point. When the trigger signal is received, repeat the above calculation process, look for the compensation data at this point, until the entire frequency band scan is completed, and the software will resend the start frequency and step at the start of the second scan. The specific process is:

Step 201: the CPLD receives the start frequency and the step frequency sent from the vector network analyzer;

Step 202: Divide the current frequency by the step frequency, and round up to obtain the storage address of the DAC value that should be compensated for the frequency in the memory;

Step 203: read the stored DAC value and output it to the compensation circuit;

Step 204: the compensation circuit performs power compensation at the current frequency point according to the DAC value, and at the same time adds the step frequency to the current frequency to obtain the frequency value of the next scanning point;

Step 205: Determine whether a trigger signal is received, and if a trigger signal is received, repeat steps 2.2-2.4; otherwise, complete power compensation.

Embodiment two

This embodiment provides a signal power characteristic compensation device based on a vector network analyzer, and the device includes a vector network analyzer, a CPLD, a memory and a compensation circuit.

The vector network analyzer is connected with a power meter to collect the uncompensated power value of each frequency point, calculate the DAC value required when the uncompensated power value is compensated to the set value, and send it to the CPLD; the CPLD sends the DAC value into the compensation circuit; the compensation circuit converts the received DAC value into a voltage value through DA conversion for power adjustment; the memory stores the DAC value after power adjustment.

The vector network analyzer sends the start frequency and the step frequency to the CPLD; the CPLD divides the frequency of the scanning point by the step frequency, and rounds to obtain the storage address of the DAC value that should be compensated for by the frequency, The stored DAC value is read and output to the compensation circuit; the compensation circuit performs power compensation according to the received DAC value.

Wherein, the compensation circuit includes a 12-bit D/A converter and a corresponding peripheral operational amplifier. The DAC data is converted into a voltage through a D/A conversion chip, and then the voltage is output to the A voltage-controlled attenuator to adjust for power variations.

From the above description, it can be seen that the above-mentioned embodiments of the present application have achieved the following technical effects:

(1) The present invention adds a 12-bit DAC circuit in the compensation circuit, the power can be adjusted by setting a suitable DAC, and data storage and reading are changed to hardware implementation, which avoids the time of software calculation and improves the scanning speed , and there are more calibration points at the same time, which also improves the compensation accuracy;

(2) The present invention saves the compensation data in the hardware and realizes the power compensation function through the hardware, realizes the part of the software calculation through the hardware, reduces the calculation time, improves the scanning speed, and adopts a point every 16MHz to calibrate at the same time, when scanning When the point falls within this range, the compensation data is called directly from the memory, and the compensation accuracy is improved by increasing the number of calibration points.

Although the specific implementation of the present invention has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, those skilled in the art do not need to pay creative work Various modifications or variations that can be made are still within the protection scope of the present invention.

Claims (9)

1. A signal power characteristic compensation method based on vector network analyzer, is characterized in that, comprises the following steps: Step 1: Collect the uncompensated power value at each frequency point, calculate the DAC value required to compensate the uncompensated power value to the set power, adjust the power according to the DAC value, and store the DAC value in the memory; Step 2: Obtain the storage location of the DAC value required for current frequency compensation according to the current frequency and step frequency, read the DAC value from the memory, and output it to the compensation circuit for power compensation. 2. the signal power characteristic compensation method based on vector network analyzer according to claim 1, it is characterized in that, in described step 1, gather the uncompensated power value of each frequency point, calculate uncompensated power value compensation to set The DAC value required for setting the value, the power is adjusted according to the DAC value, and the DAC value is stored in the memory, including: Step 1.1: Divide the scanning range into multiple frequency bands at equal intervals, and calculate the adjustable power range of the compensation circuit; Step 1.2: Collect the uncompensated power values of each point in each frequency band, and calculate the DAC value required for each uncompensated power value to compensate to the set power; Step 1.3: The compensation circuit converts the DAC value into a voltage value for power adjustment according to the received DAC value, and obtains the adjusted power value; Step 1.4: Verify whether the adjusted power value meets the expected compensation threshold, if not, calculate the DAC value again, and return to step 1.3; if satisfied, go to step 1.5; Step 1.5: Store the DAC value into memory. 3. the signal power characteristic compensation method based on vector network analyzer according to claim 2, it is characterized in that, described scanning range is divided into a plurality of frequency bands at equal intervals, and calculates the adjustable power range of compensation circuit, comprises: Divide the entire scanning range into multiple frequency bands at equal intervals, and select the middle frequency point of each frequency band as the calibration reference; Set the DAC value to 0 and 4095 respectively, and read the minimum adjustable power value when the DAC value is 0; the maximum adjustable power value when the DAC value is 4095; A vector network analyzer determines a power setpoint; The power setting value is taken as the compensation target, and a certain error range deviated from the power setting value is taken as the compensation threshold. 4. The signal power characteristic compensation method based on the vector network analyzer according to claim 2, characterized in that, after calculating the adjustable power range, the DAC value required for every 1dB change of the power is also calculated. 5. the signal power characteristic compensation method based on vector network analyzer according to claim 2, is characterized in that, the uncompensated power value of each point in each frequency band of described collection, and calculates that each uncompensated power value is compensated to DAC values required when setting power, including: (1) The vector network analyzer collects the uncompensated power value at the current frequency point by connecting a power meter; (2) According to the DAC value required when the power changes by 1dB, calculate the DAC value required when the uncompensated power value is compensated to the set power; (3) Add a fixed frequency value on the basis of the current frequency to get the frequency of the next point, and repeat steps (1)-(2) until the frequency compensation of all points in the entire frequency range is obtained to the set power. DAC value. 6. the signal power characteristic compensation method based on vector network analyzer according to claim 2, is characterized in that, whether the power value after the verification adjustment reaches the power value threshold, comprising: When the error between the adjusted power value and the power setting value is less than the power value threshold, the requirement is met; otherwise, the requirement is not met, according to the DAC value required for every 1dB change in power and the error between the power value and the power setting value , modify the DAC value required when the power value is compensated to the set value, and send the corrected DAC value to the compensation circuit for readjustment until the expected compensation threshold is met. 7. the signal power characteristic compensation method based on vector network analyzer according to claim 1, is characterized in that, in described step 2, according to current frequency and step frequency, obtain the storage of the DAC value required for current frequency compensation position, read the DAC value from the memory, and output it to the compensation circuit for power compensation, including: Step 2.1: CPLD receives the start frequency and step frequency sent from the vector network analyzer; Step 2.2: Divide the current frequency by the step frequency and round to get the storage position of the DAC value required for compensation of the frequency in the memory; Step 2.3: Read the stored DAC value and output it to the compensation circuit; Step 2.4: The compensation circuit performs power compensation at the current frequency point according to the DAC value, and at the same time adds the step frequency to the current frequency to obtain the frequency value of the next scanning point; Step 2.5: Judging whether a trigger signal is received, if a trigger signal is received, repeat steps 2.2-2.4; otherwise, complete power compensation. 8. A signal power characteristic compensation device based on a vector network analyzer, characterized in that it comprises a vector network analyzer, CPLD, memory and compensation circuit; The vector network analyzer is connected with a power meter, which is used to collect the uncompensated power value of each frequency point, calculate the DAC value required when the uncompensated power value is compensated to the set value, and send it to the CPLD; The CPLD is used to send the DAC value to the compensation circuit; The compensation circuit is used to convert the received DAC value into a voltage value through DA conversion for power adjustment; The memory is used to store the DAC value after power adjustment. 9. the signal power characteristic compensation device based on vector network analyzer according to claim 8, is characterized in that, described vector network analyzer sends start frequency and step frequency to CPLD; The frequency is divided by the step frequency and rounded to obtain the storage address of the frequency that should be compensated for the DAC value in the memory, and the stored DAC value is read and output to the compensation circuit; the compensation circuit performs power based on the received DAC value compensate.