CN102571052B - Pulse automatic locking/unlocking circuit of insulated gate bipolar transistor (IGBT) in half-bridge mode - Google Patents
Pulse automatic locking/unlocking circuit of insulated gate bipolar transistor (IGBT) in half-bridge mode Download PDFInfo
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- CN102571052B CN102571052B CN201210013163.4A CN201210013163A CN102571052B CN 102571052 B CN102571052 B CN 102571052B CN 201210013163 A CN201210013163 A CN 201210013163A CN 102571052 B CN102571052 B CN 102571052B
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Abstract
The invention discloses a pulse automatic locking/unlocking circuit of an insulated gate bipolar transistor (IGBT) in a half-bridge mode. The pulse automatic locking/unlocking circuit is reliable in performance, practical, low in cost, high in response speed and particularly applicable to the occasions with low cost requirement. The pulse automatic locking/unlocking circuit of the IGBT in the half-bridge mode comprises a resistor-capacitor (RC)-based charging circuit, a 555-based charging and discharging control circuit, a comparison circuit and two level reversers, wherein an RC output end of the RC-based charging circuit is connected with a reverse input end of the comparison circuit and connected with a discharge end pin of the 555-based charging and discharging control circuit; and the two level reversers and the circuit are respectively connected with the input and output of a signal to provide a level required by the circuit.
Description
Technical field
The present invention relates to a kind of circuit, more specifically to the pulse automatic sealing package release circuit under a kind of IGBT half-bridge mode, belong to field of power electronics.
Background technology
IGBT module is widely used in field of power electronics, and is a kind of more expensive components and parts.At present a lot of two-tube IGBT drive circuits have 2 kinds of mode of operations, one is Direct Model, another kind is half-bridge mode, needing 2 pwm signals to control respectively it at the next two-tube IGBT of Direct Model opens and closes, just can control opening and closing of 2 pipes and only need 1 pwm signal to lead under half-bridge mode.Distance between control circuit and the power circuit distant time marquis of being separated by, being just connected of the pwm signal between power circuit and control circuit need to realize with guaranteed performance by optical fiber.In order to provide reliable Dead Time to save hardware cost (contrast Direct Model can be saved the optical fiber of half) to upper and lower bridge arm simultaneously, conventionally adopt half-bridge mode.But when IGBT breaks down need to block pwm signal time, use this pattern and an IGBT pipe is only had in the situation of a pwm control signal, realize it protected with regard to the rate of exchange and has been bothered.Conventional way is to increase by a road optical fiber to be connected to control end at present, for it sets up a special control signal.This way not only cost increases many and control underaction.
Summary of the invention
The present invention has well solved above-mentioned the deficiencies in the prior art and problem, and the release circuit of the pulse automatic sealing package under a kind of IGBT half-bridge mode is provided, and this circuit performance is reliable and practical, with low cost, and response speed is high, is particularly suitable for the occasion that low cost requires.
Technical scheme of the present invention is as follows:
Pulse automatic sealing package release circuit under IGBT half-bridge mode of the present invention, it includes 1 charging circuit, 1 charge-discharge control circuit, 1 comparison circuit and 2 level reverser based on 555 based on RC, the RC output of described RC charging circuit connects the reverse input end of comparison circuit the discharge end pin with 555 charge-discharge circuits, and 2 level inverter are connected with the input and output of signal the level that provides circuit required respectively with circuit.
Pulse automatic sealing package release circuit under IGBT half-bridge mode of the present invention, its further technical scheme is that described RC charging circuit comprises resistance R 33 and capacitor C 9; Described comparison circuit comprises comparator U5A and resistance R 31; 555 described charge-discharge control circuits comprise 555 chip U4 and capacitor C 18; 2 described inverters are U1E inverter and U1F inverter; Wherein one end of resistance R 33 is connected with the anode of 5V power supply, and the discharge end DISC of one end of the other end and capacitor C 19, the reverse input end of comparator U5A and 555 circuit links together; Hold and be connected to the reference of the other end of capacitor C 19 and 5V power supply; The CVOLT end of one end of comparator U5A positive input and capacitor C 18 and 555 charge-discharge control circuits links together; Be connected to the reference of the other end of capacitor C 18 and 5V power supply; Comparator U5A is 5V Power supply, and the TRIG end of the output of comparator U5A and resistance R 33 one end and 555 charge-discharge control circuits links together; The other end of resistance R 33 is connected with 5V power positive end; The input of described inverter U1E connects pwm signal, and its output is connected with the reset terminal RST of 555 charge-discharge control circuits; 555 charge-discharge control circuits and 2 inverters are all 5V power supply; The THR end of 555 charge-discharge control circuits is directly connected with the anode of 5V power supply; The output of 555 charge-discharge control circuits is connected with the input of inverter U1F; The output of U1F is the output of automatic sealing package lock signal.
Pulse automatic sealing package release circuit under IGBT half-bridge mode of the present invention, its further technical scheme be that described resistance R 33 is 1.82K ohm; The electric capacity that described capacitor C 19 is 1uF; Described comparator U5A model is LM339D; The electric capacity that described capacitor C 18 is 0.1uF; The model of described U1E is SN74LS04D.
The course of work of the whole circuit of the present invention is as follows:
Under normal circumstances: pwm signal is that frequency is fixed, the signal that pulse duration is variable.In the time there is high level pulse in PWM, inverter U1E output low level, now 555 circuit U 4 reset, the discharge end DISC conducting of U4, capacitor C 19 is held and is discharged by DISC; U4 is output as low level simultaneously, is high level through inverter locking signal, and IGBT is de-preservation state.In the time that pulse appears in PWM, inverter U1E exports high level, and now the THR terminal voltage of 555 circuit is supply voltage, and the CVOLT terminal voltage of 555 circuit is 2/3rds times of supply voltages; 5V power supply charges to capacitor C 19 by resistance R 33; Voltage within the time of the low pulse of PWM in capacitor C 19 is less than 2/3rds times of supply voltages, is less than CVOLT terminal voltage, and relatively its U5A is output as high level, and TRIG terminal voltage is greater than 1/3rd times of supply voltages; Now THR end is greater than 2/3rds times of supply voltages; The discharge end DISC conducting of 555 circuit U 4, capacitor C 19 is held and is discharged by DISC; Simultaneously U4 is output as low level, is high level through inverter locking signal, and to appoint be so de-preservation state to IGBT.
In the time breaking down: pwm signal is lasting low level.Inverter U1E exports high level, and now the THR terminal voltage of 555 circuit is supply voltage, and the CVOLT terminal voltage of 555 circuit is 2/3rds times of supply voltages; 5V power supply charges to capacitor C 19 by resistance R 33; At PWM, for continuing in low level situation, the voltage in capacitor C 19 will be greater than 2/3rds times of supply voltages, is greater than CVOLT terminal voltage, and relatively its U5A is output as low level, and TRIG terminal voltage is less than 1/3rd times of supply voltages; Now THR end is greater than 2/3rds times of supply voltages; The discharge end DISC cut-off of 555 circuit U 4, U4 is output as high level simultaneously, is low level through inverter locking signal, and IGBT is lock-out state.Situation reopen pwm signal after fault disappears time and the state of normal condition are the same.
Brief description of the drawings
Fig. 1 is electrical block diagram of the present invention
Embodiment
Below in conjunction with accompanying drawing, the technology of the present invention content is explained:
As shown in Figure 1, pulse automatic sealing package release circuit under IGBT half-bridge mode of the present invention, it includes 1 charging circuit, 1 charge-discharge control circuit, 1 comparison circuit and 2 level reverser based on 555 based on RC, the RC output of described RC charging circuit connects the reverse input end of comparison circuit the discharge end pin with 555 charge-discharge circuits, and 2 level inverter are connected with the input and output of signal the level that provides circuit required respectively with circuit.Wherein said RC charging circuit comprises resistance R 33 and capacitor C 9; Described comparison circuit comprises comparator U5A and resistance R 31; 555 described charge-discharge control circuits comprise 555 chip U4 and capacitor C 18; 2 described inverters are U1E inverter and U1F inverter; Wherein one end of resistance R 33 is connected with the anode of 5V power supply, and the discharge end DISC of one end of the other end and capacitor C 19, the reverse input end of comparator U5A and 555 circuit links together; Hold and be connected to the reference of the other end of capacitor C 19 and 5V power supply; The CVOLT end of one end of comparator U5A positive input and capacitor C 18 and 555 charge-discharge control circuits links together; Be connected to the reference of the other end of capacitor C 18 and 5V power supply; Comparator U5A is 5V Power supply, and the TRIG end of the output of comparator U5A and resistance R 33 one end and 555 charge-discharge control circuits links together; The other end of resistance R 33 is connected with 5V power positive end; The input of described inverter U1E connects pwm signal, and its output is connected with the reset terminal RST of 555 charge-discharge control circuits; 555 charge-discharge control circuits and 2 inverters are all 5V power supply; The THR end of 555 charge-discharge control circuits is directly connected with the anode of 5V power supply; The output of 555 charge-discharge control circuits is connected with the input of inverter U1F; The output of U1F is the output of automatic sealing package lock signal.Wherein said resistance R 33 is 1.82K ohm; The electric capacity that described capacitor C 19 is 1uF; Described comparator U5A model is LM339D; The electric capacity that described capacitor C 18 is 0.1uF; The model of described U1E is SN74LS04D.
Claims (3)
1. the pulse automatic sealing package release circuit under an IGBT half-bridge mode, it is characterized in that including 1 charging circuit, 1 charge-discharge control circuit, 1 comparison circuit and 2 level inverter logical AND circuit based on 555 based on RC, the RC output of the described charging circuit based on RC connects the reverse input end of comparison circuit and is connected with the discharge end pin of the charge-discharge control circuit based on 555, and 2 level inverter logical AND circuit are connected with the input and output of pwm signal the level that provides circuit required respectively; Described comparison circuit comprises comparator U5A and resistance R 31; Comparator U5A positive input links together with the CVOLT end of the charge-discharge control circuit based on 555; The output of comparator U5A links together with the TRIG end of the charge-discharge control circuit based on 555.
2. the pulse automatic sealing package release circuit under IGBT half-bridge mode according to claim 1, is characterized in that the described charging circuit based on RC comprises resistance R 33 and capacitor C 9; The described charge-discharge control circuit based on 555 comprises 555 chip U4 and capacitor C 18; 2 described inverters are U1E inverter and U1F inverter; Wherein one end of resistance R 33 is connected with the anode of 5V power supply, and the discharge end DISC of one end of the other end and capacitor C 19, the reverse input end of comparator U5A and the charge-discharge control circuit based on 555 links together; Hold and be connected to the reference of the other end of capacitor C 19 and 5V power supply; One end of comparator U5A positive input and capacitor C 18 links together; Hold and be connected to the reference of the other end of capacitor C 18 and 5V power supply; Comparator U5A is by 5V Power supply, and the output of comparator U5A and resistance R 31 one end link together; The other end of resistance R 31 is connected with 5V power positive end; The input of described U1E inverter connects pwm signal, and its output is connected with the reset terminal RST of the charge-discharge control circuit based on 555; Charge-discharge control circuit based on 555 and 2 inverters are all by 5V Power supply; The THR end of the charge-discharge control circuit based on 555 is directly connected with the anode of 5V power supply; The output of the charge-discharge control circuit based on 555 is connected with the input of U1F inverter; The output of U1F inverter is the output of automatic sealing package lock signal.
3. the pulse automatic sealing package release circuit under IGBT half-bridge mode according to claim 2, is characterized in that described resistance R 33 is for 1.82K ohm; The electric capacity that described capacitor C 19 is 1uF; Described comparator U5A model is LM339D; The electric capacity that described capacitor C 18 is 0.1uF; The model of described U1E is SN74LS04D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210013163.4A CN102571052B (en) | 2012-01-17 | 2012-01-17 | Pulse automatic locking/unlocking circuit of insulated gate bipolar transistor (IGBT) in half-bridge mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210013163.4A CN102571052B (en) | 2012-01-17 | 2012-01-17 | Pulse automatic locking/unlocking circuit of insulated gate bipolar transistor (IGBT) in half-bridge mode |
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| Publication Number | Publication Date |
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| CN102571052A CN102571052A (en) | 2012-07-11 |
| CN102571052B true CN102571052B (en) | 2014-07-09 |
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| CN201210013163.4A Active CN102571052B (en) | 2012-01-17 | 2012-01-17 | Pulse automatic locking/unlocking circuit of insulated gate bipolar transistor (IGBT) in half-bridge mode |
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| CN106786853A (en) * | 2016-12-02 | 2017-05-31 | 杭州创睿新能源科技有限公司 | A kind of charging pile power down release circuit |
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| JP5487746B2 (en) * | 2009-06-15 | 2014-05-07 | 富士電機株式会社 | IGBT overcurrent protection circuit with reverse breakdown voltage |
| CN102185549B (en) * | 2011-04-14 | 2012-06-20 | 江苏浩峰汽车附件有限公司 | Multifunctional speed-regulation and light-modulation PWM (Pulse-Width Modulation) controller |
| CN202094613U (en) * | 2011-06-02 | 2011-12-28 | 深圳市汇川技术股份有限公司 | IGBT current foldback circuit |
| CN202435364U (en) * | 2012-01-17 | 2012-09-12 | 南京亚派科技实业有限公司 | Automatic pulse blocking and deblocking circuit in insulated gate bipolar transistor (IGBT) half-bridge mode |
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