CN102569472B - Silicon photocell - Google Patents

Abstract

The invention discloses a silicon photocell, comprising a backside P<+> ohmic contact region, a P<-> base region and an N<+> emission region, wherein a pin structure is formed by the backside P<+> ohmic contact region, the P<-> base region and the N<+> emission region. The silicon photocell is characterized by further comprising a medium buried layer, wherein the medium buried layer is located in the P<-> base region and outside an exhaustion region; and the P<-> base region is not separated by the medium buried layer. As for the silicon photocell disclosed by the invention, an inner reflection mechanism is formed by introducing a buried layer medium into the base region of the photocell and the introduced medium buried layer has certain capability of reflecting incident light, so that more light illumination can be received by the position with a high photocell collecting possibility and more photons can be absorbed; and therefore, a higher photo-generated current can be obtained under the condition that the thickness of the photocell is not increased and the conversion efficiency is effectively improved.

Description

A kind of silicon photocell

Technical field

The invention belongs to technical field of electronic components, be specifically related to a kind of design of silicon photocell.

Background technology

Photocell is to utilize photovoltaic effect directly luminous energy to be transformed into the device of electric energy, is called again solar cell, and at present, most widely used, the most rising is silicon photocell.Along with the developing rapidly of microminiature semiconductor inverter, photronic application is more general in recent years.

Silica-based battery comprises three kinds of polysilicon, monocrystalline silicon and amorphous silicon batteries.Monocrystalline silicon photocell technique is closely ripe now, in battery is made, improves photoelectric conversion efficiency and is summed up the mainly improvement based on following three aspects: 1, improve battery material performance and minority carrier life time; 2, improve the technical process that battery is developed; 3, improve battery structure design.In aspect three, the most flexible, with fastest developing speed to improve battery structure again.

Existing silicon photocell for light can be coupled in semiconductor as much as possible, has following several measure in structure aspects at present: with effective one or more layers anti-reflective film, reduce the light reflection of battery upper surface.Upper surface suede structure and afterwards improved micro groove structure not only can reduce battery upper surface reflection of light is lost, and the angle that made to enter into refract light deflection in silicon, have been equivalent to increase the light path of photon and the probability being absorbed by semiconductor.By cell backside polishing and steam metal that luminous reflectanc is strong (as gold, copper, aluminium), now back of the body gold has played the effect of reflecting interface, " light falls into rule " penetrated with front suede structure or micro groove structure and can be formed to this back of the body golden hair makes light at inside battery generation multiple reflections, and this structural manufacturing process is simple, and cost is lower, but the photogenerated current of its acquisition is lower, conversion efficiency is not high.

Summary of the invention

The object of the invention is in order to solve the photogenerated current that existing silicon photocell obtains lowlyer, the defect that conversion efficiency is not high, has proposed a kind of silicon photocell.

Technical scheme of the present invention is: a kind of silicon photocell, comprise: P+ ohmic contact regions, the back side, P-base and N+ emitter region, P+ ohmic contact regions, the described back side, P-base and N+ emitter region form pin structure, it is characterized in that, also comprise dielectric buried layer, it is inner that described dielectric buried layer is positioned at P-base, and depletion region is outside, and dielectric buried layer does not cut off P-base.

Further, described silicon photocell also comprises the antireflection layer that is positioned at silicon photocell top, and described antireflection layer is covered on N+ emitter region.

Further, described dielectric buried layer is specially silicon dioxide.

Further, the thickness of described dielectric buried layer is

wherein, λ is lambda1-wavelength, and n is dielectric buried layer refractive index, and β is the incidence angle that light enters dielectric buried layer.

Beneficial effect of the present invention: the silicon photocell that the present invention proposes forms internal reflection mechanism by introduce buried regions medium in photocell base, the dielectric buried layer of introducing has certain ability reflecting the incident light, make photocell Hu always collect the position that probability is high and can receive more illumination, absorb more photon, thereby can under the condition that does not increase cell thickness, obtain high photogenerated current, conversion efficiency is effectively promoted.

Accompanying drawing explanation

Fig. 1 is the structure chart of silicon photocell embodiment mono-of the present invention.

Fig. 2 is the buried regions light reflection principle schematic diagram of silicon photocell embodiment mono-local A of the present invention.

Fig. 3 is the structure chart of silicon photocell embodiment bis-of the present invention.

Fig. 4 is the buried regions light reflection schematic diagram of silicon photocell embodiment bis-local A ' of the present invention.

Fig. 5 is silicon photocell position and the graph of relation of collecting probability.

Fig. 6 take a kind of buried regions of silicon dioxide during as buried regions medium to make flow chart.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment, the invention will be further elaborated.

Embodiment mono-:

According to a kind of embodiment of silicon photocell of the present invention as shown in the embodiment mono-of Fig. 1.Comprise: 103HeN+ emitter region, 105,P-base, P+ ohmic contact regions, the back side 102,103HeN+ emitter region, 105,P-base, P+ ohmic contact regions, the described back side 102 forms pin structure, also comprise dielectric buried layer 104, described dielectric buried layer 104 is positioned at 103 inside, P-base, 107 outsides, depletion region, and dielectric buried layer 103 does not cut off P-base 103.

Here, 107 regions are 103 formed depletion regions, 102HeP-base, N+ emitter region.

Here, silicon photocell also comprises the antireflection layer 101 that is positioned at silicon photocell top, and antireflection layer 101 is covered on N+ emitter region 102.

Here, dielectric buried layer 103 can be that any and silicon refractive index difference are large and can form the solid matter of good interface state with silicon in theory, such as silicon dioxide, carborundum and silicon nitride.The concrete silicon dioxide that adopts in the present embodiment.

The thickness of dielectric buried layer 103 depends on incident light wavelength, and whether the refractive index of buried regions and surface adopt suede structure, and choosing of buried regions thickness is in order to obtain the maximum reflectivity of the light of interface specific wavelength.As a kind of preferred version, the thickness of dielectric buried layer 103 is

wherein, λ is lambda1-wavelength, and n is dielectric buried layer refractive index, and β is the incidence angle that light enters dielectric buried layer.In the present embodiment, β=0, the thickness of dielectric buried layer 103 is

nsio2 is the refractive index of silicon dioxide.

In the embodiment shown in fig. 1,105 as ohmic contact regions, and back metal 106 and front electrode 108 have formed two electrodes of silicon photocell, and 109 is positive heavily doped region.

N+ emitter region 102, P+ ohmic contact regions, the 103He back side, P-base 105 has formed the basic pin structure of silicon photocell, dielectric buried layer 104 is positioned at 103 middle parts, P-base for introducing reflex mechanism, positive heavily doped region 109 junction depths are greater than N+ emitter region for reducing contact resistance, and have inner passivation.

The position in pin running down of battery district and the thickness of battery are depended in the position of dielectric buried layer 103, and choosing of buried regions position is in order to make the buried regions the highest depletion region of collection probability of trying one's best, thereby makes light can reflex to as far as possible depletion region.

The width W of dielectric buried layer 103 depends on the requirement of silicon photocell equivalent series resistance, thereby in general after photocell attenuate, can suitably improve the photronic i of pin district concentration reduction equivalent series resistance, but the larger equivalent series resistance of buried regions width is higher.

Dielectric buried layer 103 shown in Fig. 1 is symmetrical two, in concrete application, can select according to the actual requirements number, position and the width of dielectric buried layer.

Antireflection layer 101 can consist of single or multiple lift antireflective coating, and object is that the value of reflectivity is relevant with the refractive index of antireflective coating and thickness in order to make the light reflectivity of the non-shading region of battery surface for minimum.The junction depth of N+ emitter region 102 is about 3um, and doping content is about 10 ¹⁷to 10 ¹⁸cm ^-3, P-base 103 thickness are about 100um, and doping content is about 10 ¹⁴to 10 ¹⁵cm ^-3, it is main contributions regions of photogenerated current that 103 interfaces, 102YuP-base, N+ emitter region have formed 107， depletion region, depletion region 107.P+ ohmic contact regions, the back side 105 thickness are about 1 to 2um, and doping is about 10 ¹⁸cm ^-3p+ ohmic contact regions, the 103He back side, P-base 105 has formed height junction structure, this structure has played the effect of back of the body electric field (BSF), the reflection of back of the body electric field energy is towards back side diffusion electronics, make electronics have certain probability to get back to depletion region photogenerated current is produced to contribution, improved photronic efficiency, the photocell especially little for thickness, minority carrier life time is large, back of the body electric field action is more remarkable.Back metal 106 is generally copper or aluminium, and thickness is about 1um.Back metal has played the effect of reflecting interface, and " light falls into rule " penetrated with Facad structure and can be formed to this back of the body golden hair makes light at inside battery generation multiple reflections, obtains high photogenerated current under the condition that does not increase cell thickness.Top layer heavily doped region 109 is positioned under top layer electrode 108, and top layer heavily doped region 109 doping contents are about 10 ²⁰cm ^-3junction depth is about 4um, and top layer electrode 108 is aluminium electrode, and the high concentration of top layer heavily doped region 109 has reduced the resistance of shading region, and has formed inner passivation, is that the surface recombination of few son reduces to some extent.

Specific works principle is as follows: collecting probability is in photocell theory, to describe the spatial parameter of photo-generated carrier, and it is defined as: on average, and a photo-generated carrier, the probability that photocell short circuit current is done to contribute.Because the position that photo-generated carrier produces in battery is different, the probability finally photoelectric current being contributed through different paths is also just different, and it is the function of a position.According to definition, through deriving and measuring and calculating, collecting probability, be that generation point along with photo-generated carrier leaves depletion region edge and reduces exponentially along the increase of distance.

The collection probability of common pin battery and the relation of position are as shown in Figure 5, significantly, the collection probability in region, depletion region is the highest, in order to make more luminous energy concentrate on depletion region, the present invention proposes the reflex mechanism that increases interior media buried regions (dielectric buried layer of the present embodiment is silicon dioxide) thereby introduce inside, base.

Fig. 2 is the partial schematic diagram of A dotted portion in Fig. 1, uses the optical characteristics that this part illustrates dielectric buried layer structure.

With reference to figure 2, light impinges perpendicularly on behind photocell base 103, pass through silicon dioxide buried regions 104, and now base 103 and buried regions 104 have formed the membrane structure of " silicon-silicon dioxide-silicon ".Can there is reflection to a certain degree in the surface of different medium film, the size of reflectivity is relevant with thin layer of silicon dioxide thickness with lambda1-wavelength, make silicon-silicon dioxide interface obtain maximum reflectivity and need meet following equation:

required maximum reflectivity R is: wherein, n _sio2and n _sibe respectively the refractive index of silicon dioxide and silicon, d is the thickness of silicon dioxide buried regions 104, and λ is incident light wavelength.

Through calculating that the maximum reflectivity that silicon dioxide buried regions can reach is in theory about 47.81%.Reflectivity for other dielectric buried layer only calculates and need change the refractive index of above formula silicon dioxide into required medium refraction index in addition, by formula, can find out that the buried regions that 3.42 of refractive index value and silicon differs larger medium composition has higher reflectivity, but still will consider the interfacial characteristics of buried regions and silicon and the compatibility of technique during specific design.

The position of dielectric buried layer is also one of factor affecting conversion efficiency of the present invention, require in theory buried regions more to approach depletion region effect better, once but buried regions region is overlapping with depletion region, make the photo-generated carrier contribution area loss of depletion region, efficiency reduces on the contrary, and general suitable position should make buried regions be positioned at 3-5um place, below, depletion region.

The width W of dielectric buried layer is the key factor that affects photocell parasitic series resistance, and buried regions is wider, connects the upper and lower silicon channel part of buried regions narrower in base, and resistance is larger, and reflection region is also larger.In the process of light incident, because buried regions has reflected about 45% light to collecting the higher region of probability, the light that enters buried regions below will be very little on the impact of photogenerated current, therefore photocell of the present invention can be thinner than general silicon photocell under equal index, the doping of base is also higher.The raising of doping has reduced the impact of buried regions width on parasitic series resistance to a certain extent.In addition, thin battery makes P+, and the back surface field effect that P-forms is more remarkable, and this point contributes to the increase of photogenerated current.

Embodiment bis-:

According to a kind of embodiment of silicon photocell of the present invention as shown in the embodiment bis-of Fig. 3.Fig. 3 is that photronic silicon face corrodes formed suede structure figure through alkaline solution, intercepts its local A ' as shown in Figure 4.Be different from embodiment mono-, from air, the light of incident is being n through surface refractive index ₁ antireflective coating 201 after there is refraction, wherein the angle of light of matte is α, according to the law of refraction, can calculate the value that bright dipping enters the incidence angle β of dielectric buried layer 204, now calculates the thickness d of buried regions dieletric reflection rate when maximum and should carry out according to following formula:

$n_{\mathrm{sio}2}d=\frac{\mathrm{\&lambda;}}{4*\cos \mathrm{\&beta;}}$

Wherein, n _sio2for the refractive index of silicon dioxide, d is the thickness of silicon dioxide buried regions 204, and λ is incident light wavelength, and β is the incidence angle that light enters dielectric buried layer.

Fig. 4 is the partial schematic diagram of A ' dotted portion in Fig. 3, uses the optical characteristics that this part illustrates dielectric buried layer structure, and concrete principle, process are similar to embodiment mono-, at this, are not described in detail.

In order to realize, embodiment mono-and embodiment bis-are described usings silicon dioxide during as buried regions medium silicon photocell, need on the basis in conventional photocell technique, introduce the bonding techniques of location oxidation of silicon process and SOI, specifically can be with reference to a kind of buried regions manufacture method as shown in Figure 6, concrete steps are as follows:

1, in the doping of P type, be about 10 ¹⁴cm ^-3single crystalline substrate 612 on the layer of oxide layer 611 of growing;

2, deposit one deck nitride 613 in oxide layer 611;

3, carry out the etching of nitride 613, the part that exposes oxide layer is nitride window;

4, carry out LOCOS oxidation (there will be the beak phenomenon shown in 614);

5, remove nitride, and polishing is until silicon is exposed in non-nitride window district;

6, the bonding techniques that utilizes SOI is by previous step gained silicon chip and another piece identical wafer bonding that adulterates;

7, on previous step gained silicon chip, spread other processing steps such as injection.

Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not depart from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (2)

1. a silicon photocell, comprise: P+ ohmic contact regions, the back side, P-base and N+ emitter region, P+ ohmic contact regions, the described back side, P-base and N+ emitter region form pin structure, it is characterized in that, also comprise dielectric buried layer, it is inner that described dielectric buried layer is positioned at P-base, and depletion region is outside, and described dielectric buried layer is positioned at 3-5um place, below, depletion region; And dielectric buried layer does not cut off P-base; Described dielectric buried layer is specially silicon dioxide; The thickness of described dielectric buried layer is

wherein, λ is lambda1-wavelength, and n is dielectric buried layer refractive index, and β is the incidence angle that light enters dielectric buried layer.

2. silicon photocell according to claim 1, is characterized in that, described silicon photocell also comprises the antireflection layer that is positioned at silicon photocell top, and described antireflection layer is covered on N+ emitter region.

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