CN102569409B - Double-layer isolation longitudinal stacked semiconductor nanowire MOSFET (Metal Oxide Semiconductor Field Effect Transistor) - Google Patents
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Abstract
The invention provides a double-layer isolation longitudinal stacked semiconductor nanowire MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The double-layer isolation longitudinal stacked semiconductor nanowire MOSFET comprises a semiconductor substrate, a first semiconductor nanowire MOSFET, a second semiconductor nanowire MOSFET, an isolation medium layer and a buried oxide layer, wherein the first semiconductor nanowire MOSFET further comprises a first semiconductor nanowire group and a first gate oxide layer; the second semiconductor nanowire MOSFET further comprises a second semiconductor nanowire group and a second gate oxide layer; the isolation medium layer is arranged between the first semiconductor nanowire MOSFET and the second semiconductor nanowire MOSFET; and the buried oxide layer is arranged between the first semiconductor nanowire MOSFET and the semiconductor substrate. According to the invention, by using the structural design that the first semiconductor nanowire MOSFET has the longitudinal stacked first semiconductor nanowire group and the second semiconductor nanowire MOSFET has the longitudinal stacked second semiconductor nanowire group, the process can be debugged in a completely independent way and high integration level of the device is obtained. At the same time, by using the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention, the electrical property of the field effect transistor is improved and the device current driving capability is improved in multiples; and the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention is suitable for the technical field of advanced nanodevices.
Description
Technical field
The present invention relates to semiconductor field effect transistor technical field, relate in particular to a kind of double-deck isolation vertical stack formula semiconductor nanowires MOSFET.
Background technology
By dwindling transistorized size, improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in microelectronics industry development always.Current, the long 20nm that approached of physical gate of field-effect transistor, gate medium also only has several oxygen atom bed thickness, by dwindling the size of conventional field effect transistor, improve performance and faced some difficulties, this is mainly because short-channel effect and grid leakage current degenerate transistorized switch performance under small size.
Nano-wire field effect transistor (NWFET, Nanowire MOSFET) is expected to address this problem.On the one hand, little channel thickness and width make the grid of NWFET closer to the various piece of raceway groove, contribute to the enhancing of transistor gate modulation capability, and they mostly adopt and enclose grid structure, grid is modulated raceway groove from multiple directions, further enhanced modulation ability, improves Sub-Threshold Characteristic.Therefore, NWFET can suppress short-channel effect well, and transistor size is further dwindled.On the other hand, NWFET utilizes the rill road of self and encloses grid Structure Improvement grid modulation power and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced the discrete distribution of impurity and Coulomb scattering in raceway groove.For 1-dimention nano wire channel, due to quantum limitation effect, in raceway groove charge carrier away from surface distributed, therefore carrier transport be subject to surface scattering and channel laterally electric field influence little, can obtain higher mobility.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Due to Si material and technique, in semi-conductor industry, occupy dominant position, compare with other materials, the making of silicon nanowires field-effect transistor (SiNWFET) more easily with current process compatible.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.Making for Si nano wire, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technique, the latter is gas-liquid-solid (VLS) growth mechanism based on metal catalytic mainly, usings catalyst granules as nucleating point in growth course.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of SiNWFET due to its randomness, and therefore the SiNW in current silicon nanowires field-effect transistor is prepared by top-down process route.Meanwhile, existing nano-wire field effect transistor also has the defect of himself.
Refer to Fig. 4 (a), Fig. 4 (b), Fig. 4 (c), Fig. 4 (a), Fig. 4 (b), Fig. 4 (c) are the structural representation of the disclosed a kind of all-around-gate CMOS field effect transistor of US Patent No. 20110254058A1.Described all-around-gate CMOS field effect transistor is round by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Fig. 5 (a), Fig. 5 (b), Fig. 5 (c), Fig. 5 (a), Fig. 5 (b), Fig. 5 (c) are the structural representation of the disclosed a kind of mixed material accumulation type cylinder all-around-gate CMOS field effect transistor of US Patent No. 20110254099A1.Described all-around-gate CMOS field effect transistor is round by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Fig. 6 (a), Fig. 6 (b), Fig. 6 (c), Fig. 6 (a), Fig. 6 (b), Fig. 6 (c) are the structural representation of the disclosed a kind of composite material inversion mode cylinder all-around-gate CMOS field effect transistor of US Patent No. 20110254101A1.Described all-around-gate CMOS field effect transistor is round by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Fig. 7 (a), Fig. 7 (b), Fig. 7 (c), Fig. 7 (a), Fig. 7 (b), Fig. 7 (c) are the structural representation of the disclosed a kind of hybrid crystal orientation accumulation type total surrounding grid CMOS field-effect transistor of US Patent No. 20110254013A1.Described all-around-gate CMOS field effect transistor is racetrack by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Fig. 8 (a), Fig. 8 (b), Fig. 8 (c), Fig. 8 (a), Fig. 8 (b), Fig. 8 (c) are the structural representation of the disclosed a kind of hybrid orientation inversion mode all-around-gate CMOS field-effect transistor of US Patent No. 20110254102A1.Described all-around-gate CMOS field effect transistor is racetrack by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Fig. 9 (a), Fig. 9 (b), Fig. 9 (c), Fig. 9 (a), Fig. 9 (b), Fig. 9 (c) are the transistorized structural representation of the disclosed a kind of mixed material accumulation type total surrounding grid CMOS field effect of US Patent No. 20110254100A1.Described all-around-gate CMOS field effect transistor is racetrack by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
Refer to Figure 10 (a), Figure 10 (b), Figure 10 (c), Figure 10 (a), Figure 10 (b), Figure 10 (c) are the transistorized structural representation of the disclosed a kind of composite material inversion mode all-around-gate CMOS field effect of US Patent No. 20110248354A1.Described all-around-gate CMOS field effect transistor is racetrack by full raceway groove 301 ', the 401 ' cross section surrounding, gate regions 500 '.There is following defect in described all-around-gate CMOS field effect transistor structure: (1) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction; (2) nmos area 300 ' and PMOS district 400 ' share same gate regions 500 ', cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS; (3) realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large.
In addition, when guaranteeing high device integration density, how to improve device current driving force is also this area institute problem demanding prompt solution always.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in, and active research improvement, so there has been the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET.
Summary of the invention
The present invention be directed in prior art, existing semiconductor nanowires MOSFET cannot realize NMOS and PMOS isolating construction, cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS, and realize and for NMOS and PMOS, to carry out respectively source to leak the technology difficulty of Implantation large, and device current driving force limits by semiconductor nano cross-sectional area, cannot further increase the defects such as device current driving ability provides a kind of double-deck isolation vertical stack formula semiconductor nanowires MOSFET.
In order to address the above problem, the invention provides a kind of double-deck isolation vertical stack formula semiconductor nanowires MOSFET, comprising:
Semiconductor substrate;
The first semiconductor nanowires MOSFET, there is the first source area, the first drain region and first grid polar region, and be formed in described Semiconductor substrate, described the first semiconductor nanowires MOSFET further comprise laterally through described first grid polar region and be arranged on described the first source area and described the first drain region between the first semiconductor nano group, described the first semiconductor nanowires group comprises the first semiconductor nanowires that is the setting of vertical stack formula, described the first semiconductor nanowires MOSFET also comprises and encircles the first semiconductor nanowires outside the first grid oxide layer between described the first semiconductor nanowires and described first grid polar region that is arranged on described the first semiconductor nanowires group,
The second semiconductor nanowires MOSFET, there is the second source area, the second drain region and second gate polar region, and be formed in described Semiconductor substrate, described the second semiconductor nanowires MOSFET further comprise laterally through described second gate polar region and be arranged on described the second source area and described the second drain region between the second semiconductor nano group, described the second semiconductor nanowires group comprises the second semiconductor nanowires that is the setting of vertical stack formula, described the second semiconductor nanowires MOSFET also comprises and encircles the second semiconductor nanowires outside the second gate oxide layer between described the second semiconductor nanowires and described second gate polar region that is arranged on described the second semiconductor nanowires group,
Spacer medium layer, is arranged between described the first semiconductor nanowires MOSFET and described the second semiconductor nanowires MOSFET;
Oxygen buried layer, is arranged between described the first semiconductor nanowires MOSFET and described Semiconductor substrate;
The first insulating medium layer, is arranged between the first source area, the first drain region and the first grid polar region of described the first semiconductor nanowires MOSFET;
The second insulating medium layer, is arranged between the second source area, the second drain region and the second gate polar region of described the second semiconductor nanowires MOSFET;
The 3rd insulating medium layer, is arranged between between described spacer medium layer and described oxygen buried layer and be positioned at described the first semiconductor nanowires MOSFET mono-side and be connected with described the first source area, the first drain region and first grid polar region;
The 4th insulating medium layer, is towards arranging and being connected with described the second source area, the second drain region and second gate polar region with described the 3rd insulating medium layer;
The first conductive layer, is separately positioned between described spacer medium layer and described the first source area, the first drain region and first grid polar region; And,
The second conductive layer, is separately positioned on described spacer medium layer one side of differing from of the second source area, the second drain region and second gate polar region.
Described the first semiconductor nanowires group comprises a plurality of the first semiconductor nanowires that vertical stack formula arranges that are, and described the second semiconductor nanowires group comprises a plurality of the second semiconductor nanowires that vertical stack formula arranges that are.Only enumerate in the present invention the first semiconductor nanowires group and comprise that 3 are the first semiconductor nanowires that vertical stack formula arranges, described the second semiconductor nanowires group comprises that 3 the second semiconductor nanowires that are the setting of vertical stack formula are example.
Optionally, described the first semiconductor nanowires MOSFET is NMOSFET, and described the second semiconductor nanowires MOSFET is PMOSFET.
Optionally, described the first semiconductor nanowires MOSFET is PMOSFET, and described the second semiconductor nanowires MOSFET is NMOSFET.
Optionally, described the first semiconductor nanowires group and described the second semiconductor nanowires group are spatially stacked, and have respectively the cross section structure of circle, horizontal track type or longitudinal racetrack.
Optionally, described the first semiconductor nanowires MOSFET draws electrode by the 4th insulating medium layer from the first conductive layer, forms respectively the first source electrode, the first drain electrode and first grid.
Optionally, described the second semiconductor nanowires MOSFET draws electrode by the second conductive layer being positioned on the second source area, the second drain region and second gate polar region, forms respectively the second source electrode, the second drain electrode and second grid.
Optionally, the width perpendicular to described the first semiconductor nanowires of described the first source area, the first drain region is greater than the diameter of the first semiconductor nanowires, and the width perpendicular to the second semiconductor nanowires of described the second source area, the second drain region is greater than the diameter of the second semiconductor nanowires.
In sum, the present invention adopts the first semiconductor nanowires MOSFET to have the structural design that vertical stack formula the first semiconductor nanowires group and the second semiconductor nanowires MOSFET have vertical stack formula the second semiconductor nanowires group can completely independently carry out process debugging, and device integrated level is high.Improve the electric property of field-effect transistor simultaneously, increase at double device current driving force, and be applicable to forward position nano-device technical field.
Accompanying drawing explanation
Fig. 1 (a) is the plan structure schematic diagram of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET;
Fig. 1 (b) is depicted as Fig. 1 (a) along the sectional structure schematic diagram of X-X ' direction;
Fig. 1 (c) is depicted as Fig. 1 (a) along the sectional structure schematic diagram of Y-Y ' direction;
Fig. 2 is the perspective view of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET;
Fig. 3 is that the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET is through the perspective view of the formed complete field-effect transistor of follow-up semiconductor preparing process;
The structural representation that Fig. 4 (a), Fig. 4 (b), Fig. 4 (c) are existing MOSFET;
The structural representation that Fig. 5 (a), Fig. 5 (b), Fig. 5 (c) are existing MOSFET;
The structural representation that Fig. 6 (a), Fig. 6 (b), Fig. 6 (c) are existing MOSFET;
The structural representation that Fig. 7 (a), Fig. 7 (b), Fig. 7 (c) are existing MOSFET;
The structural representation that Fig. 8 (a), Fig. 8 (b), Fig. 8 (c) are existing MOSFET;
The structural representation that Fig. 9 (a), Fig. 9 (b), Fig. 9 (c) are existing MOSFET;
The structural representation that Figure 10 (a), Figure 10 (b), Figure 10 (c) are existing MOSFET.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.Wherein, described the first semiconductor nanowires group can comprise a plurality of the first semiconductor nanowires that vertical stack formula arranges that are, in embodiment and accompanying drawing, take 3 as example, described the second semiconductor nanowires group can comprise a plurality of the second semiconductor nanowires that vertical stack formula arranges that are, and take 3 as example in embodiment and accompanying drawing.
Refer to Fig. 1 (a), Fig. 1 (b), Fig. 1 (c), Fig. 1 (a) is depicted as the plan structure schematic diagram of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET.Fig. 1 (b) is depicted as Fig. 1 (a) along the sectional structure schematic diagram of X-X ' direction.Fig. 1 (c) is depicted as Fig. 1 (a) along the sectional structure schematic diagram of Y-Y ' direction.Described double-deck isolation vertical stack formula semiconductor nanowires MOSFET 1 comprises Semiconductor substrate 10, the first semiconductor nanowires MOSFET 11, the second semiconductor nanowires MOSFET12, be arranged on the spacer medium layer 13 between described the first semiconductor nanowires MOSFET 11 and described the second semiconductor nanowires MOSFET12, be arranged on the oxygen buried layer 14 between described the first semiconductor nanowires MOSFET 11 and described Semiconductor substrate 10, be arranged on the first source area 110 of described the first semiconductor nanowires MOSFET 11, the first insulating medium layer 113 between the first drain region 111 and first grid polar region 112, be arranged on the second source area 120 of described the second semiconductor nanowires MOSFET 12, the second insulating medium layer 123 between the second drain region 121 and second gate polar region 122, be arranged between described spacer medium layer 13 and described oxygen buried layer 14 and be positioned at described the first semiconductor nanowires MOSFET 11 1 sides and with described the first source area 110, the 3rd insulating medium layer 114 that the first drain region 111 and first grid polar region 112 are connected, with described the 3rd insulating medium layer 114 be towards arrange and with described the second source area 120, the 4th insulating medium layer 124 that the second drain region 121 and second gate polar region 122 connect, and be separately positioned on described spacer medium layer 13 and described the first source area 110, the first conductive layer 115 between the first drain region 111 and first grid polar region 112 and be separately positioned on the second source area 120, second conductive layer 125 that differs from described spacer medium layer 13 1 side of the second drain region 121 and second gate polar region 122.
Refer to Fig. 2, and in conjunction with consulting Fig. 1 (a), Fig. 1 (b) and Fig. 1 (c), Figure 2 shows that the perspective view of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET 1.Described the first semiconductor nanowires MOSFET 11 further comprise laterally through described first grid polar region 112 and be arranged on described the first source area 110 and described the first drain region 111 between the first semiconductor nanowires group 116.Wherein, described the first semiconductor nanowires group 116 comprises 3 the first semiconductor nanowires 1161 that are the setting of vertical stack formula.Described the first semiconductor nanowires MOSFET 11 also comprises and encircles the first semiconductor nanowires 1161 outsides the first grid oxide layer 117 between described the first semiconductor nanowires 1161 and described first grid polar region 112 that is arranged on described the first semiconductor nanowires group 116.
Please continue to refer to Fig. 2, and in conjunction with consulting Fig. 1 (a), 1 (b), Fig. 1 (c), the second semiconductor nanowires MOSFET 12 of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET 1 further comprise laterally through described second gate polar region 122 and be arranged on described the second source area 120 and described the second drain region 121 between the second semiconductor nanowires group 126.Wherein, described the second semiconductor nanowires group 126 comprises 3 the second semiconductor nanowires 1261 that are the setting of vertical stack formula.Described the second semiconductor nanowires MOSFET 12 also comprises encircling and is arranged on the second semiconductor nanowires 1261 of described the second semiconductor nanowires group 126 and the second gate oxide layer 127 between described second gate polar region 122.Described the first semiconductor nanowires group 116 is spatially stacked with described the second semiconductor nanowires group 126, and has respectively the cross section structure of circle, horizontal track type or longitudinal racetrack.
The width perpendicular to described the first semiconductor nanowires 1161 of described the first source area 110, the first drain region 111 is greater than the diameter of the first semiconductor nanowires 1161, the width perpendicular to the second semiconductor nanowires 1261 of described the second source area 120, the second drain region 121 is greater than the diameter of the second semiconductor nanowires 1261, so the roomy fin-shaped in thin two ends in the middle of being when the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET 1 overlooks.If, the first semiconductor nanowires MOSFET 11 is NMOSFET, the second semiconductor nanowires MOSFET 12 is PMOSFET, can make the contact hole of the second semiconductor nanowires MOSFET 12 shorter, thereby the contact hole resistance value of the second semiconductor nanowires MOSFET 12 is less, and then further improve the electric property of the second semiconductor nanowires MOSFET 12.So in the present invention preferably, described the first semiconductor nanowires MOSFET 11 is NMOSFET, described the second semiconductor nanowires MOSFET 12 is PMOSFET.Apparently, it is PMOSFET that the present invention can adopt the first semiconductor nanowires MOSFET 11 equally, the structural design that the second semiconductor nanowires MOSFET 12 is NMOSFET.
The first insulating medium layer 113 is being set to avoid the phase mutual interference between the first source area 110, the first drain region 111 and first grid polar region 112 between the first source area 110, the first drain region 111 and first grid polar region 112.The second insulating medium layer 123 is being set to avoid the phase mutual interference between the second source area 120, the second drain region 121 and second gate polar region 122 between the second source area 120, the second drain region 121 and second gate polar region 122.Between the first semiconductor nanowires MOSFET 11 and Semiconductor substrate 10, oxygen buried layer 14 is set, by described the first semiconductor nanowires MOSFET 11 and described Semiconductor substrate 10 isolation, effectively reduces leakage current, thereby improve device performance.
Refer to Fig. 2, and in conjunction with consulting Fig. 3, Figure 3 shows that the perspective view through the formed complete field-effect transistor of follow-up semiconductor preparing process.Described the first semiconductor nanowires MOSFET11 can draw electrode by the 4th insulating medium layer 124 from the first conductive layer 115, to form respectively the first source electrode 118a, the first drain electrode 118b and first grid 119.Described the second semiconductor nanowires MOSFET 12 can draw electrode by the second conductive layer 125 being positioned on the second source area 120, the second drain region 121 and second gate polar region 122, to form respectively the second source electrode 128a, the second drain electrode 128b and second grid 129.
In sum, the first semiconductor nanowires MOSFET of the double-deck isolation of the present invention vertical stack formula semiconductor nanowires MOSFET and the second semiconductor nanowires MOSFET pass through spacer medium interlayer every, can completely independently carry out process debugging, and device integrated level is high.Simultaneously, the present invention adopts the first semiconductor nanowires MOSFET to have the electric property that structural design that vertical stack formula the first semiconductor nanowires group and the second semiconductor nanowires MOSFET have vertical stack formula the second semiconductor nanowires group is further improved field-effect transistor, increase at double device current driving force, and be applicable to forward position nano-device technical field.
Those skilled in the art all should be appreciated that, in the situation that not departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (6)
1. a double-deck isolation vertical stack formula semiconductor nanowires MOSFET, is characterized in that, described double-deck isolation vertical stack formula semiconductor nanowires MOSFET comprises:
Semiconductor substrate;
The first semiconductor nanowires MOSFET, there is the first source area, the first drain region and first grid polar region, and be formed in described Semiconductor substrate, described the first semiconductor nanowires MOSFET further comprise laterally through described first grid polar region and be arranged on described the first source area and described the first drain region between the first semiconductor nanowires group, described the first semiconductor nanowires group comprises the first semiconductor nanowires that is the setting of vertical stack formula, described the first semiconductor nanowires MOSFET also comprises and encircles the first semiconductor nanowires outside the first grid oxide layer between described the first semiconductor nanowires and described first grid polar region that is arranged on described the first semiconductor nanowires group,
The second semiconductor nanowires MOSFET, there is the second source area, the second drain region and second gate polar region, and be formed in described Semiconductor substrate, described the second semiconductor nanowires MOSFET further comprise laterally through described second gate polar region and be arranged on described the second source area and described the second drain region between the second semiconductor nanowires group, described the second semiconductor nanowires group comprises the second semiconductor nanowires that is the setting of vertical stack formula, described the second semiconductor nanowires MOSFET also comprises and encircles the second semiconductor nanowires outside the second gate oxide layer between described the second semiconductor nanowires and described second gate polar region that is arranged on described the second semiconductor nanowires group,
Spacer medium layer, is arranged between described the first semiconductor nanowires MOSFET and described the second semiconductor nanowires MOSFET;
Oxygen buried layer, is arranged between described the first semiconductor nanowires MOSFET and described Semiconductor substrate;
The first insulating medium layer, is arranged between the first source area, the first drain region and the first grid polar region of described the first semiconductor nanowires MOSFET;
The second insulating medium layer, is arranged between the second source area, the second drain region and the second gate polar region of described the second semiconductor nanowires MOSFET;
The 3rd insulating medium layer, is arranged between between described spacer medium layer and described oxygen buried layer and be positioned at described the first semiconductor nanowires MOSFET mono-side and be connected with described the first source area, the first drain region and first grid polar region;
The 4th insulating medium layer, is towards arranging and being connected with described the second source area, the second drain region and second gate polar region with described the 3rd insulating medium layer;
The first conductive layer, is separately positioned between described spacer medium layer and described the first source area, the first drain region and first grid polar region; And,
The second conductive layer, is separately positioned on described spacer medium layer one side of differing from of the second source area, the second drain region and second gate polar region;
Described the first semiconductor nanowires group and described the second semiconductor nanowires group are spatially stacked;
Wherein, described the first semiconductor nanowires MOSFET draws electrode by the 4th insulating medium layer from the first conductive layer, forms respectively the first source electrode, the first drain electrode and first grid; Described the second semiconductor nanowires MOSFET draws electrode by the second conductive layer being positioned on the second source area, the second drain region and second gate polar region, forms respectively the second source electrode, the second drain electrode and second grid.
2. bilayer as claimed in claim 1 is isolated vertical stack formula semiconductor nanowires MOSFET, it is characterized in that, described the first semiconductor nanowires group comprises a plurality of the first semiconductor nanowires that vertical stack formula arranges that are, and described the second semiconductor nanowires group comprises a plurality of the second semiconductor nanowires that vertical stack formula arranges that are.
3. double-deck isolation vertical stack formula semiconductor nanowires MOSFET as claimed in claim 1, is characterized in that, described the first semiconductor nanowires MOSFET is NMOSFET, and described the second semiconductor nanowires MOSFET is PMOSFET.
4. double-deck isolation vertical stack formula semiconductor nanowires MOSFET as claimed in claim 1, is characterized in that, described the first semiconductor nanowires MOSFET is PMOSFET, and described the second semiconductor nanowires MOSFET is NMOSFET.
5. bilayer as claimed in claim 1 is isolated vertical stack formula semiconductor nanowires MOSFET, it is characterized in that, described the first semiconductor nanowires group and described the second semiconductor nanowires group have respectively the cross section structure of circle, horizontal racetrack or longitudinal racetrack.
6. the bilayer as described in claim as arbitrary in claim 1-5 is isolated vertical stack formula semiconductor nanowires MOSFET, it is characterized in that, the width perpendicular to described the first semiconductor nanowires of described the first source area, the first drain region is greater than the diameter of the first semiconductor nanowires, and the width perpendicular to the second semiconductor nanowires of described the second source area, the second drain region is greater than the diameter of the second semiconductor nanowires.
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| CN104282560B (en) * | 2013-07-02 | 2018-07-27 | 中国科学院微电子研究所 | Method for manufacturing cascade stacked nanowire MOS transistor |
| US11404325B2 (en) | 2013-08-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
| CN105552227B (en) * | 2016-02-03 | 2018-06-22 | 苏州大学 | Fin carbon nanotube field-effect transistor and preparation method thereof |
| CN107819037B (en) * | 2017-12-07 | 2023-10-27 | 苏州大学 | Fin type field effect transistor using carbon nano tube as conductive groove and preparation method thereof |
| CN112420615B (en) * | 2020-12-04 | 2022-02-08 | 南京大学 | Semiconductor structure preparation method and semiconductor device |
| US11777034B2 (en) | 2021-09-07 | 2023-10-03 | International Business Machines Corporation | Hybrid complementary field effect transistor device |
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